Wednesday, 13 May 2015 2.00pm – 4.00pm
(Duration: 2 hours)
DEGREES OF MSc, MSci, MEng, BEng, BSc, MA and MA (Social Sciences)
Systems and Networks
Answer ALL 3 Questions
This examination paper is worth a total of 60 marks
INSTRUCTIONS TO INVIGILATORS
Please collect all exam question papers and exam answer scripts and retain for school to collect. Candidates must not remove exam question papers.
1. (a)
What number does the codeword $FD represent in:
- 8-bit unsigned code
- 8-bit two’s complement code
Explain your reasoning in each case.
(b) Using a 32-bit binary word give the ranges of numbers that can be represented using: (a) an unsigned; and (b) a two’s complement code. (You may express the answers in the form of powers of 2.)
[4]
[2]
[3]
[6]
[5]
(c) Explain how a 32-bit numeric codeword would be stored in memory in a Sigma16 system? How would it be stored in a 6811 system?
(d) A Sigma16 system has two arrays, X and Y, of 4 16-bit signed numbers in memory. Write an assembly language program to form a third array, Z, whose ith element, zi, is formed by multiplying the ith elements of X and Y together, i.e. zi = xi* yi
(e) With a view to maximising efficiency, modify your program in (d) to sum the elements of Z and put the result in a variable called SPRDT.
For reference, this is part of the instruction set of the Sigma16 CPU.
lea load store add sub mul div cmplt cmpeq cmpgt jumpf jumpt jal trap jump
Rd, x[Ra] Rd, x[Ra] Rd, x[Ra] Rd,Ra,Rb Rd,Ra,Rb Rd,Ra,Rb Rd,Ra,Rb Rd,Ra,Rb Rd,Ra,Rb Rd,Ra,Rb Rd, x[Ra] Rd, x[Ra] Rd, x[Ra] Rd,Ra,Rb x[Ra]
Rd:= x +Ra
Rd:= mem[x +Ra] mem[x +Ra]:=Rd
Rd:= Ra+Rb
Rd:= Ra-Rb
Rd:= Ra*Rb
Rd:= Ra/Rb
Rd:= Ra<Rb
Rd:= Ra=Rb
Rd:= Ra>Rb
If Rd=0 then PC:=x+Ra If Rd<>0 then PC:=x+Ra Rd:= pc, pc: =x +Ra PC:= interrupt handler PC:= x +Ra
CONTINUED OVERLEAF
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2. (a)
In the memory hierarchy, explain how cache memory works. Clearly define the concepts of a cache miss, cache hit and replacement policy
(b) What does the following Sigma16 program do?
(c) How many cycles are in the main loop?
- (d) If a memory cycle takes 10ns, how long would this program take to execute?
- (e) If a cache is introduced, how many hits will there be?
- (f) If a cache cycle takes 1ns, how long would this program take to execute?
- (g) Does it make sense to cache memory mapped I/O locations? Explain your answer.
[2] [2] [3] [2] [2] [3]
[6]
; Initialise registers
LEA R1,1[R0] LEA R2,1[R0] LOAD R3,n[R0] LEA R4,1[R0]
; For loop follows
FORLOOP CMPGT R5,R2,R3 JUMPT R5,OUT[R0]
MUL R4,R4,R2 ADD R2,R2,R1 JUMP FORLOOP[R0]
; Exit Loop and store result.
OUT STORE R4,x[R0] TRAP R0,R0,R0
; Data Area
n DATA 5 x DATA 0
; R1 = 1 (constant) ; i = 1
; R3 = n
; x = 1
; IF i>n
; EXIT Loop ; x = x*i
; i = i + 1
; Loop again
; Store x ; Finish
CONTINUED OVERLEAF
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3. (a)
What is the difference between a circuit-switched and packet-switched network. Explain the role of the nodes in each case.
[4]
[8]
[4]
[4]
(b) Describe the layered structure of the Internet communications system, identifying the layers and their functions.
(c) In a packet-switched network packets occasionally arrive in the wrong order or are lost completely.
Explain how each of these problems might arise and how the communications system would fix them
(d) Explain how the problems discussed in (c) would impact the following user applications:
i. ii.
A file transfer application
A music streaming application
END OF QUESTION PAPER
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