MIPS计算机体系结构代写

Which of these expressions can bring to an overflow? Select all that apply. a + b, with a > 0 and b > 0

a + b , with a > 0 and b > 0

a + b, with a < 0 and b > 0 a – b, with a < 0 and b < 0

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Question 2​1 pts If you have this code:

    jal Procedure
    addi $t1, $v0, 1

Which instruction will be in the $ra register after the jal instruction is executed?

addi $a2, $t2, 1 add $a1, $t1, $zero

add $a1, $t1, $zero

addi $a2, $t2, 1

jal Procedure addi $t1, $v0, 1

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Question 3​1 pts
Immagine that you have a branch instruction with an offset equal to

10​10​(0000000000001010​2​), and the PC contains the address 30000​10 If the branch is taken, which will be the new address stored in the PC?

30040

30024
30044
30014

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Question 4​1 pts
Which of these instructions could cause a Data Hazard? Select all that apply.

Remember: The instructions are intended “stand alone”; it’s not a sequence of instructions from the same program.

sub

lw add jal

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Question 5​1 pts
Which of these instructions could cause a Control Hazard? Select all that

apply

sub lw beq bne

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Question 6​1 pts

If you have a “lw” instruction, which will be the first pipeline register to contain the retrieved information?

ID/EX IF/ID EX/MEM MEM/WB

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Question 7​1 pts
Do we have a Data Hazard in this situation?

EX/MEM.RegisterRd = $t1 (address of register t1)

ID/EX.RegisterRd = $t2 (address of register t2)

ID/EX.RegisterRt = $t3 (address of register t3)

MEM/WB.RegisterRd = $t1 (address of register t1)

Yes No

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Question 8​1 pts
Do we have a Data Hazard in this case?

EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM.RegisterRd = $zero

Yes No

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Question 9​1 pts
For a 2-way set associative cache with a 32-bit address, the following bits of

the address are used to access the cache: Tag: 31-10
Index: 9-5
Block Offset: 4-0

What is the block size (in words)? 2

16 4 8

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Question 10​1 pts
If a 16-way set-associative cache has 32 bit words, 2 words per block and

8192 sets, how big is the cache in bytes?

524,288 (2^19) 1,048,576 (2^20) 262,144 (2^18) 2,097,152 (2^21)

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Question 11​1 pts

A 256kiB (2^18 bytes) cache has a block size of 32 bytes and is 32-way set-associative.

How many bits of a 32-bit address will be in the Tag, Index, and Bock Offset? Tag: 19; Index: 8; Offset: 5

Tag: 14; Index: 13; Offset: 5 Tag: 18; Index: 9; Offset: 5 Tag: 19; Index: 9; Offset: 4

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Question 12​1 pts
For a 2-way set associative cache, the following number of bits for each field

of the 32-bit address are used to access the cache: Tag: 17 bits
Index: 9 bits
Block Offset: 6 bits

What is the block size (in words)? 8 words

4 words 16 words 32 words

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Question 13​1 pts
For a 4-way set associative cache, the following number of bits for each field

of the 32-bit address are used to access the cache: Tag: 17 bits
Index: 8 bits
Block Offset: 7 bits

How many sets are present in this cache?

256

32 128 64

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Question 14​1 pts
A 16kiB (2​14​ bytes) cache has a block size of 8 bytes and is 2-way

set-associative.
How many bits of a 32-bit address will be in the Tag, Index, and Bock Offset?

Tag: 20; Index: 9; Block Offset: 3 Tag: 19; Index: 10; Block Offset: 3 Tag: 18; Index: 10; Block Offset: 4 Tag: 18; Index: 11; Block Offset: 3

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Question 15​1 pts
Given a 2-way set associative cache with this configuration: Index: 10 bits

Block Offset: 6 bits

a. How many words are in a block?

b. How many bytes of data does this cache hold? a) 16 words per block; b) 65536 bytes (2^16)

a) 8 words per block; a) 65536 bytes (2^16)
a) 16 words per block; b) 131072 bytes (2^17) a) 16 words per block; b) 32768 bytes (2^15)

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Question 16​1 pts
If you have this list of actual prediction from the same branch instruction, that

is, the actual outcome of the branch instruction: T

T

T NT T NT T NT

Where T is for Taken, and NT for Not Taken.

What is the prediction accuracy using 3-bit Dynamic Branch Prediction starting from NT (100)?

Key:
000 – Taken 001 – Taken

10. 010  – Taken
11. 011  – Taken

100. 100  – Not Taken
101. 101  – Not Taken

110. 110  – Not Taken
111. 111  – Not Taken

3/8 4/8 5/8 2/8 6/8