CSCI2467: Systems Programming Concepts
Slideset 5: Examining Programs at the Machine Level Source: CS:APP Chapter 3, Bryant & O’Hallaron
Instructor: Matthew Toups
Spring 2019
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Announcements
Datalab due last night
grace day applied automatically by AutoLab
copying code or comments without citation from websites/classmates/github/stackexchange/etc is plagiarism
copying with a citation but not explained in your own words will receive no credit, but may save you from disciplinary proceedings
things like uploading/downloading files and using the command line are crucial to your future as a CS student
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
datalab is done!
Bomblab begins!
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Announcements
Bomblab writeup passed out today (due Friday Feb 22)
detailed tutorial on gdb and other important tools on Friday lab session
don’t explode your bomb!
Scoreboard on AutoLab is automatically updated (no handing in)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Class updates
1 History of Intel CPU architecture
Intel processor “family”
The move to 64-bit wide architecture
Summary
2 C, assembly, and machine code Definitions
Compiling C Disassembling / debugging Registers
3 Arithmetic & Logical operations Instructions
Example
4 Memory and addressing Pointers!
Call-by-value
Swapping by reference
5 Bomblab
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Intel x86 Processors
Dominate laptop/desktop/server market today (but not mobile)
Evolutionary design
– Backwards compatible all the way back to 8086 (1978)
– Added more features over time
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Intel x86 Processors
Complex instruction set computer (CISC)
– Many different instructions with many different formats
– … but, only small subset encountered with most programs
– Hard to match performance of Reduced Instruction Set Computer (RISC)
– … but Intel has done just that
(in terms of speed, less so for low power)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Intel x86 Processors
Name Date Transistors MHz Notes
8086
386
1978 29k 5-10
1985 275k 16-33
first 16-bit Intel CPU, basis for IBM PC & DOS. 1MB address space
first 32-bit Intel CPU, re- ferred to as IA32. Added “flat addressing” – capable of running Unix OSes
First 64-bit Intel x86 CPU (x86-64)
2004 125M 2800-3800
2006 291M 1060-3500
2008 731M 1700-3900 4 cores per CPU
Pentium 4E
Core 2
Core i7
Xeon E5-2697v2 2013 4.3B 2700 12 cores per CPU Xeon E5-2699v4 2016 7.2B 2200 22 cores per CPU
First multi-core Intel CPU
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Carnegie Mellon
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 6
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Intel x86 processor evolution
Intel x86 Processors, cont.
Machine Evolution
▪ 386 1985 0.3M ▪ Pentium 1993 3.1M ▪ Pentium/MMX 1997 4.5M ▪ PentiumPro 1995 6.5M ▪ Pentium III 1999 8.2M ▪ Pentium 4 2000 42M ▪ Core 2 Duo 2006 291M ▪ Core i7 2008 731M ▪ Core i7 Skylake 2015 1.9B
Added Features
▪ Instructions to support multimedia operations
▪ Instructions to enable more efficient conditional operations ▪ Transition from 32 bits to 64 bits
▪ More cores
Carnegie Mellon
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 7
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Intel x86 processors, process technology
Intel x86 Processors, cont.
Past Generations ▪1stPentiumPro 1995 ▪ 1st Pentium III 1999 ▪ 1st Pentium 4 2000 ▪ 1st Core 2 Duo 2006
Process technology
600nm 250 nm 180 nm
65 nm
Process technology dimension = width of narrowest wires (10 nm ≈ 100 atoms wide)
Recent & Upcoming Generations
1. Nehalem 2008
2. Sandy Bridge 2011
3. Ivy Bridge 2012
4. Haswell 2013
5. Broadwell 2014
6. Skylake 2015
7. Kaby Lake 2016
8. Coffee Lake 2017
▪ Cannon Lake 2019?
45 nm 32 nm 22 nm 22 nm 14 nm 14 nm 14 nm 14 nm 10 nm
2018 CPU State of the Art Carnegie Mellon Intel “Coffee Lake” microarchitecture
Mobile Model: Core i7 ▪ 2.2-3.2 GHz
Server Model: Xeon ▪ Integrated graphics
▪ Multi-socket enabled ▪ 3.3-3.8 GHz
▪ 80-95 W
▪ 45 W
Desktop Model: Core i7 ▪ Integrated graphics
▪ 2.4-4.0 GHz
▪ 35-95 W
2018 State of the Art: Coffee Lake
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 8
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
E
x86 clones: Advanced Micro Devices (AMD)
Historically AMD has followed just behind Intel
– a little slower, a lot cheaper
Then in early 2000s …
– AMD recruited top designers from Digital Equipment Corp
and other defunct CPU makers
– Built Opteron: tough competitor to Pentium 4
– Developed x86-64 extension (64 bit x86)
In recent Years…
– Intel got its act together, retook the lead
– AMD returned to 2nd place . . . until recently?
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
64-bit history
2001: Intel attempts radical shift from IA32 to IA64
– Totally different architecture (Itanium)
– Executes IA32 code only as legacy
– Performance disappointing
2003: AMD steps in with evolutionary solution
– x86-64 (also known as AMD64)
Intel felt obligated to focus on IA64
– Hard to admit mistake or that AMD is better
2004: Intel announces EM64T extension to IA32
– Extended Memory 64-bit technology
– Almost identical to amd64!
Since then: all but low-end x86 CPUs support x86-64
– but lots of code still runs in 32-bit mode
– 32-bit CPUs still very widely used (embedded, mobile)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Coverage in CSCI2467
x86-64 is now standard
CS:APP 3rd edition focuses on x86-64 – (web asides on IA32 available)
We will only cover x86-64
(extension of x86, will be easy for 2450 students to pick up)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Class updates
1 History of Intel CPU architecture
2 C, assembly, and machine code Definitions
Compiling C Disassembling / debugging Registers
3 Arithmetic & Logical operations
4 Memory and addressing
5 Bomblab
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Some definitions
Architecture (also ISA: instruction set architecture)
The parts of a processor design that one needs to understand
to write assembly/machine code.
– Examples: instruction set specification, registers
Microarchitecture
Implementation of the architecture.
– Examples: cache sizes and core frequency
Code forms:
– Machine code: byte-level programs that a processor executes
– Assembly code: a text representation of machine code
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Some definitions
Example Instruction Set Architectures (ISAs):
– Intel:
x86 (IA32)
Itanium (64-bit, never mass produced)
x86-64 (64-bit, created by AMD and copied by Intel)
– ARM (Acorn RISC Machine):
used in almost all mobile phones designed for low power consumption
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Assembly/Machine Code view
Carnegie Mellon
Assembly/Machine Code View
CPU
PC
Registers
Addresses
Data
Condi�on Codes
Programmer-Visible State § PC: Program counter
§ Address of next instruc�on
§ Called “RIP” (x86-64) § Register file
§ Heavily used program data § Condi�on codes
§ Store status informa�on about most recent arithme�c or logical opera�on
§ Used for condi�onal branching
§ Memory
§ Byte addressable array
§ Code and user data
§ Stack to support procedures
Instruc�ons
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 12
Memory
Code Data Stack
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Turning C into Object Code
Carnegie Mellon
Turning C into Object Code
§ Code in files p1.c p2.c
§ Compile with command: gcc –Og p1.c p2.c -o p
§ Use basic op�miza�ons (-Og) [New to recent versions of GCC] § Put resul�ng binary in file p
text
text binary
binary
C program (p1.c p2.c)
Compiler (gcc –Og -S)
Asm program (p1.s p2.s)
Assembler (gcc or as)
Object program (p1.o p2.o)
Linker (gcc or ld)
Executable program (p)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 13
Sta�c libraries (.a)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Compiling into Assembly
long plus (long x, long y); void sumstore(long x,long y,
{
}
long *dest)
long t = plus(x,y); *dest = t;
Using:
gcc -Og -S sum.c -masm=intel
Will get very different results on other systems: Mac OS X, Windows, other compilers, even gcc with other flags
sumstore :
push rbx
mov rbx, rdx
call plus
mov QWORDPTR [rbx], rax pop rbx
ret
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Assembly characteristics: data types
“integer” data of 1,2,4, or 8 bytes
– data values
– addresses (untyped pointers)
Floating point data of 4, 8, or 10 bytes
Code: byte sequences encoding series of instructions No aggregate types such as arrays or structures
– Just contiguously allocated bytes in memory
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Assembly characteristics: operations
Operations are assembly instructions, which can:
Perform arithmetic function on register or memory data
Transfer data between memory and register
– load data from memory into register
– store register data into memory
Transfer control
– unconditional jumps to/from procedures
– conditional branches
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Object code (binary)
400532: 0x53 0x48 0x89 0xd3 0xe8 0xf2
0xff 0xff 0xff 0x48 0x89 0x03 0x5b 0xc3
Assembler:
– translates .s into .o
– binary encoding of each instruction
– nearly-complete image of executable program
– missing linkages between code in different files
Linker:
– resolves references between files
– combined with static run-time libraries
(e.g. printf)
– some libraries are dynamically linked
(linking occurs when program begins execution)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Disassembling object code
Disassembler: objdump -M intel -d sum
useful tool for examining object code
analyzes bit pattern of series of instructions
produces approximate rendition of assembly code
can be run on either a.out (complete executable) or .o file
0000000000400532
push rbx
mov rbx,rdx
call 40052d
ret
400533: 48 400536: e8 40053b: 48 40053 e : 5b 40053 f : c3
89 d3
f2 ff ff ff 89 03
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Machine instruction example
∗dest = t;
mov QWORD PTR [rbx],rax
C code: store value t where designated by dest
Assembly:
move 8-byte value to memory (“quad word”)
Operands:
t: register rax
dest: register rbx *dest: memory at [rbx]
Object code: 3-byte instruction stored at address 0x40053b
40053b: 48 89 03
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Disassembly with gdb
gdb commands:
(gdb) disassemble sumstore
Dump of assembler code for function sumstore:
0x0000000000400532 <+0>: 0x0000000000400533 <+1>: 0x0000000000400536 <+4>: 0x000000000040053b <+9>: 0x000000000040053e <+12>: 0x000000000040053f <+13>: ret
Examine the 14 bytes starting at location sumstore: (gdb) x/14xb sumstore
push rbx
mov rbx , rdx
call 0x40052d
0x400532
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
GDB 166 CHAPTER3. MACHINE-LEVELREPRESENTATIONOFCPROGRAMS Crucial tool for our labs! See CSAPP3e for examples (p.280 Figure 3.39)
Command Starting and Stopping
quit run kill
Breakpoints
break sum
break *0x80483c3 delete 1
delete
Execution
Effect
Exit GDB
Run your program (give command line arguments here) Stop your program
Set breakpoint at entry to function sum Set breakpoint at address 0x80483c3 Delete breakpoint 1
Delete all breakpoints
Execute one instruction
Execute four instructions
Like stepi, but proceed through function calls Resume execution
Run until current function returns
Disassemble current function
Disassemble function sum
Disassemble function around address 0x80483b7 Disassemblecodewithinspecifiedaddressrange Print program counter in hex
Print contents of %eax in decimal Print contents of %eax in hex
Print contents of %eax in binary
Print decimal representation of 0x100 Print hex representation of 555
Print contents of %ebp plus 8 in hex Printintegerataddress0xbffff890
Print integer at address %ebp + 8
Examine two (4-byte) words starting at address 0xbffff890 Examine first 20 bytes of function sum
Information about current stack frame Values of all the registers
Get information about GDB
stepi stepi nexti continue finish
Examining code
4
disas
disas
disas disas0x80483b70x80483c7 print /x $eip
Examining data
print $eax
print /x $eax
print /t $eax
print 0x100
print /x 555
print /x ($ebp+8) print*(int*)0xbffff890 print *(int *) ($ebp+8) x/2w 0xbffff890
x/20b sum
Useful information
info frame info registers help
sum 0x80483b7
Figure 3.26: Example GDB Commands. These examples illustrate some of the ways GDB supports debug-
ging of machine-level programs.
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
What can be disassembled?
Anything that can be interpreted as executable code disassembler examines bytes and reconstructs assembly
What Can be Disassembled?
Carnegie Mellon
% objdump -d WINWORD.EXE
WINWORD.EXE: file format pei-i386
No symbols in “WINWORD.EXE”.
Disassembly of section .text:
30001000 <.text>:
30001000:
30001001:
30001003:
30001005:
3000100a:
55 push %ebp
8b ec mov
%esp,%ebp
Reverse engineering forbidden by
6a ff push
68M9i0cro10so0�0E3n0d pUussehr Lic$e0nxs3e0A00g1r0e9e0ment
$0xffffffff
68 91 dc 4c 30 push $0x304cdc91
¢ Anything that can be interpreted as executable code
Classupd¢at esDHisistaorsysoefmInteblClePUraercxhaitemctuirneeCs,abssyemteblys,anndmdacrheinceocondestAruritchmtsetiacs&sLeogmicablolpyersatoiounsrcMeemoryandadd
Legacy: IA32 (x86) registers
Origin
%ecx %cx
%ch
%al
%cl
(mostly obsolete)
%eax %ax
%edx
%dx
16-bit virtual registers
(backwards compa�bility)
and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on
Bryant 24
%ah
%ebx %bx
%edi %di
%esp
%sp
%ebp %bp
%dh
accumulate
counter
data
base
source index
destination index
stack
pointer
base pointer
%bh
%dl
%bl
%esi %si
Some History: IA32 Registers
general purpose
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
x86-64 integer registers Carnegie Mellon
inxtr8od6uc-i6ng4: 6I4n-btietsgweidre,Ranedg8isatddeitriosnal general purpose registers
%rax
%rbx
%rcx
%rdx
%rsi
%rdi
%rsp
%rbp
%eax
%ebx
%ecx
%edx
%esi
%edi
%esp
%ebp
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on 23
%r8
%r9
%r10
%r11
%r12
%r13
%r14
%r15
%r8d
%r9d
%r10d
%r11d
%r12d
%r13d
%r14d
§ Can reference low-order 4 bytes (also low-order 1 & 2 bytes)
%r15d
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Class updates
1 History of Intel CPU architecture
2 C, assembly, and machine code
3 Arithmetic & Logical operations Instructions
Example
4 Memory and addressing
5 Bomblab
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Arithemetic operations
Two operand instructions
Pay attention to order of operands
No distinction between signed & unsigned. (why not?)
Format Operands add dest,src sub dest,src imul dest,src sal dest,src sar dest,src shr dest,src xor dest,src and dest,src or dest,src
Computation
dest = dest + src dest = dest – src dest = dest * src dest = dest << src dest = dest >> src dest = dest >> src dest = dest ∧ src dest = dest & src dest = dest | src
(also shl) (arithmetic) (logical)
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Arithemetic operations
One operand instructions
Format Operand inc dest
dec dest
neg dest
Computation dest = dest + 1 dest = dest – 1 dest = – dest dest = ̃dest
not dest
See CSAPP3e for more on these operations.
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
An arithmetic example
How would we write this in x86-64 assembly?
Assume x is stored in register rdi:
long m12(long x) {
return x*12; }
Perhaps this?
Nope: This is not how a compiler “thinks”!
imul rax , rdi , 12
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Address computation instruction
lea dst src
– src is address mode expression
– set dst to address denoted by expression
Uses:
– Computing addresses without a memory reference
(e.g. translation of p = & x [i];)
– Computing arithmetic expressions of the form x + k ∗ y
k = 1, 2, 4, or 8
lea rax, [rdi+rdi*2] # rax <- x+x*2 sal rax, 2 # rax <- rax<<2
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Address computation instruction
Compilers love lea instruction
Fast way to compute x + k ∗ y and similar
long m12(long x) {
return x*12; }
Compiles to:
m12:
lea rax, [rdi+rdi*2] # rax <- x+x*2 sal rax, 2 # rax <- rax<<2
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Arithmetic expression example
long arith
(long x,long y,long z) {
long t1 = x+y;
long t2 = z+t1;
long t3 = x+4;
long t4 = y * 48; long t5 = t3 + t4; long rval = t2 * t5; return rval;
}
arith:
lea rax, [rdi+rsi] add rax , rdx
lea rcx, [rsi+rsi*2] sal rcx, 4
lea rcx, [rdi+4+rcx] imul rax, rcx
ret
Interesting instructions:
lea: address computation sal: shift left
imul: multiplication
(only used once!)
arith:
lea rax, [rdi+rsi] # t1
Class updates History of Intel CPU architecture C, assembly, and macahdinedcode Arraithxm,etic r&dLxogical operations M#emtor2y and add lea rcx, [rsi+rsi*2]
Machine Programming I: Summary
History of Intel processors and architectures
- Evolutionary design leads to many quirks and artifacts
C, assembly, machine instructions
- New forms of visible state: program counter, registers, ...
- Compiler must transform statements, expressions, procedures into low-level instruction sequences
Assembly basics: registers, operands, move
Arithmetic
- C compiler will figure out different instruction combinations to carry out computation
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Class updates
1 History of Intel CPU architecture
Intel processor “family”
The move to 64-bit wide architecture Summary
2 C, assembly, and machine code Definitions
Compiling C Disassembling / debugging Registers
3 Arithmetic & Logical operations Instructions
Example
4 Memory and addressing Pointers!
Call-by-value
Swapping by reference
5 Bomblab
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
C Code
int x; int *p;
x = 99; p = &x;
Pointers in C
//holds a value
//holds an address of a value
Operator Function
& “address of”
Memory
M1 M *p p
C Code
int x;
x
int *p;
x = 99; p = &x;
Memory
&x &p *x
99 M1
XX XX XX XX
//holds a value
//holds an address of a value (hopefully)
Segmentation Fault
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add 99 M1 XX XX XX XX
2 99
Pointers in C
C pointer syntax
Operator Function
* pointer / dereference & “address of”
int x = 1, y = 2, z[10];
int *ip; /* ip is a pointer to int */
ip = &x; /* ip now points to x */
y = *ip; /* y is now 1 */
*ip = 0; /* x is now 0 */
ip = &z[0]; /* ip now points to z[0] */
Source: K&R Chapter 5
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Pointers illustrated
Imagine memory as a long block of boxes that store data. Each box is labeled with an address. A pointer is a variable that holds a particular address. An array is a group of contiguous boxes that can be accessed by their index values.
Here we declare p and q as pointers that will hold the addresses of int variables, and x as an ordinary int variable.
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
C pointer syntax
Operator Function
* pointer / dereference & “address of”
int x = 1, y = 2, z[10];
int *ip; /* ip is a pointer to int */
ip = &x; /* ip now points to x */
y = *ip; /* y is now 1 */
*ip = 0; /* x is now 0 */
ip = &z[0]; /* ip now points to z[0] */
Source: K&R Chapter 5
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
C pointer syntax
C uses “call-by-value” semantics for function calls
void swap(int x, int y) {
int temp;
temp = x; x = y;
y = temp;
}
Source: K&R Section 5.2
int a=123,b=456; swap(a, b);
This function won’t swap a and b, only copies of the values.
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Addressing example
void swap (long *xp, long *yp)
{
long t0 = *xp; long t1 = *yp; *xp = t1;
*yp = t0;
}
swap:
mov rax, QWORD PTR [rdi] mov rdx, QWORD PTR [rsi] mov QWORD PTR [rdi], rdx mov QWORD PTR [rsi], rax
swap : movq
movq movq movq
ret
(%rdi), %rax (%rsi), %rdx %rdx, (%rdi) %rax, (%rsi)
Called with:
(or in the other “flavor” asm)
long a=123,b=456; swap(&a, &b);
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
Understanding swap()
Carnegie Mello
Understanding Swap() Registers
Memory
void swap
{ (long *xp, long *yp)
long t0 = *xp;
long t1 = *yp;
*xp = t1;
} *yp = t0;
%rdi
%rsi
Register
Value
Register
Value
rdi %rdi rsi%rsi rax%rax rdx %rdx
xp xp ypyp t0t0 t1 t1
movq %rdx, (%rdi) # *xp = t1
movq %rax, (%rsi) # *yp = t0
ret
%rax
%rdx
mov rax,QWORDPTR[rdi] mov rdx,QWORDPTR[rsi]
swap:
mov QWORDPTR [rdi], rdx
movq (%rdi), %rax # t0 = *xp
mov QWORDPTR [rsi], rax
movq (%rsi), %rdx # t1 = *yp
n
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and ad29d Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add mov QWORD PTR [rdi], rdx
n
Understanding Swap() U Understanding swap()
swap: mov mov mov mov
swap:
movq (%rdi), %rax # t0 = *xp
rax, QWORD PTR [rdi]
movq (%rsi), %rdx # t1 = *yp
movq %rdx, (%rdi) # *xp = t1 QWmOoRvqD PT%Rrax[,r(d%ir]si,) r#dx*yp = t0
rdx, QWORD PTR [rsi]
ret
QWORD PTR [rsi], rax
Bry an3d0 O’Hallar
Registers
Memory
Address
123
456
0x120
0x118
0x110
0x108
0x100
%rdi
0x120
%rsi
0x100
%rax
%rdx
swap:
ant and O’Hallaron, Computer Systems: A Programmer’s Perspec�ve, Third Edi�on Bryant
mov rax, QWORD PTR [rdi]
mov rdx, QWORD PTR [rsi]
Class updates
1 History of Intel CPU architecture
Intel processor “family”
The move to 64-bit wide architecture Summary
2 C, assembly, and machine code Definitions
Compiling C Disassembling / debugging Registers
3 Arithmetic & Logical operations Instructions
Example
4 Memory and addressing Pointers!
Call-by-value
Swapping by reference
5 Bomblab
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
lab warmup
get sum.c from 2467 course page
- (go to schedule, link to example code for today)
compile with
- Then run:
- ignore noise at beginning, look for sumstore and plus
compile with optimizations such as gcc −Og and −O3 , compare
launch GNU debugger: gdb ./a.out
breakpoint on sumstore...
commands to try: run, disassemble, x, nexti
see bomblab writeup with info on changing
disassembly-flavor
gcc sum.c
objdump −d a.out −M intel
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add
bomblab
download bomblab from on campus into homedir on
systems-lab
either use classroom terminals, or copy from your computer to systems-lab using scp or sftp
untar, examine with objdump
open with gdb ... may want to change disassembly-flavor to taste
Class updates History of Intel CPU architecture C, assembly, and machine code Arithmetic & Logical operations Memory and add