2019 DCS Lab 3
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Pipeline
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Pipeline
• 優點
– Cycle Time 可以降低，可以增加frequency – 增加硬體Utilization與throughput
• 缺點
– 可能會有hazard – 設計困難
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
𝑛8
• 由多個乘法器組成一個𝑛8 • 基本
n
Critical path
𝑛8
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
IN
in_ valid
OUT
OUT vali
Pipeline 𝑛8
• 嘗試去Pipeline這些乘法器 • Hint: 三個stage就可以
•
Block diagram如下
Critical path
Clk,rst_n
Clk,rst_n
Clk,rst_n
Clk,rst_n
N C T U . E E , Hsinchu, Taiwan
d
VLSI Signal Processing Lab.
Spec
• Pipeline是利用Sequentialcircuit具有clock跟儲存功
能的D Flip-Flop(DFF)。
• Input後跟output前面都必須擋DFF。
• Asynchronousreset.
• Input會給值，在in_valud=1時每個clocknegative edge。
• Output會檢查，在out_valid=1時每個clockpostive edge。
• 禁止用窮舉方式。
• 02_SYN合成電路，cycletime=5ns.
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
pipeline.sv
Input Signal
Bit Width
Definition
clk
1
5 ns Clock
rst_n
1
非同步reset
當reset negedge時 out及out_valid需為0
in
4
in = 1 ~ 15 且不會為0
in_valid
1
in_valid 拉起為1 時in進入，in最後一筆進 入，in_valid降下為0。
Output Signal
Bit Width
Definition
out
32
𝑜𝑢𝑡 = 𝑖𝑛8
out_valid
1
請參考block digram設計，當out_valid = 1 時每個posedge會依”in順序”檢查output。
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Output & Waveform • Waveform
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Command
• tar-xvf~dcsta01/Lab03.tar • Need 02_SYN/01_run_dc Synthesis
without any latch, error timing met
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Appendix
Digital Circuits and Systems(DEE3342) How to Upload Your Design?
Name: Jesse Chen Advisor: Tian-Sheuan Chang 2019.03.20(revised)
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Problems
• The servers in ED415 can not connect to external network for security issues
• It takes too long for students to wait for demo
• We will give you a script to upload your file to us
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Directory Tree Structure
• The following directory of lab and homework will be like this:
– Add 09_upload with 01_upload and 02_download
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Upload Steps
• $ ./01_upload
• Display the file first in green color
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Upload Steps
• Display the deadline for the 1st demo and the 2nd demo
– Get the current time and decide whether it is for 1st demo or the 2nd demo
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Upload Steps
• It will overwrite the file you uploaded before – Input y or n
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.
Download Steps
• You can check your file after uploading
• $ ./02_download [Argument] – $ ./02_download demo1
– $ ./02_download demo2
• Download to 09_upload
N C T U . E E , Hsinchu, Taiwan
VLSI Signal Processing Lab.