Fall ’18 CIS 314 Final A Name: SID:
1. [15] Recall the x86-64 cmpq rA, rB instruction, which sets the condition codes based on rB – rA, but does not otherwise write to registers. Now consider implementing the cmpq instruction for the Y86-64 processor:
a. (10) Describe the functionality of each Y86-64 processor stage in terms of the
icode, ifun, rA, rB, valA, valB, valC, valP, valE, valM, srcA, srcB, dstE, dstM, cnd
signals (you may also use M, R, and PC): IF:
ID: EX: MEM: WB: PC:
b. (5) How many bytes are required to encode this instruction (i.e., based on Y86-64 encoding conventions)? Why?
2. [15] Draw a circuit (using AND, OR, NOT, XOR gates) with inputs A, B, and C and one output such that the output is on only if at least 2 of the 3 inputs are on:
3. [10] Describe the functionality of each Y86-64 processor stage during execution of the ret instruction in terms of the icode, ifun, rA, rB, valA, valB, valC, valP, valE, valM, srcA, srcB, dstE, dstM, cnd signals (you may also use M, R, and PC):
IF: ID: EX: MEM: WB: PC:
4. [15] Consider the following C code:
void g(char *p, int *prod) {
for (int i = 0; i < strlen(p); ++i) {
*prod *= p[i];
}
}
a. (10) Rewrite the above code to eliminate unnecessary procedure calls and memory writes:
b. (5) Consider your code from part a above – which loop operation(s) are sequential dependencies and therefore cannot be pipelined? Why?
5. [15] Consider the following C code:
long absDiff(long x, long y) {
long result;
if (x >= y) {
result = x – y;
} else {
result = y – x;
}
return result;
}
Write Y86-64 code to implement the C code above. Use the appropriate registers for the arguments and return value (as specified by the x86-64/Y86-64 register conventions). Comment your code:
6. (30) Consider a 64B direct-mapped cache with 16B blocks and 4 sets for an 8-bit architecture (i.e., 256 bytes of memory):
a. (5) Write a C function unsigned char getTag(unsigned char address) that returns the cache tag for the specified address using bitwise operators:
b. (5) Write a C function unsigned char getSet(unsigned char address) that returns the cache set for the specified address using bitwise operators:
c. (10) Considering the following sequence of memory addresses, which addresses will result in cache hits and which will result in misses (assuming that the cache is initially empty)? For each address, show the tag, set, offset, and whether it resulted in hit or miss:
0x00
0x46
0x06
0x40
0x12
0x0c
d. (10) Now assume that cache is 2-way set associative with 2 sets rather than direct mapped with 4 sets, but that the parameters are otherwise unchaged. Use the Least Recently Used (LRU) eviction policy if evictions are necessary. Again consider the following sequence of memory addresses; for each address, show the tag, set, offset, and whether it resulted in hit or miss:
0x00
0x46
0x06
0x40
0x12
0x0c