Yes: add
sub
and
or
slt
sw
No: lw
beq j
This design shows the correct logic for synchronizing control signals and instructions, and forwarding logic, but lacks hazard detection.
Unsimplified Datapath with Forwarding Pipeline Stalls 1
CS@VT Computer Organization II ý2005-2015 McQuain
Consider the following sequence of instructions:
lw $t2, 20($t1) # writes a value
and $t4, $t2, $t5 # reads that value
This hazard cannot be resolved by simple forwarding… why not?
and lw
The value lw writes into $t2 is not available until lw completes the MEM stage, but and needs that value when it enters the EX stage, which is when lw enters the MEM stage.
QTP: why can this situation not occur if the writing instruction is R-type?
Load-Use Data Hazard Pipeline Stalls 2
CS@VT Computer Organization II ý2005-2015 McQuain
A load-use hazard requires delaying the execution of the using instruction until the result from the loading instruction can be made available to the using instruction.
lw $t2, 20($t1) # loads $t2 and $t4, $t2, $t5 # uses $t2
and STALL lw If we can stall the execution of the using instruction for one cycle:
– value to be loaded to $t2 will be available in the MEM/WB buffer when the using instruction moves from ID to EX
– that value can be forwarded to the using instruction as the using instruction enters the EX stage
Handling a Load-Use Hazard Pipeline Stalls 3
CS@VT Computer Organization II ý2005-2015 McQuain
When can we detect the existence of a load-use hazard?
When we are decoding the using instruction — if we remember right information about the preceding instruction.
What do we need to remember?
– whether the preceding instruction reads a value from data memory
– whether the preceding instruction writes a value to the register file
– whether that value is written to a register that current instruction reads from
ID/EX.MemRead
ID/EX.RegisterRt
IF/ID.RegisterRs IF/ID.RegisterRt
Why do we not need to consider this question?
Detection Pipeline Stalls 4
CS@VT Computer Organization II ý2005-2015 McQuain
The loading instruction must be just that… so it writes to register rt.
There is a load-use hazard when
ID/EX.MemRead AND
1 iff we’re executing a load instruction
( ( ID/EX.RegisterRt == IF/ID.RegisterRs) OR
( ( ID/EX.RegisterRt == IF/ID.RegisterRt) )
If detected… do what?
ID/EX shows register being written to; IF/ID shows registers being read from
Load-UseHazardDetection PipelineStalls 5
CS@VT Computer Organization II ý2005-2015 McQuain
“If it isn’t written down, it didn’t happen.”
Force all control values in ID/EX register to 0 – whenusingreachesIDstage
– EX, MEM and WB do a nop
Prevent update of PC and IF/ID registers
– usinginstructionisdecodedagain
– instructionaftertheusinginstructionwillbefetchedagain
– 1-cyclestallallowsMEMtoreaddataforlw
– can subsequently forward data to using instruction in EX stage
HowtoStallthePipeline PipelineStalls 6
CS@VT Computer Organization II ý2005-2015 McQuain
lw $2, 20($1) and $4, $2, $5 or $8, $2, $6 add $9, $4, $2
# 1 # 2 # 3 # 4
or and lw
When and reaches the ID stage, the hazard involving $2 is detected.
All the control signals from the ID stage are set to 0 and the PC and IF/ID interstage buffer are prevented from updating.
Trace Pipeline Stalls 7
CS@VT Computer Organization II ý2005-2015 McQuain
Resetting the control signals and locking PC and IF/ID cause:
or and STALL lw
Because IF/ID is not updated, the and instruction is processed through ID again.
Because PC is not updated, the or instruction is fetched again in the IF stage.
And:
– EX operates as usual (with all relevant signals 0)
– EX sends only 0 control signals to MEM for the next cycle
lw reaches the MEM stage and reads the value to be written to $2. That value goes into MEM/WB.
Trace Pipeline Stalls 8
CS@VT Computer Organization II ý2005-2015 McQuain
On the next cycle:
add or and STALL lw
The control signals for and (set in ID in the previous cycle) reach EX. The value for $2 in MEM/WB is forwarded to the ALU in EX.
And:
– MEM operates as usual (with all relevant signals 0)
– MEM sends only 0 control signals to WB for the next cycle
Instructions preceding and proceed normally…
Trace Pipeline Stalls 9
CS@VT Computer Organization II ý2005-2015 McQuain
On the following cycles:
add or and STALL
… and so on…
The execution time has increased by one clock cycle.
add or and
Stall/Bubble in the Pipeline Pipeline Stalls 10
CS@VT Computer Organization II ý2005-2015 McQuain
Simplified Datapath with Hazard Detection Pipeline Stalls 11
CS@VT Computer Organization II ý2005-2015 McQuain
Stall Details
Pipeline Stalls 12 Stall == 1 iff load-use hazard
CS@VT
Computer Organization II
ý2005-2015 McQuain
InhibitWrite prevents updating of storage
AND gates allow ¡°erasing¡± of normal control signals
Unsimplified Datapath with Hazard Detection
Yes: add
sub
and
or
slt
sw
lw
No: beq
j
Pipeline Stalls 13
CS@VT
Computer Organization II
ý2005-2015 McQuain
Consider the following scenario:
lw lw
$t1, ($t3) # rd == t1
$t1, ($t2) # rt == t1 (really the destination reg)
rs rt
The Hazard Detection design sees $t1 as an input register for the second lw… So it would stall… needlessly.
How could we fix this?
A Question to Ponder Pipeline Stalls 14
CS@VT Computer Organization II ý2005-2015 McQuain