Major components:
– memory
– centralprocessingunit – registers
– thefetch/executecycle
(the hardware process)
CPU
Main Memory
0
PC
IR
Ex Unit
Instruction
Instruction
Instruction
Data
Data
Data
System Bus
I/O Module
n-1
buffers
Instr Decoding Registers Arithmetic/Logic
PC IR
= program counter = instruction register
Hardware Level Organization Intro MIPS 1
CS@VT Computer Organization II ý2005-2017 McQuain
Control
– decodes instructions and manages CPU¡¯s internal resources
Registers
– general-purpose registers available to user processes
– special-purpose registers directly managed in fetch/execute cycle
– other registers may be reserved for use of operating system
– very fast and expensive (relative to memory)
– hold all operands and results of arithmetic instructions (on RISC systems)
– save bits in instruction representation
Data path or arithmetic/logic unit (ALU)
– operatesondata
Central Processing Unit Intro MIPS
2
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Instructions are collections of bits
Programs are stored in memory, to be read or written just like data
Main Memory
0
CPU
Instruction
Instruction
Instruction
Data
Data
Data
PC
IR
MAR
MBR
I/O AR
I/O BR
Ex Unit
memory for data, programs, compilers, editors, etc.
Fetch & Execute Cycle
Instructions are fetched and put into a special register Bits in the register “control” the subsequent actions Fetch the ¡°next¡± instruction and continue
n-1
Stored Program Concept Intro MIPS 3
CS@VT Computer Organization II ý2005-2017 McQuain
Of course, on most systems several programs will be stored in memory at any given time.
On most contemporary systems instructions of only one of those will be executed at any given instant.
Main Memory CPU
PowerPoint pgm (machine code)
vim (machine code)
GIS source code (data)
g++ (machine code)
PC
IR
MAR
MBR
I/O AR
I/O BR
Ex Unit
The operating system will rapidly switch among the eligible processes, producing the illusion that several programs are executing at the same time.
Stored Program Concept Intro MIPS 4
CS@VT Computer Organization II ý2005-2017 McQuain
Sometimes called the hardware process… executes continuously.
Fetch Stage Execute Stage
START
Steps:
– fetch an instruction from memory to the instruction register
– incrementtheprogramcounterregister(bytheinstructionlength)
– decode the instruction (in the control unit)
– fetch operands, if any, usually from registers
– perform the operation (in the data path); this may modify the PC register
– store the results, usually to registers
Fetch Next Instruction
Execute Instruction
HALT
Fetch/Execute Cycle Intro MIPS 5
CS@VT Computer Organization II ý2005-2017 McQuain
But, how is all of this driven? Machine language:
– registersstorecollectionsofbits
– all data and instructions must be encoded as collections of bits (binary)
– bitsarerepresentedaselectricalcharges(moreorless)
– control logic and arithmetic operations are implemented as circuits, which are driven by the movement of electrical charges
– so, the instructions directly manipulate the underlying hardware (cool, huh?)
The collection of all valid binary instructions is known as the machine language.
– what¡¯s valid depends on the design of the hardware, especially the control circuitry
– must be formally specified
– machine language is not human-friendly
Machine Language Intro MIPS 6
CS@VT Computer Organization II ý2005-2017 McQuain
More human-friendly syntax:
– expressed in text, not in binary
– instructions are identified by (more-or-less) mnemonic names
– instruction operands may include registers, memory locations, or…
Aspects of assembly language:
– unlike high-level languages, each instruction is extremely simple, so assembly language programs are much longer than corresponding high-level language programs
– assembly language must be translated into machine language in order to be executed
– assembly language is not usually any more portable across different hardware platforms that is machine language
– most assembly languages are quite similar… from a certain point of view
Assembly Language Intro MIPS 7
CS@VT Computer Organization II ý2005-2017 McQuain
We¡¯ll be working with the MIPS instruction set architecture (ISA)
– similar to other architectures developed since the 1980’s
– almost 100 million MIPS processors manufactured in 2002
– used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …
1400 1300 1200 1100 1000
900
800
700
600
500
400
300
200
100
0
Other SPARC Hitachi SH PowerPC Motorola 68K MIPS
IA-32 ARM
1998 1999
2000 2001 2002
MIPS ISA Intro MIPS 8
CS@VT Computer Organization II ý2005-2017 McQuain
Registers
– 32 32-bit general-purpose registers, referred to as $0, $1, …, $31
– 32 32-bit floating-point registers, referred to as $f0, $f1, … $f31
– 16 64-bit floating-point registers, referred to as $f0, $f2, … $f30 – conventionsgoverntheuseofthegeneralregisters
We will, for now, adopt the view that the underlying computer is a ¡°black box¡± that understands MIPS machine language.
MIPS Registers Intro MIPS 9
CS@VT Computer Organization II ý2005-2017 McQuain
Operands to arithmetic and logical instructions must be registers or immediates. Compiler associates variables with registers
What about programs with lots of variables?
Control
Datapath
Processor
Memory
Input
Output
I/O
Registers vs. Memory Intro MIPS 10
CS@VT Computer Organization II ý2005-2017 McQuain
We will study the MIPS assembly language as an exemplar of the concept.
MIPS assembly instructions each consist of a single token specifying the command to be carried out, and zero or more operation parameters:
The tokens are separated by commas. Indentation is insignificant to the
assembler, but is certainly significant to the human reader.
MIPS command tokens are short and mnemonic (in principle). For example:
add lw sw jr
The MIPS reference card bound in the front of P&H includes a listing of many of the MIPS commands you will need to understand and use.
MIPS Assembly Language Intro MIPS 11
CS@VT Computer Organization II ý2005-2017 McQuain
MIPS operands include:
– hardwareregisters
– offsetandbaseregister
– literalconstants(immediateparameters) – labels
Of course, MIPS assembly also allows comments. Simply, all characters from a ¡®#¡¯ character to the end of the line are considered a comment.
There are also some special directives, but those can wait…
MIPS Assembly Language Intro MIPS 12
CS@VT Computer Organization II ý2005-2017 McQuain
Viewed as a large, single-dimension array, with an address.
A memory address is an index into the array
“Byte addressing” means that the index points to a byte of memory.
0 1 2 3 4 5 6 …
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
Memory Organization Intro MIPS 13
CS@VT Computer Organization II ý2005-2017 McQuain
Bytes are nice, but most data items use larger “words” For MIPS, a word is 32 bits or 4 bytes.
32 bits of data
32 bits of data
32 bits of data
32 bits of data
0 4 8
12 …
Registers hold 32 bits of data
232 bytes with byte addresses from 0 to 232 – 1 230 words with byte addresses 0, 4, 8, … 232 – 4
Words are aligned, that is, each has an address that is a multiple of 4.
MIPS can be either big-endian (that is, the address of each word is the address of the ¡°left-most¡± byte of the word) or little-endian. This is important when viewing the contents of memory.
MIPS Memory Organization Intro MIPS 14
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http://jamesgart.com/procsim/
Simple MIPS Overview Intro MIPS 15
CS@VT Computer Organization II ý2005-2017 McQuain