Individual Project I
Signal Integrity (SI) Engineering
PCI Express 5.0 Interconnect Design & Characterization with ANSYS®
Objective:
Design a single trace route consisting of on-chip and off-chip interconnect spanning three FR4 layers and characterize it for a PCI Express 5.0 serial data link.
Problem Outline:
PCI Express 5.0 is an upgrade of PCI Express (PCIe), a high-speed serial data interconnect framework for, e.g. graphics communications. PCIe bus consists of 16 lanes, whereas each lane contains two differential signal pairs (for transmit and receive), thus a total of four signal traces comprise one lane. This project assignment focuses on modeling signal propagation through only one such trace, i.e. on modeling one half of a differential signal pair (or ¼ of one lane or 1/64 of a full PCIe bus). Assume that PCIe 5.0 will use copper as the signal trace material and FR4 for the dielectric material of the board. The operating data transfer speed for PCIe 5.0 is set at approximately 4 GB/sec, which corresponds to a single UI (unit interval) of 250 ps (see more explanation below on p. 4).
• HFSS Model Construction
For this project, you are to assume the role of a junior SI engineer at a company engaged in R&D work on PCIe 5.0 product line. You are assigned the task of routing a test trace carrying PCIe 5.0 signal and analyzing it under realistic conditions from the SIE standpoint. Your investigation will provide a starting point for developing routing guidelines and signal processing specifications.
Toward that goal, you are assigned a three-layer segment of a motherboard (MB) “real estate” to route the trace from a chipset located on one edge of this segment to the other edge of it (the two Ports are to be located opposite each other across the longer edge). It is largely up to you how you will route it; however, you must follow these specifications:
• Your MB segment size is: 4500×450 mil. It shall include: A copper ground plane (2 mil thickness); three layers of FR4 on which traces will be routed (each layer has 20 mil thickness); and all necessary routing components as described below.
• The signal shall be routed out of the chip on top FR4 layer using a combination of on-chip bump, off-chip bump, and off-chip bondpad (BP) with off-chip trace (OCT). The material for both bumps is tin; the material for the traces is copper. The on- and off-chip bumps (used in flip-chip packages) can be drawn using the ‘cone’ template in HFSS; they will look similar to the picture below once assembled:
The top bump is on-chip (and remains unconnected in this design) and the bottom is off-chip, which will rest atop the off-chip BP. Larger diameter of a bump is 20 mil; smaller diameter is 10 mil; height of each cone is 10 mil. Off-chip BP is a 45×45 mil square located at the center of the left side. OCT has width of 15 mil and length of 150 mil; thickness (height) of copper for both BP and OCT is 2 mil. Once you complete this segment it will look somewhat similar to an illustration below (not to scale):
• The rest of the trace should have width of 20 mil and height of 2 mil. The trace will be routed on each of the three FR4 layers. As stated above, the trace will start on top layer and it will also end on top layer; the rest of the routing is up to you, but it must utilize all three layers. Use vias (see Lab Exercise 3) to “jump layers.” A via is a copper cylinder with 15 mil diameter.
• The trace will also incorporate four 900 turns (typically used to route traces around various other objects). It is up to you where to include those turns. The minimal distance between the turns is 100 mil.
• Your Wave Port 1 and Wave Port 2 should be placed at two opposing edges of the MB segment along the 4500 mil direction.
Additional Hints and Reminders:
• All dimensions are in mils – be sure to select ‘mils’ from ‘Units’ at the beginning.
• Before starting to draw your design it may be a good idea to carefully calculate all coordinates and dimensions of all interconnect components.
• Every time you have a metal intersecting a dielectric, make sure to perform Boolean subtraction of metal from each dielectric layer it intersects – and don’t forget to ‘Clone tool parts.’
• Perform validation to find out whether any mistakes in drawing have been made.
• There are only three materials used to build the interconnect: tin, copper and FR4 dielectric.
• When making an Air Box, make sure to subtract from it the uppermost metal parts.
• Remember that the Port Excitation assignment arrow (representing the E-field direction) must be fully contained within a dielectric and NOT intersect any metal!
BE CAREFUL WITH DIMENSIONS, EXCITATIONS & INTERSECTIONS: It is often easier to redraw a complex design from scratch than to try to fix it when problems with drawings occur.
• HFSS Model Simulation
Once the model is drawn – set up the simulation.
Suggested simulation setup: Choose Sweep, then choose Linear Step and specify Start Frequency at 100 MHz, Stop Frequency at 20 GHz and Step Size at 100 MHz. (Depending on your design and corresponding simulation speed, you may need to modify these parameters).
Don’t forget to check ‘Save Fields’ at the bottom of Sweep Setup window and simulate.
Plot and save graphs for S11 (Reflection Loss) and S21 (Insertion Loss) once simulation completes.
Tip: For your first simulation after completing drawing of the model, you may choose to run a quick test to check whether the model is correct – to do this choose Linear Count as your simulation setup and specify a small number of frequency points (10-20) between the Start and Stop Frequencies. This will make the simulation run faster and will give you a general idea of the model’s correctness.
• Circuit Nexxim Simulation
As we have done in Lab Exercise 3, insert Circuit Design into the Project, then export (drag and drop) your HFSS model into the circuit. Use a 50 Ohm load resistor and a 5 Ohm source output resistor. Set up the simulation to run a bit sequence of 512 UI duration (note, again, that UI = PW+TRF). As in Lab Exercise 3, use the random binary source (V_PRBS) and set the amplitude to standard (for PCI Express) 3.3 V and rise/fall edges to 15 ps. Based on these figures and previous Lab exercises, set up your transient analysis. Once the simulation completes, analyze the results by examining the following:
• The overall standard plot of the bit sequence propagation – look at signal distortion, overshoot amplitude, general shape of the output signal compared to the ideal input;
• A close-up showing a few bits of data – examine the distortions again on a more detailed level;
• Eye diagram(s) – see below.
When you plot an eye diagram, you will need to specify: a). Starting point (this is the point in time when the output signal starts); b). UI; c). Length of the signal to include in eye diagram. After you plot the eye diagram you will observe that either of the two possibilities happened: 1). The eye diagram will have an opening (empty space not intersected by any lines); or 2). The eye diagram does not have an opening. Typically, a high-speed receiver will perform bit detection correctly when the eye opening is at least 25% of the max UI in horizontal direction and 25% of the max voltage amplitude in vertical direction. Compare your eye opening to this spec. If the spec isn’t met, reduce the simulation length from 512 bits to a lower number of bits until the spec is met. Note this length for the report.
Individual Report:
The report should contain the following sections:
• Abstract: A brief summary of what the Project is about, what was done and what the results are.
• Group Work Acknowledgment (if applicable; see Group Work Rules below).
• PCIe 5.0 Overview: A paragraph of brief description, including references to any online sources you used to read about this technology.
• Problem Overview: Your assessment of the problem and brief discussion of the solution to follow.
• Solution Outline: Briefly describe the following –
• HFSS model creation (to include discussion of any challenges encountered);
• HFSS results (to include evidence of the successful completion of simulation, i.e. S11/S21 plots with discussion and your interpretation of the results);
• Circuit setup and simulation results (to include schematics, graphs and discussion);
• Eye diagram implementation and analysis (to include your solution approach and the results of eye opening analysis).
• Summary: A concise description of what was achieved and your interpretation of the results. Include possible solutions for improving the performance of the architecture. Also, include the description of any challenges that you encountered during the project and how you could’ve done better.
• Conclusions: A brief statement on what you achieved, what you learned, what value the Project added to your education and what recommendations to fellow students and/or the instructor you would make.
Project Report Due Date & Format: October 10 (Thursday) by 5:00PM – by email. No printed copy is required. Penalty for late submissions will be calculated based on time delay.
Group Work Rules:
You may (but don’t have to) work in groups of 2-3 during our regular lab hours when I will be present to answer your questions and provide help, or outside the lab hours; however, the following rules will apply:
• Only the HFSS portion of the Project can be worked on in groups – the circuit simulation portion should be a 100% individual endeavor;
• If you manage to finish the HFSS part of the Project as a group, it is allowed then to copy the resultant file for use by each group member;
• You may discuss the circuit portion of the Project with other students, but NOT share the files or data;
• Each HFSS group member will have to write and turn in their individual report – no copying of text or graphs from one report to another is allowed (Exception: only HFSS graphs can be pasted into the reports if all group members were present when the graphs were generated);
• Each report should contain acknowledgment of group work and estimates of each group member’s contribution expressed in percentage points and “signed” (type in the name) by each group member.