MIPS32TM Architecture For Programmers Volume II: The MIPS32TM Instruction Set
Document Number: MD00086 Revision 0.95
March 12, 2001
MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043-1353
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Chapter 1.1
1.2
1.3 1.4
Chapter 2.1
2.2
2.3 2.4
Chapter 3.1 3.2
1 About This Book …………………………………………………………………………………………………………………………………….. 1 Typographical Conventions …………………………………………………………………………………………………………………………. 1 1.1.1 Italic Text…………………………………………………………………………………………………………………………………………. 1 1.1.2 Bold Text …………………………………………………………………………………………………………………………………………. 1 1.1.3 Courier Text……………………………………………………………………………………………………………………………………… 1 UNPREDICTABLE and UNDEFINED ………………………………………………………………………………………………………… 2 1.2.1 UNPREDICTABLE…………………………………………………………………………………………………………………………… 2 1.2.2 UNDEFINED……………………………………………………………………………………………………………………………………. 2 Special Symbols in Pseudocode Notation………………………………………………………………………………………………………. 2 For More Information …………………………………………………………………………………………………………………………………. 5
2 Guide to the Instruction Set ………………………………………………………………………………………………………………………. 7 Understanding the Instruction Fields …………………………………………………………………………………………………………….. 7 2.1.1 Instruction Fields ………………………………………………………………………………………………………………………………. 8 2.1.2 Instruction Descriptive Name and Mnemonic ……………………………………………………………………………………….. 9 2.1.3 Format Field……………………………………………………………………………………………………………………………………… 9 2.1.4 Purpose Field ………………………………………………………………………………………………………………………………….. 10 2.1.5 Description Field……………………………………………………………………………………………………………………………… 10 2.1.6 Restrictions Field …………………………………………………………………………………………………………………………….. 10 2.1.7 Operation Field ……………………………………………………………………………………………………………………………….. 11 2.1.8 Exceptions Field………………………………………………………………………………………………………………………………. 11 2.1.9 Programming Notes and Implementation Notes Fields…………………………………………………………………………. 11 Operation Section Notation and Functions …………………………………………………………………………………………………… 12 2.2.1 Instruction Execution Ordering………………………………………………………………………………………………………….. 12 2.2.2 Pseudocode Functions………………………………………………………………………………………………………………………. 12 Op and Function Subfield Notation …………………………………………………………………………………………………………….. 20 FPU Instructions ………………………………………………………………………………………………………………………………………. 20
3 The MIPS32TM Instruction Set ………………………………………………………………………………………………………………… 21 Compliance and Subsetting………………………………………………………………………………………………………………………… 21 Alphabetical List of Instructions…………………………………………………………………………………………………………………. 21
Table of Contents
ABS.fmt ……………………………………………………………………………………………………………………………………………………………………………………………………. 30 ADD…………………………………………………………………………………………………………………………………………………………………………………………………………. 31 ADD.fmt …………………………………………………………………………………………………………………………………………………………………………………………………… 33 ADDI………………………………………………………………………………………………………………………………………………………………………………………………………… 34 ADDIU……………………………………………………………………………………………………………………………………………………………………………………………………… 35 ADDU………………………………………………………………………………………………………………………………………………………………………………………………………. 36 AND…………………………………………………………………………………………………………………………………………………………………………………………………………. 37 ANDI………………………………………………………………………………………………………………………………………………………………………………………………………… 38 B………………………………………………………………………………………………………………………………………………………………………………………………………………. 39 BAL………………………………………………………………………………………………………………………………………………………………………………………………………….. 40 BC1F ………………………………………………………………………………………………………………………………………………………………………………………………………… 41 BC1FL ……………………………………………………………………………………………………………………………………………………………………………………………………… 43 BC1T………………………………………………………………………………………………………………………………………………………………………………………………………… 45 BC1TL ……………………………………………………………………………………………………………………………………………………………………………………………………… 47 BC2F ………………………………………………………………………………………………………………………………………………………………………………………………………… 49 BC2FL ……………………………………………………………………………………………………………………………………………………………………………………………………… 50 BC2T………………………………………………………………………………………………………………………………………………………………………………………………………… 52 BC2TL ……………………………………………………………………………………………………………………………………………………………………………………………………… 53 BEQ………………………………………………………………………………………………………………………………………………………………………………………………………….. 55 BEQL ……………………………………………………………………………………………………………………………………………………………………………………………………….. 56 BGEZ ……………………………………………………………………………………………………………………………………………………………………………………………………….. 58 BGEZAL…………………………………………………………………………………………………………………………………………………………………………………………………… 59 BGEZALL ………………………………………………………………………………………………………………………………………………………………………………………………… 60 BGEZL……………………………………………………………………………………………………………………………………………………………………………………………………… 62
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 i
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
BGTZ ……………………………………………………………………………………………………………………………………………………………………………………………………….. 64 BGTZL……………………………………………………………………………………………………………………………………………………………………………………………………… 65 BLEZ………………………………………………………………………………………………………………………………………………………………………………………………………… 67 BLEZL ……………………………………………………………………………………………………………………………………………………………………………………………………… 68 BLTZ………………………………………………………………………………………………………………………………………………………………………………………………………… 70 BLTZAL …………………………………………………………………………………………………………………………………………………………………………………………………… 71 BLTZALL…………………………………………………………………………………………………………………………………………………………………………………………………. 72 BLTZL………………………………………………………………………………………………………………………………………………………………………………………………………74 BNE………………………………………………………………………………………………………………………………………………………………………………………………………….. 76 BNEL ……………………………………………………………………………………………………………………………………………………………………………………………………….. 77 BREAK…………………………………………………………………………………………………………………………………………………………………………………………………….. 79 C.cond.fmt…………………………………………………………………………………………………………………………………………………………………………………………………. 80 CACHE…………………………………………………………………………………………………………………………………………………………………………………………………….. 85 CEIL.W.fmt ………………………………………………………………………………………………………………………………………………………………………………………………. 91 CFC1………………………………………………………………………………………………………………………………………………………………………………………………………… 92 CFC2………………………………………………………………………………………………………………………………………………………………………………………………………… 95 CLO………………………………………………………………………………………………………………………………………………………………………………………………………….. 96 CLZ………………………………………………………………………………………………………………………………………………………………………………………………………….. 97 COP2………………………………………………………………………………………………………………………………………………………………………………………………………… 99 CTC1………………………………………………………………………………………………………………………………………………………………………………………………………. 100 CTC2………………………………………………………………………………………………………………………………………………………………………………………………………. 103 CVT.D.fmt ………………………………………………………………………………………………………………………………………………………………………………………………. 104 CVT.S.fmt……………………………………………………………………………………………………………………………………………………………………………………………….. 105 CVT.W.fmt ……………………………………………………………………………………………………………………………………………………………………………………………… 106 DERET……………………………………………………………………………………………………………………………………………………………………………………………………. 107 DIV ………………………………………………………………………………………………………………………………………………………………………………………………………… 109 DIV.fmt…………………………………………………………………………………………………………………………………………………………………………………………………… 111 DIVU………………………………………………………………………………………………………………………………………………………………………………………………………. 112 ERET………………………………………………………………………………………………………………………………………………………………………………………………………. 113 FLOOR.W.fmt …………………………………………………………………………………………………………………………………………………………………………………………. 114 J……………………………………………………………………………………………………………………………………………………………………………………………………………… 115 JAL…………………………………………………………………………………………………………………………………………………………………………………………………………. 116 JALR………………………………………………………………………………………………………………………………………………………………………………………………………. 117 JR …………………………………………………………………………………………………………………………………………………………………………………………………………… 119 LB ………………………………………………………………………………………………………………………………………………………………………………………………………….. 121 LBU………………………………………………………………………………………………………………………………………………………………………………………………………… 122 LDC1………………………………………………………………………………………………………………………………………………………………………………………………………. 123 LDC2………………………………………………………………………………………………………………………………………………………………………………………………………. 124 LH ………………………………………………………………………………………………………………………………………………………………………………………………………….. 125 LHU ……………………………………………………………………………………………………………………………………………………………………………………………………….. 126 LL…………………………………………………………………………………………………………………………………………………………………………………………………………… 127 LUI…………………………………………………………………………………………………………………………………………………………………………………………………………. 129 LW …………………………………………………………………………………………………………………………………………………………………………………………………………. 130 LWC1……………………………………………………………………………………………………………………………………………………………………………………………………… 131 LWC2……………………………………………………………………………………………………………………………………………………………………………………………………… 132 LWL……………………………………………………………………………………………………………………………………………………………………………………………………….. 133 LWR……………………………………………………………………………………………………………………………………………………………………………………………………….. 137 MADD ……………………………………………………………………………………………………………………………………………………………………………………………………. 141 MADDU …………………………………………………………………………………………………………………………………………………………………………………………………. 142 MFC0 ……………………………………………………………………………………………………………………………………………………………………………………………………… 143 MFC1 ……………………………………………………………………………………………………………………………………………………………………………………………………… 144 MFC2 ……………………………………………………………………………………………………………………………………………………………………………………………………… 145 MFHI………………………………………………………………………………………………………………………………………………………………………………………………………. 146 MFLO …………………………………………………………………………………………………………………………………………………………………………………………………….. 147 MOV.fmt…………………………………………………………………………………………………………………………………………………………………………………………………. 148 MOVF …………………………………………………………………………………………………………………………………………………………………………………………………….. 149 MOVF.fmt ………………………………………………………………………………………………………………………………………………………………………………………………. 150 MOVN ……………………………………………………………………………………………………………………………………………………………………………………………………. 152 MOVN.fmt………………………………………………………………………………………………………………………………………………………………………………………………. 153 MOVT…………………………………………………………………………………………………………………………………………………………………………………………………….. 155 MOVT.fmt ………………………………………………………………………………………………………………………………………………………………………………………………. 156 MOVZ…………………………………………………………………………………………………………………………………………………………………………………………………….. 158 MOVZ.fmt ………………………………………………………………………………………………………………………………………………………………………………………………. 159 MSUB …………………………………………………………………………………………………………………………………………………………………………………………………….. 161 MSUBU ………………………………………………………………………………………………………………………………………………………………………………………………….. 162 MTC0……………………………………………………………………………………………………………………………………………………………………………………………………… 163
MTC1……………………………………………………………………………………………………………………………………………………………………………………………………… 164 MTC2……………………………………………………………………………………………………………………………………………………………………………………………………… 165 MTHI ……………………………………………………………………………………………………………………………………………………………………………………………………… 166 MTLO …………………………………………………………………………………………………………………………………………………………………………………………………….. 167 MUL……………………………………………………………………………………………………………………………………………………………………………………………………….. 169 MUL.fmt …………………………………………………………………………………………………………………………………………………………………………………………………. 170 MULT …………………………………………………………………………………………………………………………………………………………………………………………………….. 171 MULTU ………………………………………………………………………………………………………………………………………………………………………………………………….. 172 NEG.fmt………………………………………………………………………………………………………………………………………………………………………………………………….. 173 NOP………………………………………………………………………………………………………………………………………………………………………………………………………… 174 NOR ……………………………………………………………………………………………………………………………………………………………………………………………………….. 175 OR………………………………………………………………………………………………………………………………………………………………………………………………………….. 176 ORI…………………………………………………………………………………………………………………………………………………………………………………………………………. 177 PREF ………………………………………………………………………………………………………………………………………………………………………………………………………. 178 ROUND.W.fmt………………………………………………………………………………………………………………………………………………………………………………………… 183 SB…………………………………………………………………………………………………………………………………………………………………………………………………………… 185 SC…………………………………………………………………………………………………………………………………………………………………………………………………………… 186 SDBBP ……………………………………………………………………………………………………………………………………………………………………………………………………. 189 SDC1………………………………………………………………………………………………………………………………………………………………………………………………………. 190 SDC2………………………………………………………………………………………………………………………………………………………………………………………………………. 191 SH ………………………………………………………………………………………………………………………………………………………………………………………………………….. 192 SLL ………………………………………………………………………………………………………………………………………………………………………………………………………… 193 SLLV………………………………………………………………………………………………………………………………………………………………………………………………………. 194 SLT ………………………………………………………………………………………………………………………………………………………………………………………………………… 195 SLTI……………………………………………………………………………………………………………………………………………………………………………………………………….. 196 SLTIU …………………………………………………………………………………………………………………………………………………………………………………………………….. 197 SLTU………………………………………………………………………………………………………………………………………………………………………………………………………. 198 SQRT.fmt………………………………………………………………………………………………………………………………………………………………………………………………… 199 SRA………………………………………………………………………………………………………………………………………………………………………………………………………… 200 SRAV………………………………………………………………………………………………………………………………………………………………………………………………………201 SRL ………………………………………………………………………………………………………………………………………………………………………………………………………… 202 SRLV ……………………………………………………………………………………………………………………………………………………………………………………………………… 203 SSNOP ……………………………………………………………………………………………………………………………………………………………………………………………………. 204 SUB………………………………………………………………………………………………………………………………………………………………………………………………………… 205 SUB.fmt ………………………………………………………………………………………………………………………………………………………………………………………………….. 206 SUBU……………………………………………………………………………………………………………………………………………………………………………………………………… 207 SW………………………………………………………………………………………………………………………………………………………………………………………………………….. 208 SWC1……………………………………………………………………………………………………………………………………………………………………………………………………… 209 SWC2……………………………………………………………………………………………………………………………………………………………………………………………………… 210 SWL ……………………………………………………………………………………………………………………………………………………………………………………………………….. 211 SWR……………………………………………………………………………………………………………………………………………………………………………………………………….. 213 SYNC……………………………………………………………………………………………………………………………………………………………………………………………………… 215 SYSCALL……………………………………………………………………………………………………………………………………………………………………………………………….. 219 TEQ………………………………………………………………………………………………………………………………………………………………………………………………………… 220 TEQI ………………………………………………………………………………………………………………………………………………………………………………………………………. 221 TGE………………………………………………………………………………………………………………………………………………………………………………………………………… 222 TGEI ………………………………………………………………………………………………………………………………………………………………………………………………………. 223 TGEIU…………………………………………………………………………………………………………………………………………………………………………………………………….. 224 TGEU……………………………………………………………………………………………………………………………………………………………………………………………………… 225 TLBP ………………………………………………………………………………………………………………………………………………………………………………………………………. 226 TLBR ……………………………………………………………………………………………………………………………………………………………………………………………………… 227 TLBWI……………………………………………………………………………………………………………………………………………………………………………………………………. 229 TLBWR…………………………………………………………………………………………………………………………………………………………………………………………………… 231 TLT ………………………………………………………………………………………………………………………………………………………………………………………………………… 233 TLTI……………………………………………………………………………………………………………………………………………………………………………………………………….. 234 TLTIU…………………………………………………………………………………………………………………………………………………………………………………………………….. 235 TLTU ……………………………………………………………………………………………………………………………………………………………………………………………………… 236 TNE………………………………………………………………………………………………………………………………………………………………………………………………………… 237 TNEI ………………………………………………………………………………………………………………………………………………………………………………………………………. 238 TRUNC.W.fmt…………………………………………………………………………………………………………………………………………………………………………………………. 239 WAIT………………………………………………………………………………………………………………………………………………………………………………………………………241 XOR ……………………………………………………………………………………………………………………………………………………………………………………………………….. 243 XORI………………………………………………………………………………………………………………………………………………………………………………………………………. 244
Appendix A Revision History ………………………………………………………………………………………………………………………………. 245
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 iii
List of Figures
Figure 2-1: Example of Instruction Description ………………………………………………………………………………………………………….. 8 Figure 2-2: Example of Instruction Fields ………………………………………………………………………………………………………………….. 9 Figure 2-3: Example of Instruction Descriptive Name and Mnemonic …………………………………………………………………………… 9 Figure 2-4: Example of Instruction Format…………………………………………………………………………………………………………………. 9 Figure 2-5: Example of Instruction Purpose ……………………………………………………………………………………………………………… 10 Figure 2-6: Example of Instruction Description ………………………………………………………………………………………………………… 10 Figure 2-7: Example of Instruction Restrictions ………………………………………………………………………………………………………… 11 Figure 2-8: Example of Instruction Operation …………………………………………………………………………………………………………… 11 Figure 2-9: Example of Instruction Exception…………………………………………………………………………………………………………… 11 Figure 2-10: Example of Instruction Programming Notes…………………………………………………………………………………………… 12 Figure 2-11: COP_LW Pseudocode Function……………………………………………………………………………………………………………. 13 Figure 2-12: COP_LD Pseudocode Function…………………………………………………………………………………………………………….. 13 Figure 2-13: COP_SW Pseudocode Function……………………………………………………………………………………………………………. 13 Figure 2-14: COP_SD Pseudocode Function…………………………………………………………………………………………………………….. 14 Figure 2-15: AddressTranslation Pseudocode Function ……………………………………………………………………………………………… 14 Figure 2-16: LoadMemory Pseudocode Function………………………………………………………………………………………………………. 15 Figure 2-17: StoreMemory Pseudocode Function ……………………………………………………………………………………………………… 15 Figure 2-18: Prefetch Pseudocode Function ……………………………………………………………………………………………………………… 16 Figure 2-19: ValueFPR Pseudocode Function …………………………………………………………………………………………………………… 17 Figure 2-20: StoreFPR Pseudocode Function ……………………………………………………………………………………………………………. 18 Figure 2-21: SyncOperation Pseudocode Function…………………………………………………………………………………………………….. 18 Figure 2-22: SignalException Pseudocode Function ………………………………………………………………………………………………….. 19 Figure 2-23: NullifyCurrentInstruction PseudoCode Function…………………………………………………………………………………….. 19 Figure 2-24: CoprocessorOperation Pseudocode Function………………………………………………………………………………………….. 19 Figure 2-25: JumpDelaySlot Pseudocode Function ……………………………………………………………………………………………………. 19 Figure 2-26: FPConditionCode Pseudocode Function………………………………………………………………………………………………… 20 Figure 2-27: SetFPConditionCode Pseudocode Function……………………………………………………………………………………………. 20 Figure 3-1: Usage of Address Fields to Select Index and Way ……………………………………………………………………………………. 86 Figure 3-2: Unaligned Word Load Using LWL and LWR ………………………………………………………………………………………… 133 Figure 3-3: Bytes Loaded by LWL Instruction………………………………………………………………………………………………………… 134 Figure 3-4: Unaligned Word Load Using LWL and LWR ………………………………………………………………………………………… 138 Figure 3-5: Bytes Loaded by LWL Instruction………………………………………………………………………………………………………… 139 Figure 3-6: Unaligned Word Store Using SWL and SWR ………………………………………………………………………………………… 211 Figure 3-7: Bytes Stored by an SWL Instruction……………………………………………………………………………………………………… 212 Figure 3-8: Unaligned Word Store Using SWR and SWL ………………………………………………………………………………………… 213 Figure 3-9: Bytes Stored by SWR Instruction …………………………………………………………………………………………………………. 214
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List of Tables
Table 1-1: Symbols Used in Instruction Operation Statements …………………………………………………………………………………….. 3 Table 2-1: AccessLength Specifications for Loads/Stores …………………………………………………………………………………………. 16 Table 3-1: CPU Arithmetic Instructions ………………………………………………………………………………………………………………….. 22 Table 3-2: CPU Branch and Jump Instructions…………………………………………………………………………………………………………. 22 Table 3-3: CPU Instruction Control Instructions ………………………………………………………………………………………………………. 23 Table 3-4: CPU Load, Store, and Memory Control Instructions …………………………………………………………………………………. 23 Table 3-5: CPU Logical Instructions ………………………………………………………………………………………………………………………. 24 Table 3-6: CPU Move Instructions …………………………………………………………………………………………………………………………. 24 Table 3-7: CPU Shift Instructions…………………………………………………………………………………………………………………………… 24 Table 3-8: CPU Trap Instructions …………………………………………………………………………………………………………………………… 25 Table 3-9: Obsolete CPU Branch Instructions………………………………………………………………………………………………………….. 25 Table 3-10: FPU Arithmetic Instructions…………………………………………………………………………………………………………………. 26 Table 3-11: FPU Branch Instructions………………………………………………………………………………………………………………………. 26 Table 3-12: FPU Compare Instructions …………………………………………………………………………………………………………………… 26 Table 3-13: FPU Convert Instructions …………………………………………………………………………………………………………………….. 26 Table 3-14: FPU Load, Store, and Memory Control Instructions………………………………………………………………………………… 27 Table 3-15: FPU Move Instructions………………………………………………………………………………………………………………………… 27 Table 3-16: Obsolete FPU Branch Instructions ………………………………………………………………………………………………………… 27 Table 3-17: Coprocessor Branch Instructions…………………………………………………………………………………………………………… 27 Table 3-18: Coprocessor Execute Instructions………………………………………………………………………………………………………….. 27 Table 3-19: Coprocessor Load and Store Instructions ……………………………………………………………………………………………….. 28 Table 3-20: Coprocessor Move Instructions …………………………………………………………………………………………………………….. 28 Table 3-21: Obsolete Coprocessor Branch Instructions……………………………………………………………………………………………… 28 Table 3-22: Privileged Instructions …………………………………………………………………………………………………………………………. 28 Table 3-23: EJTAG Instructions …………………………………………………………………………………………………………………………….. 29 Table 3-24: FPU Comparisons Without Special Operand Exceptions …………………………………………………………………………. 81 Table 3-25: FPU Comparisons With Special Operand Exceptions for QNaNs……………………………………………………………… 82 Table 3-26: Usage of Effective Address ………………………………………………………………………………………………………………….. 85 Table 3-27: Encoding of Bits[17:16] of CACHE Instruction ……………………………………………………………………………………… 86 Table 3-28: Encoding of Bits [20:18] of the CACHE Instruction ……………………………………………………………………………….. 87 Table 3-29: Values of the hint Field for the PREF Instruction ………………………………………………………………………………….. 179
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 v
vi MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Chapter 1
About This Book
The MIPS32TM Architecture For Programmers Volume II comes as a multi-volume set.
• Volume I describes conventions used throughout the document set, and provides an introduction to the MIPS32TM Architecture
• Volume II provides detailed descriptions of each instruction in the MIPS32TM instruction set
• VolumeIIIdescribestheMIPS32TMPrivilegedResourceArchitecturewhichdefinesandgovernsthebehaviorofthe privileged resources included in a MIPS32TM processor implementation
• Volume IV-a describes the MIPS16TM Application-Specific Extension to the MIPS32TM Architecture
• Volume IV-b describes the MDMXTM Application-Specific Extension to the MIPS32TM Architecture and is not applicable to the MIPS32TM document set
• Volume IV-c describes the MIPS-3DTM Application-Specific Extension to the MIPS64TM Architecture and is not applicable to the MIPS32TM document set
• Volume IV-d describes the SmartMIPSTMApplication-Specific Extension to the MIPS32TM Architecture
1.1 Typographical Conventions
This section describes the use of italic, bold and courier fonts in this book.
1.1.1 Italic Text
• is used for emphasis
• is used for bits, fields, registers, that are important from a software perspective (for instance, address bits used by
software, and programmable fields and registers), and various floating point instruction formats, such as S, D, and PS
• is used for the memory access types, such as cached and uncached
1.1.2 Bold Text
• represents a term that is being defined
• is used for bits and fields that are important from a hardware perspective (for instance, register bits, which are not programmable but accessible only to hardware)
• is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through 1
• is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below.
1.1.3 Courier Text
Courier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.
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Chapter 1 About This Book
1.2 UNPREDICTABLE and UNDEFINED
The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations.
1.2.1 UNPREDICTABLE
UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is generated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.
UNPREDICTABLE results or operations have several implementation restrictions:
• ImplementationsofoperationsgeneratingUNPREDICTABLEresultsmustnotdependonanydatasource(memory
or internal state) which is inaccessible in the current processor mode
• UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process
• UNPREDICTABLE operations must not halt or hang the processor
1.2.2 UNDEFINED
UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED operations or behavior may cause data loss.
UNDEFINED operations or behavior has one implementation restriction:
• UNDEFINEDoperationsorbehaviormustnotcausetheprocessortohang(thatis,enterastatefromwhichthereis no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state
1.3 Special Symbols in Pseudocode Notation
In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1.
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1.3 Special Symbols in Pseudocode Notation
Table 1-1 Symbols Used in Instruction Operation Statements
Symbol
Meaning
←
Assignment
=, ≠
Tests for equality and inequality
||
Bit string concatenation
xy
A y-bit string formed by y copies of the single-bit value x
b#n
A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the “b#” prefix is omitted, the default base is 10.
xy..z
Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is less than z, this expression is an empty (zero length) bit string.
+, −
2’s complement or floating point arithmetic: addition, subtraction
∗, ×
2’s complement or floating point multiplication (both used for either)
div
2’s complement integer division
mod
2’s complement modulo
/
Floating point division
<
2’s complement less-than comparison
>
2’s complement greater-than comparison
≤
2’s complement less-than or equal comparison
≥
2’s complement greater-than or equal comparison
nor
Bitwise logical NOR
xor
Bitwise logical XOR
and
Bitwise logical AND
or
Bitwise logical OR
GPRLEN
The length in bits (32 or 64) of the CPU general-purpose registers
GPR[x]
CPU general-purpose register x. The content of GPR[0] is always zero.
FPR[x]
Floating Point operand register x
FCC[CC]
Floating Point condition code CC. FCC[0] has the same value as COC[1].
FPR[x]
Floating Point (Coprocessor unit 1), general register x
CPR[z,x,s]
Coprocessor unit z, general register x, select s
CCR[z,x]
Coprocessor unit z, control register x
COC[z]
Coprocessor unit z condition signal
Xlat[x]
Translation of the MIPS16 GPR number x into the corresponding 32-bit GPR number
BigEndianMem
Endian mode as configured at chip reset (0 →Little-Endian, 1 → Big-Endian). Specifies the endianness of the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endianness of Kernel and Supervisor mode execution.
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Chapter 1 About This Book
Table 1-1 Symbols Used in Instruction Operation Statements
Symbol
Meaning
BigEndianCPU
The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).
ReverseEndian
Signal to reverse the endianness of load and store instructions. This feature is available in User mode only, and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as (SRRE and User mode).
LLbit
Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is set when a linked load occurs; it is tested and cleared by the conditional store. It is cleared, during other CPU operation, when a store to the location would no longer be atomic. In particular, it is cleared by exception return instructions.
I:, I+n:, I-n:
This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the instruction time of another instruction. When this happens, the instruction operation is written in sections labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode appears to occur. For example, an instruction may have a result that is not available until after the next instruction. Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I+1.
The effect of pseudocode statements for the current instruction labelled I+1 appears to occur “at the same time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode sequence, the effects of the statements take place in order. However, between sequences of statements for different instructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.
PC
The Program Counter value. During the instruction time of an instruction, this is the address of the instruction word. The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16 instruction) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.
PABITS
The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.
FP32RegistersMode
Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). In MIPS32, the FPU has 32 32-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, the FPU has 32 64-bit FPRs in which 64-bit data types are stored in any FPR.
In MIPS32 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the processor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.
The value of FP32RegistersMode is computed from the FR bit in the Status register.
InstructionInBranchD elaySlot
Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.
SignalException(exce ption, argument)
Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function – the exception is signaled at the point of the call.
4 MIPS32TM Architecture For Programmers Volume II, Revision 0.95
1.4 For More Information
Various MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS URL: http://www.mips.com
Comments or questions on the MIPS32TM Architecture or this document should be directed to
Director of MIPS Architecture MIPS Technologies, Inc.
1225 Charleston Road Mountain View, CA 94043
or via E-mail to architecture@mips.com.
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Chapter 1 About This Book
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Chapter 2
Guide to the Instruction Set
This chapter provides a detailed guide to understanding the instruction descriptions, which are listed in alphabetical order in the tables at the beginning of the next chapter.
2.1 Understanding the Instruction Fields
Figure 2-1 shows an example instruction. Following the figure are descriptions of the fields listed below:
• “Instruction Fields” on page 8
• “Instruction Descriptive Name and Mnemonic” on page 9
• “Format Field” on page 9
• “Purpose Field” on page 10
• “Description Field” on page 10
• “Restrictions Field” on page 10
• “Operation Field” on page 11
• “Exceptions Field” on page 11
• “Programming Notes and Implementation Notes Fields” on page 11
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0
Instruction Mnemonic and Descriptive Name
Instruction encoding constant and variable field names and values
Architecture level at which instruction was defined/redefined and assembler format(s) for each definition
Short description Symbolic description
Full description of instruction operation
Restrictions on instruction and operands
High-level language description of instruction operation
Exceptions that instruction can cause
Notes for programmers
Notes for implementors
2.1.1 Instruction Fields
Example Instruction Name
EXAMPLE
6
31
26 25
21 20
16 15
5 5
11 10
6 5
0
SPECIAL 00000 0
rs
rt
rd
0 0000 0
EXAMPLE 0000 0 0
6
5
5
Format: EXAMPLE rd, rs,rt Purpose: to execute an EXAMPLE op
MIPS32
Description: rd ← rs exampleop rt
This section describes the operation of the instruction in text, tables, and illustrations. It includes information that would be difficult to encode in the Operation section.
Restrictions:
This section lists any restrictions for the instruction. This can include values of the instruction encoding fields such as register specifiers, operand values, operand formats, address alignment, instruction scheduling hazards, and type of memory access for addressed locations.
Operation:
/* This section describes the operation of an instruction in a */ /* high-level pseudo-language. It is precise in ways that the */ /* Description section is not, but is also missing information */ /* that is hard to express in pseudocode.*/
temp ← GPR[rs] exampleop GPR[rt] GPR[rd]← temp
Exceptions:
A list of exceptions taken by the instruction
Programming Notes:
Information useful to programmers, but not necessary to describe the operation of the instruction
Implementation Notes:
Like Programming Notes, except for processor implementors
Figure 2-1 Example of Instruction Description
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Fields encoding the instruction word are shown in register form at the top of the instruction description. The following rules are followed:
2.1 Understanding the Instruction Fields
• The values of constant fields and the opcode names are listed in uppercase (SPECIAL and ADD in Figure 2-2). Constant values in a field are shown in binary below the symbolic or hexadecimal value.
• Allvariablefieldsarelistedwiththelowercasenamesusedintheinstructiondescription(rs,rtandrdinFigure2-2).
• Fields that contain zeros but are not named are unused fields that are required to be zero (bits 10:6 in Figure 2-2). If
such fields are set to non-zero values, the operation of the processor is UNPREDICTABLE.
31 26 25 21 20 16 15 11 10 6 5 0
655556
Figure 2-2 Example of Instruction Fields
2.1.2 Instruction Descriptive Name and Mnemonic
The instruction descriptive name and mnemonic are printed as page headings for each instruction, as shown in Figure 2-3.
Figure 2-3 Example of Instruction Descriptive Name and Mnemonic
2.1.3 Format Field
The assembler formats for the instruction and the architecture level at which the instruction was originally defined are given in the Format field. If the instruction definition was later extended, the architecture levels at which it was extended and the assembler formats for the extended definition are shown in their order of extension (for an example, see C.cond.fmt). The MIPS architecture levels are inclusive; higher architecture levels include all instructions in previous levels. Extensions to instructions are backwards compatible. The original assembler formats are valid for the extended architecture.
SPECIAL 000000
rs
rt
rd
0 00000
ADD 100000
Add Word
ADD
Format: ADD rd, rs, rt
MIPS32 (MIPS I)
Figure 2-4 Example of Instruction Format
The assembler format is shown with literal parts of the assembler instruction printed in uppercase characters. The variable parts, the operands, are shown as the lowercase names of the appropriate fields. The architectural level at which the instruction was first defined, for example “MIPS32” is shown at the right side of the page. If the instruction was originally defined in the MIPS I through MIPS V levels of the architecture, that information is enclosed in parentheses.
There can be more than one assembler format for each architecture level. Floating point operations on formatted data show an assembly format with the actual assembler mnemonic for each valid value of the fmt field. For example, the ADD.fmt instruction lists both ADD.S and ADD.D.
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The assembler format lines sometimes include parenthetical comments to help explain variations in the formats (once again, see C.cond.fmt). These comments are not a part of the assembler format.
2.1.4 Purpose Field
The Purpose field gives a short description of the use of the instruction.
Purpose:
To add 32-bit integers. If an overflow occurs, then trap.
Figure 2-5 Example of Instruction Purpose
2.1.5 Description Field
If a one-line symbolic description of the instruction is feasible, it appears immediately to the right of the Description heading. The main purpose is to show how fields in the instruction are used in the arithmetic or logical operation.
Description: rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs
• If the addition does not overflow, the 32-bit result is placed into GPR rd Figure 2-6 Example of Instruction Description
The body of the section is a description of the operation of the instruction in text, tables, and figures. This description complements the high-level language description in the Operation section.
This section uses acronyms for register descriptions. “GPR rt” is CPU general-purpose register specified by the instruction field rt. “FPR fs” is the floating point operand register specified by the instruction field fs. “CP1 register fd” is the coprocessor 1 general register specified by the instruction field fd. “FCSR” is the floating point Control /Status register.
2.1.6 Restrictions Field
The Restrictions field documents any possible restrictions that may affect the instruction. Most restrictions fall into one of the following six categories:
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• • • • •
•
Valid values for instruction fields (for example, see floating point ADD.fmt)
ALIGNMENT requirements for memory addresses (for example, see LW)
Valid values of operands (for example, see DADD)
Valid operand formats (for example, see floating point ADD.fmt)
Orderofinstructionsnecessarytoguaranteecorrectexecution.Theseorderingconstraintsavoidpipelinehazardsfor which some processors do not have hardware interlocks (for example, see MUL).
Valid memory access types (for example, see LL/SC)
Restrictions:
None
2.1.7 Operation Field
Figure 2-7 Example of Instruction Restrictions
2.1 Understanding the Instruction Fields
The Operation field describes the operation of the instruction as pseudocode in a high-level language notation resembling Pascal. This formal description complements the Description section; it is not complete in itself because many of the restrictions are either difficult to include in the pseudocode or are omitted for legibility.
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] ← temp endif
Figure 2-8 Example of Instruction Operation
See Section 2.2 , “Operation Section Notation and Functions” on page 12 for more information on the formal notation used here.
2.1.8 Exceptions Field
The Exceptions field lists the exceptions that can be caused by Operation of the instruction. It omits exceptions that can be caused by the instruction fetch, for instance, TLB Refill, and also omits exceptions that can be caused by asynchronous external events such as an Interrupt. Although a Bus Error exception may be caused by the operation of a load or store instruction, this section does not list Bus Error for load and store instructions because the relationship between load and store instructions and external error indications, like Bus Error, are dependent upon the implementation.
Exceptions:
Integer Overflow
Figure 2-9 Example of Instruction Exception
An instruction may cause implementation-dependent exceptions that are not present in the Exceptions section.
2.1.9 Programming Notes and Implementation Notes Fields
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The Notes sections contain material that is useful for programmers and implementors, respectively, but that is not necessary to describe the instruction and does not belong in the description sections.
Programming Notes:
ADDU performs the same arithmetic operation but does not trap on overflow.
Figure 2-10 Example of Instruction Programming Notes
2.2 Operation Section Notation and Functions
In an instruction description, the Operation section uses a high-level language notation to describe the operation performed by each instruction. Special symbols used in the pseudocode are described in the previous chapter. Specific pseudocode functions are described below.
This section presents information about the following topics: • “Instruction Execution Ordering” on page 12
• “Pseudocode Functions” on page 12
2.2.1 Instruction Execution Ordering
Each of the high-level language statements in the Operations section are executed sequentially (except as constrained by conditional and loop constructs).
2.2.2 Pseudocode Functions
There are several functions used in the pseudocode descriptions. These are used either to make the pseudocode more readable, to abstract implementation-specific behavior, or both. These functions are defined in this section, and include the following:
• “Coprocessor General Register Access Functions” on page 12
• “Load Memory and Store Memory Functions” on page 14
• “Access Functions for Floating Point Registers” on page 16
• “Miscellaneous Functions” on page 18
2.2.2.1 Coprocessor General Register Access Functions
Defined coprocessors, except for CP0, have instructions to exchange words and doublewords between coprocessor general registers and the rest of the system. What a coprocessor does with a word or doubleword supplied to it and how a coprocessor supplies a word or doubleword is defined by the coprocessor itself. This behavior is abstracted into the functions described in this section.
COP_LW
The COP_LW function defines the action taken by coprocessor z when supplied with a word from memory during a load word operation. The action is coprocessor-specific. The typical action would be to store the contents of memword in coprocessor general register rt.
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2.2 Operation Section Notation and Functions
COP_LW (z, rt, memword)
z: The coprocessor unit number
rt: Coprocessor general register specifier
memword: A 32-bit word value supplied to the coprocessor
/* Coprocessor-dependent action */
endfunction COP_LW
Figure 2-11 COP_LW Pseudocode Function
COP_LD
The COP_LD function defines the action taken by coprocessor z when supplied with a doubleword from memory during a load doubleword operation. The action is coprocessor-specific. The typical action would be to store the contents of memdouble in coprocessor general register rt.
COP_LD (z, rt, memdouble)
z: The coprocessor unit number
rt: Coprocessor general register specifier
memdouble: 64-bit doubleword value supplied to the coprocessor.
/* Coprocessor-dependent action */
endfunction COP_LD
Figure 2-12 COP_LD Pseudocode Function
COP_SW
The COP_SW function defines the action taken by coprocessor z to supply a word of data during a store word operation. The action is coprocessor-specific. The typical action would be to supply the contents of the low-order word in coprocessor general register rt.
dataword ← COP_SW (z, rt)
z: The coprocessor unit number
rt: Coprocessor general register specifier dataword: 32-bit word value
/* Coprocessor-dependent action */
endfunction COP_SW
Figure 2-13 COP_SW Pseudocode Function
COP_SD
The COP_SD function defines the action taken by coprocessor z to supply a doubleword of data during a store doubleword operation. The action is coprocessor-specific. The typical action would be to supply the contents of the low-order doubleword in coprocessor general register rt.
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datadouble ← COP_SD (z, rt)
z: The coprocessor unit number
rt: Coprocessor general register specifier datadouble: 64-bit doubleword value
/* Coprocessor-dependent action */
endfunction COP_SD
Figure 2-14 COP_SD Pseudocode Function
2.2.2.2 Load Memory and Store Memory Functions
Regardless of byte ordering (big- or little-endian), the address of a halfword, word, or doubleword is the smallest byte address of the bytes that form the object. For big-endian ordering this is the most-significant byte; for a little-endian ordering this is the least-significant byte.
In the Operation pseudocode for load and store operations, the following functions summarize the handling of virtual addresses and the access of physical memory. The size of the data item to be loaded or stored is passed in the AccessLength field. The valid constant names and values are shown in Table 2-1. The bytes within the addressed unit of memory (word for 32-bit processors or doubleword for 64-bit processors) that are used can be determined directly from the AccessLength and the two or three low-order bits of the address.
AddressTranslation
The AddressTranslation function translates a virtual address to a physical address and its cache coherence algorithm, describing the mechanism used to resolve the memory reference.
Given the virtual address vAddr, and whether the reference is to Instructions or Data (IorD), find the corresponding physical address (pAddr) and the cache coherence algorithm (CCA) used to resolve the reference. If the virtual address is in one of the unmapped address spaces, the physical address and CCA are determined directly by the virtual address. If the virtual address is in one of the mapped address spaces then the TLB or fixed mapping MMU determines the physical address and access type; if the required translation is not present in the TLB or the desired access is not permitted, the function fails and an exception is taken.
(pAddr, CCA) ← AddressTranslation (vAddr, IorD, LorS)
/* pAddr: physical address */
/* CCA: Cache Coherence Algorithm, the method used to access caches*/
/* and memory and resolve the reference */
/* vAddr: virtual address */
/* IorD: Indicates whether access is for INSTRUCTION or DATA */
/* LorS: Indicates whether access is for LOAD or STORE */
/* See the address translation description for the appropriate MMU */
/* type in Volume III of this book for the exact translation mechanism */
endfunction AddressTranslation
Figure 2-15 AddressTranslation Pseudocode Function
LoadMemory
The LoadMemory function loads a value from memory.
/* AccessLength: Length, in bytes, of access */
/* pAddr:
/* vAddr:
/* IorD:
physical address */
virtual address */
Indicates whether access is for Instructions or Data */
endfunction LoadMemory
Figure 2-16 LoadMemory Pseudocode Function
StoreMemory
The StoreMemory function stores a value to memory.
The specified data is stored into the physical location pAddr using the memory hierarchy (data caches and main memory) as specified by the Cache Coherence Algorithm (CCA). The MemElem contains the data for an aligned, fixed-width memory element (a word for 32-bit processors, a doubleword for 64-bit processors), though only the bytes that are actually stored to memory need be valid. The low-order two (or three) bits of pAddr and the AccessLength field indicate which of the bytes within the MemElem data should be stored; only these bytes in memory will actually be changed.
StoreMemory (CCA, AccessLength, MemElem, pAddr, vAddr)
/* CCA: Cache Coherence Algorithm, the method used to access */ /* caches and memory and resolve the reference. */
/* AccessLength: Length, in bytes, of access */
/* MemElem:
/*
/*
/*
/* /*
/* pAddr:
/* vAddr:
Data in the width and alignment of a memory element. */
The width is the same size as the CPU general */
purpose register, either 4 or 8 bytes, */
aligned on a 4- or 8-byte boundary. For a */
partial-memory-element store, only the bytes that will be*/
stored must be valid.*/
physical address */
virtual address */
endfunction StoreMemory
Figure 2-17 StoreMemory Pseudocode Function
Prefetch
The Prefetch function prefetches data from memory.
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2.2 Operation Section Notation and Functions
This action uses cache and main memory as specified in both the Cache Coherence Algorithm (CCA) and the access (IorD) to find the contents of AccessLength memory bytes, starting at physical location pAddr. The data is returned in a fixed-width naturally aligned memory element (MemElem). The low-order 2 (or 3) bits of the address and the AccessLength indicate which of the bytes within MemElem need to be passed to the processor. If the memory access type of the reference is uncached, only the referenced bytes are read from memory and marked as valid within the memory element. If the access type is cached but the data is not present in cache, an implementation-specific size and alignment block of memory is read and loaded into the cache to satisfy a load reference. At a minimum, this block is the entire memory element.
MemElem ← LoadMemory (CCA, AccessLength, pAddr, vAddr, IorD)
/* MemElem:
/*
/*
/*
/* CCA: /*
Data is returned in a fixed width with a natural alignment. The */
width is the same size as the CPU general-purpose register, */
32 or 64 bits, aligned on a 32- or 64-bit boundary, */
respectively. */
Cache Coherence Algorithm, the method used to access caches */
and memory and resolve the reference */
Chapter 2 Guide to the Instruction Set
Prefetch is an advisory instruction for which an implementation-specific action is taken. The action taken may increase performance but must not change the meaning of the program or alter architecturally visible state.
Prefetch (CCA, pAddr, vAddr, DATA, hint)
/* CCA: Cache Coherence Algorithm, the method used to access */
/* caches and memory and resolve the reference. */
/* pAddr: physical address */
/* vAddr: virtual address */
/* DATA: Indicates that access is for DATA */
/* hint: hint that indicates the possible use of the data */
endfunction Prefetch
Figure 2-18 Prefetch Pseudocode Function
Table 2-1 lists the data access lengths and their labels for loads and stores.
Table 2-1 AccessLength Specifications for Loads/Stores
AccessLength Name
Value
Meaning
DOUBLEWORD
7
8 bytes (64 bits)
SEPTIBYTE
6
7 bytes (56 bits)
SEXTIBYTE
5
6 bytes (48 bits)
QUINTIBYTE
4
5 bytes (40 bits)
WORD
3
4 bytes (32 bits)
TRIPLEBYTE
2
3 bytes (24 bits)
HALFWORD
1
2 bytes (16 bits)
BYTE
0
1 byte (8 bits)
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2.2.2.3 Access Functions for Floating Point Registers
The pseudocode shown in below specifies how the unformatted contents loaded or moved to CP1 registers are interpreted to form a formatted value. If an FPR contains a value in some format, rather than unformatted contents from a load (uninterpreted), it is valid to interpret the value in that format (but not to interpret it in a different format).
ValueFPR
The ValueFPR function returns a formatted value from the floating point registers.
/* fpr:
/* fmt:
/*
/*
The FPR number */
The format of the data, one of: */
S, D, W, */
OB, QH, */
UNINTERPRETED_WORD, */
UNINTERPRETED_DOUBLEWORD */
/*
/*
/* The UNINTERPRETED values are used to indicate that the datatype */
/* is not known as, for example, in SWC1 and SDC1 */
case fmt of
S, W, UNINTERPRETED_WORD:
valueFPR ← FPR[fpr]
D, UNINTERPRETED_DOUBLEWORD: if (fpr0 ≠ 0) then
valueFPR ← UNPREDICTABLE else
valueFPR ← FPR[fpr+1] || FPR[fpr] endif
DEFAULT:
valueFPR ← UNPREDICTABLE
endcase
endfunction ValueFPR
Figure 2-19 ValueFPR Pseudocode Function
StoreFPR
The pseudocode shown below specifies the way a binary encoding representing a formatted value is stored into CP1 registers by a computational or move operation. This binary representation is visible to store or move-from instructions. Once an FPR receives a value from the StoreFPR(), it is not valid to interpret the value with ValueFPR() in a different format.
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2.2 Operation Section Notation and Functions
value ← ValueFPR(fpr, fmt)
/* value: The formattted value from the FPR */
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StoreFPR (fpr, fmt, value)
/* fpr:
/* fmt:
/*
/*
The FPR number */
The format of the data, one of: */
S, D, W, */
OB, QH, */
UNINTERPRETED_WORD, */
UNINTERPRETED_DOUBLEWORD */
/*
/*
/* value: The formattted value to be stored into the FPR */
/* The UNINTERPRETED values are used to indicate that the datatype */
/* is not known as, for example, in LWC1 and LDC1 */
case fmt of
S, W, UNINTERPRETED_WORD:
FPR[fpr] ← value
D, UNINTERPRETED_DOUBLEWORD: if (fpr0 ≠ 0) then
UNPREDICTABLE
else
FPR[fpr] ← value FPR[fpr+1] ← value
endif
endcase
endfunction StoreFPR
Figure 2-20 StoreFPR Pseudocode Function
2.2.2.4 Miscellaneous Functions
This section lists miscellaneous functions not covered in previous sections.
SyncOperation
The SyncOperation function orders loads and stores to synchronize shared memory.
This action makes the effects of the synchronizable loads and stores indicated by stype occur in the same order for all processors.
SyncOperation(stype)
/* stype: Type of load/store ordering to perform. */
/* Perform implementation-dependent operation to complete the */
/* required synchronization operation */
endfunction SyncOperation
Figure 2-21 SyncOperation Pseudocode Function
SignalException
The SignalException function signals an exception condition.
2.2 Operation Section Notation and Functions
This action results in an exception that aborts the instruction. The instruction operation pseudocode never sees a return from this function call.
SignalException(Exception, argument)
/* Exception: The exception condition that exists. */ /* argument: A exception-dependent argument, if any */
endfunction SignalException
Figure 2-22 SignalException Pseudocode Function
NullifyCurrentInstruction
The NullifyCurrentInstruction function nullifies the current instruction.
The instruction is aborted. For branch-likely instructions, nullification kills the instruction in the delay slot during its execution.
NullifyCurrentInstruction()
endfunction NullifyCurrentInstruction
Figure 2-23 NullifyCurrentInstruction PseudoCode Function
CoprocessorOperation
The CoprocessorOperation function performs the specified Coprocessor operation.
CoprocessorOperation (z, cop_fun)
/* z: Coprocessor unit number */
/* cop_fun: Coprocessor function from function field of instruction */
/* Transmit the cop_fun value to coprocessor z */
endfunction CoprocessorOperation
Figure 2-24 CoprocessorOperation Pseudocode Function
JumpDelaySlot
The JumpDelaySlot function is used in the pseudocode for the four PC-relative instructions. The function returns TRUE if the instruction at vAddr is executed in a jump delay slot. A jump delay slot always immediately follows a JR, JAL, JALR, or JALX instruction.
JumpDelaySlot(vAddr)
/* vAddr:Virtual address */
endfunction JumpDelaySlot
Figure 2-25 JumpDelaySlot Pseudocode Function
FPConditionCode
The FPConditionCode function returns the value of a specific floating point condition code.
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tf ←FPConditionCode(cc)
/* tf: The value of the specified condition code */ /* cc: The Condition code number in the range 0..7 */
if cc = 0 then FPConditionCode ← FCSR23
else
FPConditionCode ← FCSR24+cc
endif
endfunction FPConditionCode
Figure 2-26 FPConditionCode Pseudocode Function
SetFPConditionCode
The SetFPConditionCode function writes a new value to a specific floating point condition code.
SetFPConditionCode(cc)
if cc = 0 then
FCSR ← FCSR31..24 || tf || FCSR22..0 else
FCSR ← FCSR31..25+cc || tf || FCSR23+cc..0 endfunction SetFPConditionCode
Figure 2-27 SetFPConditionCode Pseudocode Function
2.3 Op and Function Subfield Notation
In some instructions, the instruction subfields op and function can have constant 5- or 6-bit values. When reference is made to these instructions, uppercase mnemonics are used. For instance, in the floating point ADD instruction, op=COP1 and function=ADD. In other cases, a single field has both fixed and variable subfields, so the name contains both upper- and lowercase characters.
2.4 FPU Instructions
In the detailed description of each FPU instruction, all variable subfields in an instruction format (such as fs, ft, immediate, and so on) are shown in lowercase. The instruction name (such as ADD, SUB, and so on) is shown in uppercase.
For the sake of clarity, an alias is sometimes used for a variable subfield in the formats of specific instructions. For example, rs=base in the format for load and store instructions. Such an alias is always lowercase since it refers to a variable subfield.
Bit encodings for mnemonics are given in Volume I, in the chapters describing the CPU, FPU, MDMX, and MIPS16 instructions.
See Section 2.3 , “Op and Function Subfield Notation” on page 20 for a description of the op and function subfields.
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endif
Chapter 3
The MIPS32TM Instruction Set
3.1 Compliance and Subsetting
To be compliant with the MIPS32 Architecture, designs must implement a set of required features, as described in this document set. To allow flexibility in implementations, the MIPS32 Architecture does provide subsetting rules. An implementation that follows these rules is compliant with the MIPS32 Architecture as long as it adheres strictly to the rules, and fully implements the remaining instructions.
The instruction set subsetting rules are as follows:
• All CPU instructions must be implemented – no subsetting is allowed.
• The FPU and related support instructions, including the MOVF and MOVT CPU instructions, may be omitted. Software may determine if an FPU is implemented by checking the state of the FP bit in the Config1 CP0 register. If the FPU is implemented, it must include S, D, and W formats, operate instructions, and all supporting instructions. Software may determine which FPU data types are implemented by checking the appropriate bit in the FIR CP1 register. The following allowable FPU subsets are compliant with the MIPS32 architecture:
– No FPU
– FPU with S, D, and W formats and all supporting instructions –
• Coprocessor 2 is optional and may be omitted. Software may determine if Coprocessor 2 is implemented by checking the state of the C2 bit in the Config1 CP0 register. If Coprocessor 2 is implemented, the Coprocessor 2 interface instructions (BC2, CFC2, COP2, CTC2, LDC2, LWC2, MFC2, MTC2, SDC2, and SWC2) may be omitted on an instruction by instruction basis.
• Instruction fields that are marked “Reserved” or shown as “0” in the description of that field are reserved for future use by the architecture and are not available to implementations. Implementations may only use those fields that are explicitly reserved for implementation dependent use.
• SupportedASEsareoptionalandmaybesubsettedout.Ifmostcases,softwaremaydetermineifasupportedASEis implemented by checking the appropriate bit in the Config1 or Config3 CP0 register. If they are implemented, they must implement the entire ISA applicable to the component, or implement subsets that are approved by the ASE specifications.
• If any instruction is subsetted out based on the rules above, an attempt to execute that instruction must cause the appropriate exception (typically Reserved Instruction or Coprocessor Unusable).
Supersetting of the MIPS32 ISA is only allowed by adding functions to the SPECIAL2 major opcode or by adding instructions to support Coprocessor 2.
3.2 Alphabetical List of Instructions
Table 3-1 through Table 3-23 provide a list of instructions grouped by category. Individual instruction descriptions follow the tables, arranged in alphabetical order.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 21
Chapter 3 The MIPS32TM Instruction Set
Table 3-1 CPU Arithmetic Instructions
Mnemonic
Instruction
ADD
Add Word
ADDI
Add Immediate Word
ADDIU
Add Immediate Unsigned Word
ADDU
Add Unsigned Word
CLO
Count Leading Ones in Word
CLZ
Count Leading Zeros in Word
DIV
Divide Word
DIVU
Divide Unsigned Word
MADD
Multiply and Add Word to Hi, Lo
MADDU
Multiply and Add Unsigned Word to Hi, Lo
MSUB
Multiply and Subtract Word to Hi, Lo
MSUBU
Multiply and Subtract Unsigned Word to Hi, Lo
MUL
Multiply Word to GPR
MULT
Multiply Word
MULTU
Multiply Unsigned Word
SLT
Set on Less Than
SLTI
Set on Less Than Immediate
SLTIU
Set on Less Than Immediate Unsigned
SLTU
Set on Less Than Unsigned
SUB
Subtract Word
SUBU
Subtract Unsigned Word
Table 3-2 CPU Branch and Jump Instructions
Mnemonic
Instruction
B
Unconditional Branch
BAL
Branch and Link
BEQ
Branch on Equal
BGEZ
Branch on Greater Than or Equal to Zero
BGEZAL
Branch on Greater Than or Equal to Zero and Link
BGTZ
Branch on Greater Than Zero
BLEZ
Branch on Less Than or Equal to Zero
BLTZ
Branch on Less Than Zero
22 MIPS32TM Architecture For Programmers Volume II, Revision 0.95
3.2 Alphabetical List of Instructions
Table 3-2 CPU Branch and Jump Instructions
Mnemonic
Instruction
BLTZAL
Branch on Less Than Zero and Link
BNE
Branch on Not Equal
J
Jump
JAL
Jump and Link
JALR
Jump and Link Register
JR
Jump Register
Table 3-3 CPU Instruction Control Instructions
Table 3-4 CPU Load, Store, and Memory Control Instructions
Mnemonic
Instruction
NOP
No Operation
SSNOP
Superscalar No Operation
Mnemonic
Instruction
LB
Load Byte
LBU
Load Byte Unsigned
LH
Load Halfword
LHU
Load Halfword Unsigned
LL
Load Linked Word
LW
Load Word
LWL
Load Word Left
LWR
Load Word Right
PREF
Prefetch
SB
Store Byte
SC
Store Conditional Word
SD
Store Doubleword
SH
Store Halfword
SW
Store Word
SWL
Store Word Left
SWR
Store Word Right
SYNC
Synchronize Shared Memory
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Chapter 3 The MIPS32TM Instruction Set
Table 3-5 CPU Logical Instructions
Mnemonic
Instruction
AND
And
ANDI
And Immediate
LUI
Load Upper Immediate
NOR
Not Or
OR
Or
ORI
Or Immediate
XOR
Exclusive Or
XORI
Exclusive Or Immediate
Table 3-6 CPU Move Instructions
Mnemonic
Instruction
MFHI
Move From HI Register
MFLO
Move From LO Register
MOVF
Move Conditional on Floating Point False
MOVN
Move Conditional on Not Zero
MOVT
Move Conditional on Floating Point True
MOVZ
Move Conditional on Zero
MTHI
Move To HI Register
MTLO
Move To LO Register
Table 3-7 CPU Shift Instructions
Mnemonic
Instruction
SLL
Shift Word Left Logical
SLLV
Shift Word Left Logical Variable
SRA
Shift Word Right Arithmetic
SRAV
Shift Word Right Arithmetic Variable
SRL
Shift Word Right Logical
SRLV
Shift Word Right Logical Variable
24 MIPS32TM Architecture For Programmers Volume II, Revision 0.95
3.2 Alphabetical List of Instructions
Table 3-8 CPU Trap Instructions
Mnemonic
Instruction
BREAK
Breakpoint
SYSCALL
System Call
TEQ
Trap if Equal
TEQI
Trap if Equal Immediate
TGE
Trap if Greater or Equal
TGEI
Trap if Greater of Equal Immediate
TGEIU
Trap if Greater or Equal Immediate Unsigned
TGEU
Trap if Greater or Equal Unsigned
TLT
Trap if Less Than
TLTI
Trap if Less Than Immediate
TLTIU
Trap if Less Than Immediate Unsigned
TLTU
Trap if Less Than Unsigned
TNE
Trap if Not Equal
TNEI
Trap if Not Equal Immediate
Table 3-9 Obsoletea CPU Branch Instructions
Mnemonic
Instruction
BEQL
Branch on Equal Likely
BGEZALL
Branch on Greater Than or Equal to Zero and Link Likely
BGEZL
Branch on Greater Than or Equal to Zero Likely
BGTZL
Branch on Greater Than Zero Likely
BLEZL
Branch on Less Than or Equal to Zero Likely
BLTZALL
Branch on Less Than Zero and Link Likely
BLTZL
Branch on Less Than Zero Likely
BNEL
Branch on Not Equal Likely
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
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Chapter 3 The MIPS32TM Instruction Set
Table 3-10 FPU Arithmetic Instructions
Mnemonic
Instruction
ABS.fmt
Floating Point Absolute Value
ADD.fmt
Floating Point Add
DIV.fmt
Floating Point Divide
MADD.fmt
Floating Point Multiply Add
MSUB.fmt
Floating Point Multiply Subtract
MUL.fmt
Floating Point Multiply
NEG.fmt
Floating Point Negate
NMADD.fmt
Floating Point Negative Multiply Add
NMSUB.fmt
Floating Point Negative Multiply Subtract
RECIP.fmt
Reciprocal Approximation
RSQRT.fmt
Reciprocal Square Root Approximation
SQRT
Floating Point Square Root
SUB.fmt
Floating Point Subtract
Table 3-11 FPU Branch Instructions
Table 3-12 FPU Compare Instructions
Table 3-13 FPU Convert Instructions
Mnemonic
Instruction
BC1F
Branch on FP False
BC1T
Branch on FP True
Mnemonic
Instruction
C.cond.fmt
Floating Point Compare
Mnemonic
Instruction
CEIL.W.fmt
Floating Point Ceiling Convert to Word Fixed Point
CVT.D.fmt
Floating Point Convert to Double Floating Point
CVT.S.fmt
Floating Point Convert to Single Floating Point
CVT.W.fmt
Floating Point Convert to Word Fixed Point
FLOOR.W.fmt
Floating Point Floor Convert to Word Fixed Point
ROUND.W.fmt
Floating Point Round to Word Fixed Point
TRUNC.W.fmt
Floating Point Truncate to Word Fixed Point
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Table 3-14 FPU Load, Store, and Memory Control Instructions
3.2 Alphabetical List of Instructions
Mnemonic
Instruction
LDC1
Load Doubleword to Floating Point
LWC1
Load Word to Floating Point
SDC1
Store Doubleword from Floating Point
SWC1
Store Word from Floating Point
Table 3-15 FPU Move Instructions
Mnemonic
Instruction
CFC1
Move Control Word from Floating Point
CTC1
Move Control Word to Floating Point
MFC1
Move Word from Floating Point
MOV.fmt
Floating Point Move
MOVF.fmt
Floating Point Move Conditional on Floating Point False
MOVN.fmt
Floating Point Move Conditional on Not Zero
MOVT.fmt
Floating Point Move Conditional on Floating Point True
MOVZ.fmt
Floating Point Move Conditional on Zero
MTC1
Move Word to Floating Point
Table 3-16 Obsoletea FPU Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Table 3-17 Coprocessor Branch Instructions
Table 3-18 Coprocessor Execute Instructions
Mnemonic
Instruction
BC1FL
Branch on FP False Likely
BC1TL
Branch on FP True Likely
Mnemonic
Instruction
BC2F
Branch on COP2 False
BC2T
Branch on COP2 True
Mnemonic
Instruction
COP2
Coprocessor Operation to Coprocessor 2
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Chapter 3 The MIPS32TM Instruction Set
Table 3-19 Coprocessor Load and Store Instructions
Mnemonic
Instruction
LDC2
Load Doubleword to Coprocessor 2
LWC2
Load Word to Coprocessor 2
SDC2
Store Doubleword from Coprocessor 2
SWC2
Store Word from Coprocessor 2
Table 3-20 Coprocessor Move Instructions
Mnemonic
Instruction
CFC2
Move Control Word from Coprocessor 2
CTC2
Move Control Word to Coprocessor 2
MFC2
Move Word from Coprocessor 2
MTC2
Move Word to Coprocessor 2
Table 3-21 Obsoletea Coprocessor Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Table 3-22 Privileged Instructions
Mnemonic
Instruction
BC2FL
Branch on COP2 False Likely
BC2TL
Branch on COP2 True Likely
Mnemonic
Instruction
CACHE
Perform Cache Operation
ERET
Exception Return
MFC0
Move from Coprocessor 0
MTC0
Move to Coprocessor 0
TLBP
Probe TLB for Matching Entry
TLBR
Read Indexed TLB Entry
TLBWI
Write Indexed TLB Entry
TLBWR
Write Random TLB Entry
WAIT
Enter Standby Mode
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Table 3-23 EJTAG Instructions
3.2 Alphabetical List of Instructions
Mnemonic
Instruction
DERET
Debug Exception Return
SDBBP
Software Debug Breakpoint
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 29
ABS.fmt
Floating Point Absolute Value
ABS.fmt
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: ABS.S fd, fs MIPS32 (MIPS I) ABS.D fd, fs MIPS32 (MIPS I)
Purpose:
To compute the absolute value of an FP value
Description:fd ← abs(fs)
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause
bits are ORed into the Flag bits if no exception is taken.
This operation is arithmetic; a NaN operand signals invalid operation.
Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-
DICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE. Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation
COP1 010001
fmt
0 00000
fs
fd
ABS 000101
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ADD
Add Word
ADD
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: ADD rd, rs, rt MIPS32 (MIPS I) Purpose:
To add 32-bit integers. If an overflow occurs, then trap.
Description: rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rd. Restrictions:
None
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] ← temp endif
Exceptions:
Integer Overflow
Programming Notes:
ADDU performs the same arithmetic operation but does not trap on overflow.
SPECIAL 000000
rs
rt
rd
0 00000
ADD 100000
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32 MIPS32TM Architecture For Programmers Volume II, Revision 0.95
ADD.fmt
Floating Point Add
ADD.fmt
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: ADD.S fd, fs, ft MIPS32 (MIPS I) ADD.D fd, fs, ft MIPS32 (MIPS I)
Purpose:
To add floating point values
Description: fd ← fs + ft
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-
DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the
operand FPRs becomes UNPREDICTABLE. Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) +fmt ValueFPR(ft, fmt)) Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow
COP1 010001
fmt
ft
fs
fd
ADD 000000
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 33
ADDI
Add Immediate Word
ADDI
31
26 25 21 20 16 15
655 16
Format: ADDI rt, rs, immediate Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
0
MIPS32 (MIPS I)
ADDI 001000
rs
rt
immediate
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt. Restrictions:
None
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 ≠ temp31 then
SignalException(IntegerOverflow)
else
GPR[rt] ← temp endif
Exceptions:
Integer Overflow
Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.
ADDIU
Add Immediate Unsigned Word
ADDIU
31
26 25 21 20 16 15
655 16
Format: ADDIU rt, rs, immediate Purpose:
To add a constant to a 32-bit integer
0
MIPS32 (MIPS I)
ADDIU 001001
rs
rt
immediate
Description: rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rt.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp ← GPR[rs] + sign_extend(immediate) GPR[rt]← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith- metic environments that ignore overflow, such as C language arithmetic.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 35
ADDU
Add Unsigned Word
ADDU
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: ADDU rd, rs, rt MIPS32 (MIPS I) Purpose:
To add 32-bit integers
Description: rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rd.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp ← GPR[rs] + GPR[rt] GPR[rd] ← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith- metic environments that ignore overflow, such as C language arithmetic.
SPECIAL 000000
rs
rt
rd
0 00000
ADDU 100001
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
AND
And
AND
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: AND rd, rs, rt MIPS32 (MIPS I) Purpose:
To do a bitwise logical AND
Description: rd ← rs AND rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is
placed into GPR rd. Restrictions:
None
Operation:
GPR[rd] ← GPR[rs] and GPR[rt] Exceptions:
None
SPECIAL 000000
rs
rt
rd
0 00000
AND 100100
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 37
ANDI
And Immediate
ANDI
31
26 25 21 20 16 15
655 16
Format: ANDI rt, rs, immediate Purpose:
To do a bitwise logical AND with a constant
0
MIPS32 (MIPS I)
ANDI 001100
rs
rt
immediate
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: rt ← rs AND immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND
operation. The result is placed into GPR rt. Restrictions:
None
Operation:
GPR[rt] ← GPR[rs] and zero_extend(immediate)
Exceptions:
None
B
Unconditional Branch
B
31
26 25 21 20 16 15
655 16
Format: B offset Purpose:
To do an unconditional branch
0
Assembly Idiom
BEQ 000100
0 00000
0 00000
offset
Description: branch
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the
hardware as BEQ r0, r0, offset.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) I+1: PC ← PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 39
BAL
Branch and Link
BAL
31
26 25 21 20 16 15
655 16
Format: BAL rs, offset Purpose:
To do an unconditional PC-relative procedure call
0
Assembly Idiom
REGIMM 000001
0 00000
BGEZAL 10001
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: procedure_call
BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the
hardware as BGEZAL r0, offset.
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset ← sign_extend(offset || 02) GPR[31] ← PC + 8
I+1: PC ← PC + target_offset Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
BC1F
Branch on FP False
BC1F
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1F offset (cc = 0 implied) BC1F cc, offset
Purpose:
To test an FP condition code and do a PC-relative conditional branch
Description: if cc = 0 then branch
0
MIPS32 (MIPS I) MIPS32 (MIPS IV)
COP1 010001
BC 01000
cc
nd 0
tf 0
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 0
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
endif
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 41
Branch on FP False (cont.)
BC1F
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
BC1FL
Branch on FP False Likely
BC1FL
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1FL offset (cc = 0 implied) BC1FL cc, offset
Purpose:
0
MIPS32 (MIPS II) MIPS32 (MIPS IV)
COP1 010001
BC 01000
cc
nd 1
tf 0
offset
To test an FP condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description: if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con- dition Code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 0
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 43
Branch on FP False Likely (cont.)
BC1FL
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC1F instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS II andIII architectionrs there must be at least one instruction between the compare instruction that sets a condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
BC1T
Branch on FP True
BC1T
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1T offset (cc = 0 implied) BC1T cc, offset
Purpose:
To test an FP condition code and do a PC-relative conditional branch
Description: if cc = 1 then branch
0
MIPS32 (MIPS I) MIPS32 (MIPS IV)
COP1 010001
BC 01000
cc
nd 0
tf 1
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 1
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
endif
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 45
Branch on FP True (cont.)
BC1T
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
BC1TL
Branch on FP True Likely
BC1TL
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1TL offset (cc = 0 implied) BC1TL cc, offset
Purpose:
0
MIPS32 (MIPS II) MIPS32 (MIPS IV)
COP1 010001
BC 01000
cc
nd 1
tf 1
offset
To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description: if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con- dition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 1
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 47
Branch on FP True Likely (cont.)
BC1TL
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC1T instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS II andIII architectionrs there must be at least one instruction between the compare instruction that sets a condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
BC2F
Branch on COP2 False
BC2F
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2F offset (cc = 0 implied) BC2F cc, offset
Purpose:
To test a COP2 condition code and do a PC-relative conditional branch
Description: if cc = 0 then branch
0
MIPS32 (MIPS I) MIPS32 (MIPS IV)
COP2 010010
BC 01000
cc
nd 0
tf 0
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: condition ← COP2Condition(cc) = 0
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
endif
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 49
BC2FL
Branch on COP2 False Likely
BC2FL
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2FL offset (cc = 0 implied) BC2FL cc, offset
Purpose:
0
MIPS32 (MIPS II) MIPS32 (MIPS IV)
COP2 010010
BC 01000
cc
nd 1
tf 0
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
To test a COP2 condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description: if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: I+1:
condition ← COP2Condition(cc) = 0
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02 if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on COP2 False Likely (cont.)
BC2FL
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC2F instruction instead.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 51
BC2T
Branch on COP2 True
BC2T
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2T offset (cc = 0 implied) BC2T cc, offset
Purpose:
To test a COP2 condition code and do a PC-relative conditional branch
Description: if cc = 1 then branch
0
MIPS32 (MIPS I) MIPS32 (MIPS IV)
COP2 010010
BC 01000
cc
nd 0
tf 1
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: condition ← COP2Condition(cc) = 1
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
endif
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
BC2TL
Branch on COP2 True Likely
BC2TL
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2TL offset (cc = 0 implied) BC2TL cc, offset
Purpose:
0
MIPS32 (MIPS II) MIPS32 (MIPS IV)
COP2 010010
BC 01000
cc
nd 1
tf 1
offset
To test a COP2 condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description: if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: condition ← COP2Condition(cc) = 1
target_offset ← (offset15)GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 53
Branch on COP2 True Likely (cont.)
BC2TL
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC2T instruction instead.
BEQ
Branch on Equal
BEQ
31
26 25 21 20 16 15
655 16
Format: BEQ rs, rt, offset Purpose:
To compare GPRs then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
BEQ 000100
rs
rt
offset
Description: if rs = rt then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] = GPR[rt])
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
BEQ r0, r0 offset, expressed as B offset, is the assembly idiom used to denote an unconditional branch.
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 55
BEQL
Branch on Equal Likely
BEQL
31
26 25 21 20 16 15 0
655 16
Format: BEQL rs, rt, offset MIPS32 (MIPS II) Purpose:
To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs = rt then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are equal, branch to the target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
BEQL 010100
rs
rt
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Operation:
I: I+1:
target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] = GPR[rt])
if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Branch on Equal Likely (cont.)
BEQL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BEQ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 57
BGEZ
Branch on Greater Than or Equal to Zero
BGEZ
31
26 25 21 20 16 15
655 16
Format: BGEZ rs, offset Purpose:
To test a GPR then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
REGIMM 000001
rs
BGEZ 00001
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: if rs ≥ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
None
BGEZAL
Branch on Greater Than or Equal to Zero and Link
BGEZAL
31
26 25 21 20 16 15
655 16
Format: BGEZAL rs, offset Purpose:
To test a GPR then do a PC-relative conditional procedure call
0
MIPS32 (MIPS I)
REGIMM 000001
rs
BGEZAL 10001
offset
Description: if rs ≥ 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN
GPR[31] ← PC + 8
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
BGEZAL r0, offset, expressed as BAL offset, is the assembly idiom used to denote a PC-relative branch and link. BAL is used in a manner similar to JAL, but provides PC-relative addressing and a more limited target PC range.
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 59
BGEZALL
Branch on Greater Than or Equal to Zero and Link Likely
BGEZALL
31
26 25 21 20 16 15
655 16
Format: BGEZALL rs, offset Purpose:
0
MIPS32 (MIPS II)
REGIMM 000001
rs
BGEZALL 10011
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
Description: if rs ≥ 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
I:
I+1:
Exceptions:
None
target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN
GPR[31] ← PC + 8
if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on Greater Than or Equal to Zero and Link Likely (con’t.) BGEZALL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGEZAL instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 61
BGEZL
Branch on Greater Than or Equal to Zero Likely
BGEZL
31
26 25 21 20 16 15
655 16
Format: BGEZL rs, offset Purpose:
0
MIPS32 (MIPS II)
REGIMM 000001
rs
BGEZL 00011
offset
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To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs ≥ 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: I+1:
Exceptions: None
target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN
if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on Greater Than or Equal to Zero Likely (cont.) BGEZL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGEZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 63
BGTZ
Branch on Greater Than Zero
BGTZ
31
26 25 21 20 16 15
655 16
Format: BGTZ rs, offset Purpose:
To test a GPR then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
BGTZ 000111
rs
0 00000
offset
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MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: if rs > 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] > 0GPRLEN
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
None
BGTZL
Branch on Greater Than Zero Likely
BGTZL
31
26 25 21 20 16 15 0
655 16
Format: BGTZL rs, offset MIPS32 (MIPS II) Purpose:
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs > 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not exe- cuted.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] > 0GPRLEN
I+1: if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
BGTZL 010111
rs
0 00000
offset
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 65
Branch on Greater Than Zero Likely (cont.)
BGTZL
66
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGTZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
BLEZ
Branch on Less Than or Equal to Zero
BLEZ
31
26 25 21 20 16 15
655 16
Format: BLEZ rs, offset Purpose:
To test a GPR then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
BLEZ 000110
rs
0 00000
offset
Description: if rs ≤ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≤ 0GPRLEN
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 67
BLEZL
Branch on Less Than or Equal to Zero Likely
BLEZL
31
26 25 21 20 16 15 0
655 16
Format: BLEZL rs, offset MIPS32 (MIPS II) Purpose:
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs ≤ 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
BLEZL 010110
rs
0 00000
offset
68
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Operation:
I: I+1:
Exceptions:
None
target_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≤ 0GPRLEN
if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on Less Than or Equal to Zero Likely (cont.)
BLEZL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLEZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 69
BLTZ
Branch on Less Than Zero
BLTZ
31
26 25 21 20 16 15
655 16
Format: BLTZ rs, offset Purpose:
To test a GPR then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
REGIMM 000001
rs
BLTZ 00000
offset
70
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: if rs < 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
Exceptions:
None
BLTZAL
Branch on Less Than Zero and Link
BLTZAL
31
26 25 21 20 16 15
655 16
Format: BLTZAL rs, offset Purpose:
To test a GPR then do a PC-relative conditional procedure call
0
MIPS32 (MIPS I)
REGIMM 000001
rs
BLTZAL 10000
offset
Description: if rs < 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN
GPR[31] ← PC + 8
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 71
BLTZALL
Branch on Less Than Zero and Link Likely
BLTZALL
31
26 25 21 20 16 15 0
655 16
Format: BLTZALL rs, offset MIPS32 (MIPS II) Purpose:
To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
Description: if rs < 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
REGIMM 000001
rs
BLTZALL 10010
offset
72
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Operation:
I:
I+1:
Exceptions:
None
target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN
GPR[31] ← PC + 8
if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on Less Than Zero and Link Likely (cont.)
BLTZALL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLTZAL instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 73
BLTZL
Branch on Less Than Zero Likely
BLTZL
31
26 25 21 20 16 15 0
655 16
Format: BLTZL rs, offset MIPS32 (MIPS II) Purpose:
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs < 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
REGIMM 000001
rs
BLTZL 00010
offset
74
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Operation:
I: I+1:
Exceptions:
None
target_offset ← sign_extend(offset || 02) condition ← GPR[rs] < 0GPRLEN
if condition then
PC ← PC + target_offset else
NullifyCurrentInstruction()
endif
Branch on Less Than Zero Likely (cont.)
BLTZL
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLTZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 75
BNE
Branch on Not Equal
BNE
31
26 25 21 20 16 15
655 16
Format: BNE rs, rt, offset Purpose:
To compare GPRs then do a PC-relative conditional branch
0
MIPS32 (MIPS I)
BNE 000101
rs
rt
offset
76
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Description: if rs ≠ rt then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] ≠ GPR[rt])
I+1: if condition then
PC ← PC + target_offset
endif
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Exceptions:
None
BNEL
Branch on Not Equal Likely
BNEL
31
26 25 21 20 16 15 0
655 16
Format: BNEL rs, rt, offset MIPS32 (MIPS II) Purpose:
To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if rs ≠ rt then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) condition ← (GPR[rs] ≠ GPR[rt])
I+1: if condition then
PC ← PC + target_offset
else
NullifyCurrentInstruction()
endif
BNEL 010101
rs
rt
offset
Exceptions:
None
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 77
Branch on Not Equal Likely (cont.)
BNEL
78
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is ± 128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BNE instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction Exception.
BREAK
Breakpoint
BREAK
31
26 25 6 5 0
6 20 6
Format: BREAK MIPS32 (MIPS I) Purpose:
To cause a Breakpoint exception
Description:
A breakpoint exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
Restrictions:
None
Operation:
SignalException(Breakpoint)
Exceptions:
Breakpoint
SPECIAL 000000
code
BREAK 001101
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 79
C.cond.fmt
Floating Point Compare
C.cond.fmt
31
26 25 21 20 16 15 11 10 8 7 6 5 4 3 0
655531124
COP1 010001
fmt
ft
fs
cc
0
A 0
FC 11
cond
80
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Format: C.cond.S fs, ft (cc = 0 implied) C.cond.D fs, ft (cc = 0 implied)
C.cond.S cc, fs, ft
C.cond.D cc, fs, ft
Purpose:
To compare FP values and record the Boolean result in a condition code
MIPS32 (MIPS I)
MIPS32 (MIPS I) MIPS32 (MIPS IV) MIPS32 (MIPS IV)
Description: cc ← fs compare_cond ft
The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The comparison is exact and nei-
ther overflows nor underflows.
If the comparison specified by cond2..1 is true for the operand values, the result is true; otherwise, the result is false. If
no exception is taken, the result is written into condition code CC; true is 1 and false is 0.
If one of the values is an SNaN, or cond3 is set and at least one of the values is a QNaN, an Invalid Operation condi- tion is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise, the Boolean result is written into condition code CC.
There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0.
The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal, equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Bool- ean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP val- ues in the equation. If the equal relation is true, for example, then all four example predicates above yield a true result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result.
Logical negation of a compare result allows eight distinct comparisons to test for the 16 predicates as shown in . Each mnemonic tests for both a predicate and its logical negation. For each mnemonic, compare tests the truth of the first predicate. When the first predicate is true, the result is true as shown in the “If Predicate Is True” column, and the sec- ond predicate must be false, and vice versa. (Note that the False predicate is never true and False/True do not follow the normal pattern.)
The truth of the second predicate is the logical negation of the instruction result. After a compare instruction, test for the truth of the first predicate can be made with the Branch on FP True (BC1T) instruction and the truth of the second can be made with Branch on FP False (BC1F).
Floating Point Compare (cont.)
C.cond.fmt
Table 3-24 shows another set of eight compare operations, distinguished by a cond3 value of 1 and testing the same 16 conditions. For these additional comparisons, if at least one of the operands is a NaN, including Quiet NaN, then an Invalid Operation condition is raised. If the Invalid Operation condition is enabled in the FCSR, an Invalid Operation exception occurs.
Table 3-24 FPU Comparisons Without Special Operand Exceptions
Instruction
Comparison Predicate
Comparison CC Result
Instruction
Cond Mnemonic
Name of Predicate and
Logically Negated Predicate (Abbreviation)
Relation Values
If Predicate Is True
Inv Op Excp. if QNaN ?
Condition Field
>
<
=
?
3
2..0
F
False [this predicate is always False]
F
F
F
F
F
No
0
0
True (T)
T
T
T
T
UN
Unordered
F
F
F
T
T
1
Ordered (OR)
T
T
T
F
F
EQ
Equal
F
F
T
F
T
2
Not Equal (NEQ)
T
T
F
T
F
UEQ
Unordered or Equal
F
F
T
T
T
3
Ordered or Greater Than or Less Than (OGL)
T
T
F
F
F
OLT
Ordered or Less Than
F
T
F
F
T
4
Unordered or Greater Than or Equal (UGE)
T
F
T
T
F
ULT
Unordered or Less Than
F
T
F
T
T
5
Ordered or Greater Than or Equal (OGE)
T
F
T
F
F
OLE
Ordered or Less Than or Equal
F
T
T
F
T
6
Unordered or Greater Than (UGT)
T
F
F
T
F
ULE
Unordered or Less Than or Equal
F
T
T
T
T
7
Ordered or Greater Than (OGT)
T
F
F
F
F
Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 81
Floating Point Compare (cont.)
C.cond.fmt
Table 3-25 FPU Comparisons With Special Operand Exceptions for QNaNs
Instruction
Comparison Predicate
Comparison CC Result
Instructio n
Cond Mnemonic
Name of Predicate and
Logically Negated Predicate (Abbreviation)
Relation Values
If Predicate Is True
Inv Op Excp If QNaN?
Condition Field
>
<
=
?
3
2..0
SF
Signaling False [this predicate always False]
F
F
F
F
F
Yes
1
0
Signaling True (ST)
T
T
T
T
NGLE
Not Greater Than or Less Than or Equal
F
F
F
T
T
1
Greater Than or Less Than or Equal (GLE)
T
T
T
F
F
SEQ
Signaling Equal
F
F
T
F
T
2
Signaling Not Equal (SNE)
T
T
F
T
F
NGL
Not Greater Than or Less Than
F
F
T
T
T
3
Greater Than or Less Than (GL)
T
T
F
F
F
LT
Less Than
F
T
F
F
T
4
Not Less Than (NLT)
T
F
T
T
F
NGE
Not Greater Than or Equal
F
T
F
T
T
5
Greater Than or Equal (GE)
T
F
T
F
F
LE
Less Than or Equal
F
T
T
F
T
6
Not Less Than or Equal (NLE)
T
F
F
T
F
NGT
Not Greater Than
F
T
T
T
T
7
Greater Than (GT)
T
F
F
F
F
Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False
82 MIPS32TM Architecture For Programmers Volume II, Revision 0.95
Floating Point Compare (cont.)
C.cond.fmt
Restrictions:
The fields fs and ft must specify FPRs valid for operands of type fmt; if they are not valid, the result is UNPREDICT-
ABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the
operand FPRs becomes UNPREDICTABLE.
Operation:
if SNaN(ValueFPR(fs, fmt)) or SNaN(ValueFPR(ft, fmt)) or QNaN(ValueFPR(fs, fmt)) or QNaN(ValueFPR(ft, fmt)) then less ← false
equal ← false
unordered ← true
if (SNaN(ValueFPR(fs,fmt)) or SNaN(ValueFPR(ft,fmt))) or
(cond3 and (QNaN(ValueFPR(fs,fmt)) or QNaN(ValueFPR(ft,fmt)))) then
SignalException(InvalidOperation)
endif
else
less ← ValueFPR(fs, fmt)
The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied
bits; the word result is placed in GPR rd. The bit-shift amount is specified by sa. Restrictions:
None Operation:
s ←sa
temp ← (GPR[rt]31)s || GPR[rt]31..s GPR[rd]← temp
Exceptions: None
SPECIAL 000000
0 00000
rt
rd
sa
SRA 000011
200
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
SRAV
Shift Word Right Arithmetic Variable
SRAV
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SRAV rd, rt, rs MIPS32 (MIPS I) Purpose:
To execute an arithmetic right-shift of a word by a variable number of bits
Description: rd ← rt >> rs (arithmetic)
The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied
bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. Restrictions:
None Operation:
s ← GPR[rs]4..0
temp ← (GPR[rt]31)s || GPR[rt]31..s GPR[rd]← temp
Exceptions:
None
SPECIAL 000000
rs
rt
rd
0 00000
SRAV 000111
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 201
SRL
Shift Word Right Logical
SRL
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SRL rd, rt, sa MIPS32 (MIPS I) Purpose:
To execute a logical right-shift of a word by a fixed number of bits
Description: rd ← rt >> sa (logical)
The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word
result is placed in GPR rd. The bit-shift amount is specified by sa. Restrictions:
None Operation:
s ←sa
temp ← 0s || GPR[rt]31..s GPR[rd]← temp
Exceptions:
None
SPECIAL 000000
0 00000
rt
rd
sa
SRL 000010
202
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
SRLV
Shift Word Right Logical Variable
SRLV
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SRLV rd, rt, rs MIPS32 (MIPS I) Purpose:
To execute a logical right-shift of a word by a variable number of bits
Description: rd ← rt >> rs (logical)
The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word
result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. Restrictions:
None Operation:
s ← GPR[rs]4..0
temp ← 0s || GPR[rt]31..s GPR[rd]← temp
Exceptions:
None
SPECIAL 000000
rs
rt
rd
0 00000
SRLV 000110
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 203
SSNOP
Superscalar No Operation
SSNOP
31
26 25 21 20 16 15 11 10 6 5
655556
Format: SSNOP Purpose:
Break superscalar issue on a superscalar processor.
Description:
0
MIPS32
SPECIAL 000000
0 00000
0 00000
0 00000
1 00001
SLL 000000
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SSNOP is the assembly idiom used to denote superscalar no operation. The actual instruction is interpreted by the hardware as SLL r0, r0, 1.
This instruction alters the instruction issue behavior on a superscalar processor by forcing the SSNOP instruction to single-issue. The processor must then end the current instruction issue between the instruction previous to the SSNOP and the SSNOP. The SSNOP then issues alone in the next issue slot.
On a single-issue processor, this instruction is a NOP that takes an issue slot.
Restrictions:
None
Operation: None
Exceptions:
None
Programming Notes:
SSNOP is intended for use primarily to allow the programmer control over CP0 hazards by converting instructions into cycles in a superscalar processor. For example, to insert at least two cycles between an MTC0 and an ERET, one would use the following sequence:
mtc0 x,y ssnop ssnop eret
Based on the normal issues rules of the processor, the MTC0 issues in cycle T. Because the SSNOP instructions must issue alone, they may issue no earlier than cycle T+1 and cycle T+2, respectively. Finally, the ERET issues no earlier than cycle T+3. Note that although the instruction after an SSNOP may issue no earlier than the cycle after the SSNOP is issued, that instruction may issue later. This is because other implementation-dependent issue rules may apply that prevent an issue in the next cycle. Processors should not introduce any unnecessary delay in issuing SSNOP instructions.
SUB
Subtract Word
SUB
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SUB rd, rs, rt MIPS32 (MIPS I) Purpose:
To subtract 32-bit integers. If overflow occurs, then trap
Description: rd ← rs – rt
The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to produce a 32-bit result. If the sub- traction results in 32-bit 2’s complement arithmetic overflow, then the destination register is not modified and an Inte- ger Overflow exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd.
Restrictions: None
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) − (GPR[rt]31||GPR[rt]31..0) if temp32 ≠ temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] ← temp31..0 endif
Exceptions:
Integer Overflow
Programming Notes:
SUBU performs the same arithmetic operation but does not trap on overflow.
SPECIAL 000000
rs
rt
rd
0 00000
SUB 100010
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SUB.fmt
[c
Floating Point Subtract
SUB.fmt
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SUB.S fd, fs, ft MIPS32 (MIPS I) SUB.D fd, fs, ft MIPS32 (MIPS I)
Purpose:
To subtract FP values
Description: fd ← fs – ft
The value in FPR ft is subtracted from the value in FPR fs. The result is calculated to infinite precision, rounded according to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in for- mat fmt. Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE- DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) –fmt ValueFPR(ft, fmt))
CPU Exceptions:
Coprocessor Unusable, Reserved Instruction
FPU Exceptions:
Inexact, Overflow, Underflow, Invalid Op, Unimplemented Op
COP1 010001
fmt
ft
fs
fd
SUB 000001
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SUBU
Subtract Unsigned Word
SUBU
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: SUBU rd, rs, rt MIPS32 (MIPS I) Purpose:
To subtract 32-bit integers
Description: rd ← rs – rt
The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs and the 32-bit arithmetic result is and
placed into GPR rd.
No integer overflow exception occurs under any circumstances.
Restrictions: None
Operation:
temp ← GPR[rs] – GPR[rt] GPR[rd]← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. It is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environ- ments that ignore overflow, such as C language arithmetic.
SPECIAL 000000
rs
rt
rd
0 00000
SUBU 100011
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SW
Store Word
SW
31
26 25 21 20 16 15
655 16
Format: SW rt, offset(base) Purpose:
To store a word to memory
0
MIPS32 (MIPS I)
SW 101011
base
rt
offset
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Description: memory[base+offset] ← rt
The least-significant 32-bit word of register rt is stored in memory at the location specified by the aligned effective
address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. Restrictions:
The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.
Operation:
vAddr ← sign_extend(offset) + GPR[base] if vAddr1..0 ≠ 02 then
SignalException(AddressError)
endif
(pAddr, CCA)← AddressTranslation (vAddr, DATA, STORE) dataword← GPR[rt]
StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA)
Exceptions:
TLB Refill, TLB Invalid, TLB Modified, Address Error
SWC1
Store Word from Floating Point
SWC1
31
26 25 21 20 16 15
655 16
Format: SWC1 ft, offset(base)
Purpose:
To store a word from an FPR to memory
0
MIPS32 (MIPS I)
SWC1 111001
base
ft
offset
Description:memory[base+offset] ← ft
The low 32-bit word from FPR ft is stored in memory at the location specified by the aligned effective address. The
16-bit signed offset is added to the contents of GPR base to form the effective address. Restrictions:
An Address Error exception occurs if EffectiveAddress1..0 ≠ 0 (not word-aligned). Operation:
vAddr ← sign_extend(offset) + GPR[base] if vAddr ≠ 03 then
1..0 SignalException(AddressError)
endif
(pAddr, CCA) ← AddressTranslation(vAddr, DATA, STORE) dataword ← ValueFPR(ft, UNINTERPRETED_WORD) StoreMemory(CCA, WORD, dataword, pAddr, vAddr, DATA)
Exceptions:
Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, TLB Modified, Address Error
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SWC2
Store Word from Coprocessor 2
SWC2
210
MIPS32TM Architecture For Programmers Volume II, Revision 0.95
31
26 25 21 20 16 15
655 16
Format: SWC2 rt, offset(base) Purpose:
To store a word from a COP2 register to memory
0
MIPS32 (MIPS I)
SWC2 111010
base
rt
offset
Description:memory[base+offset] ← ft
The low 32-bit word from COP2 (Coprocessor 2) register rt is stored in memory at the location specified by the
aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address. Restrictions:
An Address Error exception occurs if EffectiveAddress1..0 ≠ 0 (not word-aligned). Operation:
vAddr ← sign_extend(offset) + GPR[base] if vAddr ≠ 03 then
2..0 SignalException(AddressError)
endif
(pAddr, CCA) ← AddressTranslation(vAddr, DATA, STORE) dataword ← CPR[2,rt,0]
StoreMemory(CCA, WORD, dataword, pAddr, vAddr, DATA)
Exceptions:
Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, TLB Modified, Address Error
SWL
Store Word Left
SWL
31
26 25 21 20 16 15
655 16
Format: SWL rt, offset(base) Purpose:
To store the most-significant part of a word to an unaligned memory address
Description: memory[base+offset] ← rt
0
MIPS32 (MIPS I)
SWL 101010
base
rt
offset
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.
A part of W, the most-significant 1 to 4 bytes, is in the aligned word containing EffAddr. The same number of the most-significant (left) bytes from the word in GPR rt are stored into these bytes of W.
The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is located in the aligned word containing the most-significant byte at 2. First, SWL stores the most-significant 2 bytes of the low word from the source register into these 2 bytes in memory. Next, the complementary SWR stores the remainder of the unaligned word.
Figure 3-6 Unaligned Word Store Using SWL and SWR
Word at byte 2 in memory, big-endian byte order; each memory byte contains its own address most — significance — least
0
1
2
3
4
5
6
7
8
…
GPR 24
Memory: Initial contents
E
F
G
H
0
1
E
F
4
5
6
…
After executing SWL $24,2($0)
Then after SWR $24,5($0)
0
1
E
F
G
H
6
…
The bytes stored from the source register to memory depend on both the offset of the effective address within an aligned word—that is, the low 2 bits of the address (vAddr1..0)—and the current byte-ordering mode of the processor (big- or little-endian). The following figure shows the bytes stored for every combination of offset and byte ordering.
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Store Word Left (cont.)
SWL
Figure 3-7 Bytes Stored by an SWL Instruction
0
3 most
1
2
2
1
3 ←big-endian
offset (vAddr1..0)
0 ←little-endian least
Memory contents and byte offsets
Initial contents of Dest Register 64-bit register
most — significance — least 32-bit register
i
j
k
l
A
B
C
D
E
F
G
H
E
F
G
H
— significance —
Memory contents after instruction (shaded is unchanged)
Big-endian byte ordering
vAddr1..0
0 1 2 3
Little-endian byte ordering
EFGH
i
EFG
ij
EF
ijk
E
ijk
E
ij
EF
i
EFG
EFGH
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Restrictions:
None
Operation:
vAddr ← sign_extend(offset) + GPR[base]
(pAddr, CCA)← AddressTranslation (vAddr, DATA, STORE) pAddr ← pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2) If BigEndianMem = 0 then
pAddr ← pAddrPSIZE-1..2 || 02 endif
byte ← vAddr1..0 xor BigEndianCPU2
dataword← 024–8*byte || GPR[rt]31..24–8*byte StoreMemory(CCA, byte, dataword, pAddr, vAddr, DATA)
Exceptions:
TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error
SWR
Store Word Right
SWR
31
26 25 21 20 16 15
655 16
Format: SWR rt, offset(base) Purpose:
To store the least-significant part of a word to an unaligned memory address
Description: memory[base+offset] ← rt
0
MIPS32 (MIPS I)
SWR 101110
base
rt
offset
The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the least-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.
A part of W, the least-significant 1 to 4 bytes, is in the aligned word containing EffAddr. The same number of the least-significant (right) bytes from the word in GPR rt are stored into these bytes of W.
The following figure illustrates this operation using big-endian byte ordering for 32-bit and 64-bit registers. The 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. A part of W, 2 bytes, is contained in the aligned word containing the least-significant byte at 5. First, SWR stores the least-significant 2 bytes of the low word from the source register into these 2 bytes in memory. Next, the complementary SWL stores the remainder of the unaligned word.
Figure 3-8 Unaligned Word Store Using SWR and SWL
Word at byte 2 in memory, big-endian byte order, each mem byte contains its address least — significance — least
0
1
2
3
4
5
6
7
8
…
GPR 24
Memory: Initial contents
E
F
G
H
0
1
2
3
G
H
6
…
After executing SWR $24,5($0)
Then after SWL $24,2($0)
0
1
E
F
G
H
6
…
MIPS32TM Architecture For Programmers Volume II, Revision 0.95 213
Store Word Right (cont.)
SWR
The bytes stored from the source register to memory depend on both the offset of the effective address within an aligned word—that is, the low 2 bits of the address (vAddr1..0)—and the current byte-ordering mode of the processor (big- or little-endian). The following figure shows the bytes stored for every combination of offset and byte-ordering.
Figure 3-9 Bytes Stored by SWR Instruction
0
3 most
1
2
2
1
3 ← big-endian
offset (vAddr1..0)
0 ← little-endian least
Memory contents and byte offsets
Initial contents of Dest Register 64-bit register
most — significance — least 32-bit register
i
j
k
l
A
B
C
D
E
F
G
H
E
F
G
H
— significance —
Memory contents after instruction (shaded is unchanged)
Big-endian byte ordering
vAddr1..0
0 1 2 3
Little-endian byte ordering
H
jkl
GH
kl
FGH
l
EFGH
EFGH
FGH
l
GH
kl
H
jkl
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Restrictions:
None
Operation:
vAddr ← sign_extend(offset) + GPR[base]
(pAddr, CCA)← AddressTranslation (vAddr, DATA, STORE) pAddr ← pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2) If BigEndianMem = 0 then
pAddr ← pAddrPSIZE-1..2 || 02 endif
byte ← vAddr1..0 xor BigEndianCPU2
dataword← GPR[rt]31–8*byte || 08*byte
StoreMemory(CCA, WORD-byte, dataword, pAddr, vAddr, DATA)
Exceptions:
TLB Refill, TLB Invalid, TLB Modified, Bus Error, Address Error
SYNC
Synchronize Shared Memory
SYNC
31 26 25 21 20 16 15 11 10 6 5 0
6 15 5 6
Format: SYNC (stype = 0 implied) MIPS32 (MIPS II) Purpose:
To order loads and stores.
Description:
Simple Description:
• SYNCaffectsonlyuncachedandcachedcoherentloadsandstores.TheloadsandstoresthatoccurbeforetheSYNC must be completed before the loads and stores after the SYNC are allowed to start.
• Loadsarecompletedwhenthedestinationregisteriswritten.Storesarecompletedwhenthestoredvalueisvisibleto every other processor in the system.
• SYNC is required, potentially in conjunction with SSNOP, to guarantee that memory reference results are visible across operating mode changes. For example, a SYNC is required on some implementations on entry to and exit from Debug Mode to guarantee that memory affects are handled correctly.
Detailed Description:
• When the stype field has a value of zero, every synchronizable load and store that occurs in the instruction stream before the SYNC instruction must be globally performed before any synchronizable load or store that occurs after the SYNC can be performed, with respect to any other processor or coherent I/O module.
• SYNC does not guarantee the order in which instruction fetches are performed. The stype values 1-31 are reserved; they produce the same result as the value zero.
•
SPECIAL 000000
0
00 0000 0000 0000 0
stype
SYNC 001111
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Synchronize Shared Memory (cont.)
SYNC
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Terms:
Synchronizable: A load or store instruction is synchronizable if the load or store occurs to a physical location in shared memory using a virtual location with a memory access type of either uncached or cached coherent. Shared memory is memory that can be accessed by more than one processor or by a coherent I/O system module.
Performed load: A load instruction is performed when the value returned by the load has been determined. The result of a load on processor A has been determined with respect to processor or coherent I/O module B when a subsequent store to the location by B cannot affect the value returned by the load. The store by B must use the same memory access type as the load.
Performed store: A store instruction is performed when the store is observable. A store on processor A is observable with respect to processor or coherent I/O module B when a subsequent load of the location by B returns the value written by the store. The load by B must use the same memory access type as the store.
Globally performed load: A load instruction is globally performed when it is performed with respect to all processors and coherent I/O modules capable of storing to the location.
Globally performed store: A store instruction is globally performed when it is globally observable. It is globally observable when it is observable by all processors and I/O modules capable of loading from the location.
Coherent I/O module: A coherent I/O module is an Input/Output system component that performs coherent Direct Memory Access (DMA). It reads and writes memory independently as though it were a processor doing loads and stores to locations with a memory access type of cached coherent.
Synchronize Shared Memory (cont.)
SYNC
Restrictions:
The effect of SYNC on the global order of loads and stores for memory access types other than uncached and cached coherent is UNPREDICTABLE.
Operation:
SyncOperation(stype)
Exceptions:
None
Programming Notes:
A processor executing load and store instructions observes the order in which loads and stores using the same mem- ory access type occur in the instruction stream; this is known as program order.
A parallel program has multiple instruction streams that can execute simultaneously on different processors. In mul- tiprocessor (MP) systems, the order in which the effects of loads and stores are observed by other processors—the global order of the loads and store—determines the actions necessary to reliably share data in parallel programs.
When all processors observe the effects of loads and stores in program order, the system is strongly ordered. On such systems, parallel programs can reliably share data without explicit actions in the programs. For such a system, SYNC has the same effect as a NOP. Executing SYNC on such a system is not necessary, but neither is it an error.
If a multiprocessor system is not strongly ordered, the effects of load and store instructions executed by one processor may be observed out of program order by other processors. On such systems, parallel programs must take explicit actions to reliably share data. At critical points in the program, the effects of loads and stores from an instruction stream must occur in the same order for all processors. SYNC separates the loads and stores executed on the proces- sor into two groups, and the effect of all loads and stores in one group is seen by all processors before the effect of any load or store in the subsequent group. In effect, SYNC causes the system to be strongly ordered for the executing pro- cessor at the instant that the SYNC is executed.
Many MIPS-based multiprocessor systems are strongly ordered or have a mode in which they operate as strongly ordered for at least one memory access type. The MIPS architecture also permits implementation of MP systems that are not strongly ordered; SYNC enables the reliable use of shared memory on such systems. A parallel program that does not use SYNC generally does not operate on a system that is not strongly ordered. However, a program that does use SYNC works on both types of systems. (System-specific documentation describes the actions needed to reliably share data in parallel programs for that system.)
The behavior of a load or store using one memory access type is undefined if a load or store was previously made to the same physical location using a different memory access type. The presence of a SYNC between the references does not alter this behavior.
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Synchronize Shared Memory (cont.)
SYNC
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SYNC affects the order in which the effects of load and store instructions appear to all processors; it does not gener- ally affect the physical memory-system ordering or synchronization issues that arise in system programming. The effect of SYNC on implementation-specific aspects of the cached memory system, such as writeback buffers, is not defined. The effect of SYNC on reads or writes to memory caused by privileged implementation-specific instructions, such as CACHE, also is not defined.
# Processor A (writer)
# Conditions at entry:
# The value 0 has been stored in FLAG and that value is observable by B
SW R1, DATA LI R2, 1 SYNC
SW
# change shared DATA value
# Perform DATA store before performing FLAG store
# say that the shared DATA value is valid
R2, FLAG
# Processor B (reader) LI R2, 1
1: LW
BNE R2, R1, 1B# if it says that DATA is not valid, poll again NOP
SYNC # FLAG value checked before doing DATA read
LW R1, DATA # Read (valid) shared DATA value
Prefetch operations have no effect detectable by User-mode programs, so ordering the effects of prefetch operations is not meaningful.
The code fragments above shows how SYNC can be used to coordinate the use of shared data between separate writer and reader instruction streams in a multiprocessor environment. The FLAG location is used by the instruction streams to determine whether the shared data item DATA is valid. The SYNC executed by processor A forces the store of DATA to be performed globally before the store to FLAG is performed. The SYNC executed by processor B ensures that DATA is not read until after the FLAG value indicates that the shared data is valid.
R1, FLAG # Get FLAG
SYSCALL
System Call
SYSCALL
31
26 25 6 5 0
6 20 6
Format: SYSCALL MIPS32 (MIPS I) Purpose:
To cause a System Call exception
Description:
A system call exception occurs, immediately and unconditionally transferring control to the exception handler.
The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
Restrictions:
None
Operation:
SignalException(SystemCall)
Exceptions:
System Call
SPECIAL 000000
code
SYSCALL 001100
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TEQ
Trap if Equal
TEQ
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TEQ rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs = rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is equal to GPR rt, then take a Trap excep-
tion.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if GPR[rs] = GPR[rt] then
SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TEQ 110100
220
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TEQI
Trap if Equal Immediate
TEQI
31
26 25 21 20 16 15
655 16
Format: TEQI rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TEQI 01100
immediate
Description: if rs = immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is equal to immediate,
then take a Trap exception.
Restrictions:
None
Operation:
if GPR[rs] = sign_extend(immediate) then
SignalException(Trap)
endif
Exceptions:
Trap
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TGE
Trap if Greater or Equal
TGE
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TGE rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs ≥ rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is greater than or equal to GPR rt, then take
a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if GPR[rs] ≥ GPR[rt] then SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TGE 110000
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TGEI
Trap if Greater or Equal Immediate
TGEI
31
26 25 21 20 16 15
655 16
Format: TGEI rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TGEI 01000
immediate
Description: if rs ≥ immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is greater than or equal
to immediate, then take a Trap exception. Restrictions:
None
Operation:
if GPR[rs] ≥ sign_extend(immediate) then SignalException(Trap)
endif
Exceptions:
Trap
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TGEIU
Trap if Greater or Equal Immediate Unsigned
TGEIU
31
26 25 21 20 16 15
655 16
Format: TGEIU rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TGEIU 01001
immediate
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Description: if rs ≥ immediate then Trap
Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned integers; if GPR rs is greater
than or equal to immediate, then take a Trap exception.
Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range.
Restrictions:
None
Operation:
if (0 || GPR[rs]) ≥ (0 || sign_extend(immediate)) then SignalException(Trap)
endif
Exceptions:
Trap
TGEU
Trap if Greater or Equal Unsigned
TGEU
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TGEU rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs ≥ rt then Trap
Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is greater than or equal to GPR rt, then
take a Trap exception.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if (0 || GPR[rs]) ≥ (0 || GPR[rt]) then SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TGEU 110001
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TLBP
31
26 25 24 6 5 0
COP0 010000
CO 1
0
000 0000 0000 0000 0000
TLBP 001000
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Probe TLB for Matching Entry TLBP
61 19 6
Format: TLBP Purpose:
To find a matching entry in the TLB.
Description:
MIPS32
The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi reg- ister. If no TLB entry matches, the high-order bit of the Index register is set.
Restrictions:
Operation:
Index ← 1 || UNPREDICTABLE31 for i in 0…TLBEntries-1
if ((TLB[i]VPN2 and not (TLB[i]Mask)) = (EntryHiVPN2 and not (TLB[i]Mask))) and
((TLB[i]G = 1) or (TLB[i]ASID = EntryHiASID))then
Index ← i endif
endfor
Exceptions:
Coprocessor Unusable
TLBR
Read Indexed TLB Entry TLBR
31
26 25 24 6 5 0
61 19 6
Format: TLBR MIPS32 Purpose:
To read an entry from the TLB.
Description:
The EntryHi, EntryLo0, EntryLo1, and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register. Note that the value written to the EntryHi, EntryLo0, and EntryLo1 registers may be different from that originally written to the TLB via these registers in that:
• ThevaluereturnedintheVPN2fieldoftheEntryHiregistermayhavethosebitssettozerocorrespondingtothe one bits in the Mask field of the TLB entry (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.
• The value returned in the PFN field of the EntryLo0 and EntryLo1 registers may havethose bits set to zero corresponding to the one bits in the Mask field of the TLB entry (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.
• The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written.
Restrictions:
The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB
entries in the processor.
COP0 010000
CO 1
0
000 0000 0000 0000 0000
TLBR 000001
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Read Indexed TLB Entry TLBR
Operation:
i ← Index
if i > (TLBEntries – 1) then
UNDEFINED
endif
PageMaskMask ← TLB[i]Mask EntryHi ←
(TLB[i]VPN2 and not TLB[i]Mask) || # Masking implementation dependent
05 || TLB[i]ASID EntryLo1 ← 02 ||
(TLB[i]PFN1 and not TLB[i]Mask) || # Masking mplementation dependent
TLB[i]C1 || TLB[i]D1 || TLB[i]V1 || TLB[i]G EntryLo0 ← 02 ||
Exceptions:
Coprocessor Unusable
(TLB[i]PFN0 and not TLB[i]Mask) || # Masking mplementation dependent TLB[i]C0 || TLB[i]D0 || TLB[i]V0 || TLB[i]G
TLBWI
31
26 25 24 6 5
61 19 6
Format: TLBWI Purpose:
To write a TLB entry indexed by the Index register. Description:
0
MIPS32
Write Indexed TLB Entry
TLBWI
COP0 010000
CO 1
0
000 0000 0000 0000 0000
TLBWI 000010
The TLB entry pointed to by the Index register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:
• The value written to the VPN2 field of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of the PageMask register (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
• ThevaluewrittentothePFN0andPFN1fieldsoftheTLBentrymayhavethosebitssettozerocorrespondingto the one bits in the Mask field of PageMask register (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
• The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
Restrictions:
The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB
entries in the processor.
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Write Indexed TLB Entry
TLBWI
Operation:
i ← Index
TLB[i]Mask ← PageMaskMask
TLB[i]VPN2 ← EntryHiVPN2 and not PageMaskMask # Implementation dependent TLB[i]ASID ← EntryHiASID
TLB[i]G ← EntryLo1G and EntryLo0G
TLB[i]PFN1 ← EntryLo1PFN and not PageMaskMask # Implementation dependent TLB[i]C1 ← EntryLo1C
TLB[i]D1 ← EntryLo1D
TLB[i]V1 ← EntryLo1V
TLB[i]PFN0 ← EntryLo0PFN and not PageMaskMask # Implementation dependent TLB[i]C0 ← EntryLo0C
TLB[i]D0 ← EntryLo0D
TLB[i]V0 ← EntryLo0V
Exceptions:
Coprocessor Unusable
TLBWR
Write Random TLB Entry
TLBWR
31
26 25 24 6 5
61 19 6
Format: TLBWR Purpose:
To write a TLB entry indexed by the Random register. Description:
0
MIPS32
COP0 010000
CO 1
0
000 0000 0000 0000 0000
TLBWR 000110
The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:
• The value written to the VPN2 field of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of the PageMask register (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
• ThevaluewrittentothePFN0andPFN1fieldsoftheTLBentrymayhavethosebitssettozerocorrespondingto the one bits in the Mask field of PageMask register (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a TLB write.
• The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written.
Restrictions:
The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB
entries in the processor.
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Write Random TLB Entry
TLBWR
Operation:
i ← Random
TLB[i]Mask ← PageMaskMask
TLB[i]VPN2 ← EntryHiVPN2 and not PageMaskMask # Implementation dependent TLB[i]ASID ← EntryHiASID
TLB[i]G ← EntryLo1G and EntryLo0G
TLB[i]PFN1 ← EntryLo1PFN and not PageMaskMask # Implementation dependent TLB[i]C1 ← EntryLo1C
TLB[i]D1 ← EntryLo1D
TLB[i]V1 ← EntryLo1V
TLB[i]PFN0 ← EntryLo0PFN and not PageMaskMask # Implementation dependent TLB[i]C0 ← EntryLo0C
TLB[i]D0 ← EntryLo0D
TLB[i]V0 ← EntryLo0V
Exceptions:
Coprocessor Unusable
TLT
Trap if Less Than
TLT
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TLT rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs < rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is less than GPR rt, then take a Trap excep-
tion.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if GPR[rs] < GPR[rt] then
SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TLT 110010
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TLTI
Trap if Less Than Immediate
TLTI
31
26 25 21 20 16 15
655 16
Format: TLTI rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TLTI 01010
immediate
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Description: if rs < immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is less than immediate,
then take a Trap exception.
Restrictions:
None
Operation:
if GPR[rs] < sign_extend(immediate) then
SignalException(Trap)
endif
Exceptions:
Trap
TLTIU
Trap if Less Than Immediate Unsigned
TLTIU
31
26 25 21 20 16 15
655 16
Format: TLTIU rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TLTIU 01011
immediate
Description: if rs < immediate then Trap
Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned integers; if GPR rs is less than
immediate, then take a Trap exception.
Because the 16-bit immediate is sign-extended before comparison, the instruction can represent the smallest or largest unsigned numbers. The representable values are at the minimum [0, 32767] or maximum [max_unsigned-32767, max_unsigned] end of the unsigned range.
Restrictions:
None
Operation:
if (0 || GPR[rs]) < (0 || sign_extend(immediate)) then
SignalException(Trap)
endif
Exceptions:
Trap
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TLTU
Trap if Less Than Unsigned
TLTU
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TLTU rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs < rt then Trap
Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is less than GPR rt, then take a Trap
exception.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if (0 || GPR[rs]) < (0 || GPR[rt]) then
SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TLTU 110011
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TNE
Trap if Not Equal
TNE
31
26 25 21 20 16 15 6 5 0
6 5 5 10 6
Format: TNE rs, rt MIPS32 (MIPS II) Purpose:
To compare GPRs and do a conditional trap
Description: if rs ≠ rt then Trap
Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is not equal to GPR rt, then take a Trap
exception.
The contents of the code field are ignored by hardware and may be used to encode information for system software. To retrieve the information, system software must load the instruction word from memory.
Restrictions:
None
Operation:
if GPR[rs] ≠ GPR[rt] then SignalException(Trap)
endif
Exceptions:
Trap
SPECIAL 000000
rs
rt
code
TNE 110110
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TNEI
Trap if Not Equal
TNEI
31
26 25 21 20 16 15
655 16
Format: TNEI rs, immediate Purpose:
To compare a GPR to a constant and do a conditional trap
0
MIPS32 (MIPS II)
REGIMM 000001
rs
TNEI 01110
immediate
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Description: if rs ≠ immediate then Trap
Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is not equal to imme-
diate, then take a Trap exception. Restrictions:
None
Operation:
if GPR[rs] ≠ sign_extend(immediate) then SignalException(Trap)
endif
Exceptions:
Trap
TRUNC.W.fmt
Floating Point Truncate to Word Fixed Point
TRUNC.W.fmt
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: TRUNC.W.S fd, fs MIPS32 (MIPS II) TRUNC.W.D fd, fs MIPS32 (MIPS II)
Purpose:
To convert an FP value to 32-bit fixed point, rounding toward zero
Description: fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in 32-bit word fixed point format using rounding toward
zero (rounding mode 1). The result is placed in FPR fd.
When the source value is Infinity, NaN, or rounds to an integer outside the range -231 to 231-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. In this case the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written to fd and an Invalid Operation
exception is taken immediately. Otherwise, the default result, 231–1, is written to fd. Restrictions:
The fields fs and fd must specify valid FPRs; fs for type fmt and fd for word fixed point; if they are not valid, the result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand FPR becomes UNPREDICTABLE.
Operation:
StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W))
COP1 010001
fmt
0 00000
fs
fd
TRUNC.W 001101
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Floating Point Truncate to Word Fixed Point (cont.)
TRUNC.W.fmt
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Inexact, Invalid Operation, Overflow, Unimplemented Operation
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WAIT
31
26 25 24 6 5 0
61 19 6
Format: WAIT MIPS32 Purpose:
Wait for Event
Description:
The WAIT instruction performs an implementation-dependent operation, usually involving a lower power mode. Software may use bits 24:6 of the instruction to communicate additional information to the processor, and the proces- sor may use this information as control for the lower power mode. A value of zero for bits 24:6 is the default and must be valid in all implementations.
The WAIT instruction is typically implemented by stalling the pipeline at the completion of the instruction and enter- ing a lower power mode. The pipeline is restarted when an external event, such as an interrupt or external request occurs, and execution continues with the instruction following the WAIT instruction. It is implementation-dependent whether the pipeline restarts when a non-enabled interrupt is requested. In this case, software must poll for the cause of the restart. If the pipeline restarts as the result of an enabled interrupt, that interrupt is taken between the WAIT instruction and the following instruction (EPC for the interrupt points at the instruction following the WAIT instruc- tion).
The assertion of any reset or NMI must restart the pipelihne and the corresponding exception myust be taken.
Restrictions:
The operation of the processor is UNDEFINED if a WAIT instruction is placed in the delay slot of a branch or a
jump.
Enter Standby Mode WAIT
COP0 010000
CO 1
Implementation-Dependent Code
WAIT 100000
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Enter Standby Mode (cont.) WAIT
Operation:
Enter implementation dependent lower power mode
Exceptions:
Coprocessor Unusable Exception
XOR
Exclusive OR
XOR
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: XOR rd, rs, rt MIPS32 (MIPS I) Purpose:
To do a bitwise logical Exclusive OR
Description: rd ← rs XOR rt
Combine the contents of GPR rs and GPR rt in a bitwise logical Exclusive OR operation and place the result into
GPR rd. Restrictions:
None
Operation:
GPR[rd] ← GPR[rs] xor GPR[rt] Exceptions:
None
SPECIAL 000000
rs
rt
rd
0 00000
XOR 100110
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XORI
Exclusive OR Immediate
XORI
31
26 25 21 20 16 15
655 16
Format: XORI rt, rs, immediate
Purpose:
To do a bitwise logical Exclusive OR with a constant
0
MIPS32 (MIPS I)
XORI 001110
rs
rt
immediate
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Description: rt ← rs XOR immediate
Combine the contents of GPR rs and the 16-bit zero-extended immediate in a bitwise logical Exclusive OR operation
and place the result into GPR rt. Restrictions:
None
Operation:
GPR[rt] ← GPR[rs] xor zero_extend(immediate)
Exceptions:
None
Appendix A
Revision History
Revision
0.90 0.91
0.92
0.95
Date
November 1, 2000 November 15, 2000
December 15, 2000
March 12, 2001
Description
Internal review copy of reorganized and updated architecture documentation. External review copy of reorganized and updated architecture documentation. Changes in this revision:
• Correct sign in description of MSUBU.
• Update JR and JALR instructions to reflect the changes required by MIPS16.
Update for second external review release.
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