Spring 2019-2020 CSSE 232
Name:
(25 points) You are the lead designer for a single-cycle implementation of a MIPS-like processor. Your team is considering adding a new I-type instruction (¡®store quarter¡¯ – stq), which divides the value stored in a register operand by 4 and stores the result at a base-offset calculated address. Below is an example of stq being used.
la $t1, D #The location of where data should be stored
addi $t2, $0, 16
stq $t2, 8($t1) #this calculates 16/4 and puts the result in memory
You can assume this uses integer division, rather than floating point division.
1. (10 points) Write out single-cycle RTL that implements this new instruction. Make sure it is clear how your RTL implements the behavior described above. List any assumptions you make.
2. (10 points) Modify the single-cycle datapath on the following page as necessary to sup- port the new instruction. Be sure these modifications are consistent with the RTL you wrote for problem 1 and add as little to the datapath as possible. List any additional control signals added and their purpose. Be sure it is clear how your changes work.
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Spring 2019-2020 CSSE 232
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FIGURE4.15
The datapath
igure 4.12 with all nece
multiplex and all control line identifi The
lines
clock
in olo The the anch
blo has been determin whether it
The doe not quire ite inc it
itt th the incremented or the anch target
ntrol once the end
9El
nc.
hts ese
PC
Read address
Instruction [25:21] Instruction [20:16]
Read register 1
Read data 1
MemWrite
4
Add ALU result
1
Instruction [31:0]
0
Write Read
ALU ALU result
Read Address data 1
Instruction memory
1
register Write
M Mu ux x
Add
M u x
M Instruction [15:11] ux
data 2
0
Instruction [15:0]
16
Sign- 32 extend
RegDst
Write Data data memory
RegWrite
Shift left 2
Read register 2
ALUSrc
Zero
MemtoReg
data Registers
1
0
Instruction [5:0]
ALUOp
ALU control
MemRead
PCSrc
0
ess Cop
Spring 2019-2020 CSSE 232
3. (5 points) Below list the state of all control signals (in binary) in your design when the new instruction is being executed. Be sure these modifications are consistent with the RTL in Problem 1 and the datapath in Problem 2.
Note: ALUOp = 00 generates an add, ALUOp = 01 generates a subtract, and ALUOp = 10 generates an operation based on the function bits.
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