V1: Support for fixed-latency memory stalls
Submit Assignment
• Due Monday by 11:59pm
• Points 10
• Submitting a file upload
• File Types tgz
• Available after Apr 13 at 11:59pm
The provided V1 tarball (see: modules page) contains a presumed-working (for the same subset of MIPS instructions as V0) FDEMW pipelined processor with:
• Always-Predict-Not-Taken branch prediction
• Hazard detection and branch resolution in D
• Full forwarding
• Non-coherent IMEM and DMEM memories (stores to DMEM will not appear in IMEM)
The IMEM and DMEM memory modules currently always supply/accept the requested operations. However, they also each provide a READY signal that is false the first time the 4-byte block containing the specified address is accessed and true for any subsequent access to that same block.
Your task: Change the stall / NOP insertion logic to accommodate the existence of potential 1-cycle “stalls” in one or both of the IMEM/DMEM.
Goal: This project serves as direct preparation for the cache integration in the final project, where the I$ and D$ will have misses. While the mechanism and timing for determining hits/misses/evictions for cache interactions will be different, the pipeline interface for the final project will be nearly identical to the one implemented here.
What to submit:
Your Vivado project directory, as a gzipped tarball.
P2: MIPS benchmark generation for final project
Submit Assignment
• Due Monday by 11:59pm
• Points 10
• Submitting a file upload
• File Types asm
• Available after Apr 13 at 11:59pm
As part of your preparation for the final project, you will be constructing your own version of one of the two benchmarks that will run on your final project implementation (post-due-date correct standardized versions will be released for both benchmarks).
Writing these benchmarks yourself in MIPS will help you understand their behavior on the final project processor and ease debugging.
Benchmark 1 (10 points):
Naive matrix multiplication.
You will write a function, NMM, that takes 3 pointers A, B, C and 1 size parameter N and performs naive (i.e. O(N3) ) matrix multiplication on the NxN matrices, stored in row-major order, specified by starting locations A and B ,and stores the result into the location specified by C. All matrix elements will be 32-bit unsigned integers.
Direct C implementation operating on pointers to row-major projected 2D arrays (for clarity)
NMM(unsigned int * A, unsigned int *B, unsigned int * C, unsigned int N){
unsigned int i, j, k;
for (i=0; i