1) Assemble by hand the following subroutine for the CV-8052 processor. Use the opcodes provided in the appendices at the end of this exam. (10 marks)
Address
Opcode/Operands
Instruction
dseg at 30H
bcd: ds 5
x: ds 4
cseg at 1000H
h2b: clr a
mov bcd+0, a
mov bcd+1, a
mov bcd+2, a
mov bcd+3, a
mov bcd+4, a
mov r2, #32
h2b_L0: mov r1, #4
mov r0, #(x+0)
h2b_L1: mov a, @r0
rlc a
mov @r0, a
inc r0
djnz r1, h2b_L1
mov r1, #5
mov r0, #(bcd+0)
h2b_L2: mov a, @r0
addc a, @r0
da a
mov @r0, a
inc r0
djnz r1, h2b_L2
djnz r2, h2b_L0
ret
2
2) Disassemble the following sequence of machine code for the 8051 microcontroller. All the numbers are in hexadecimal. Use the tables of opcodes provided in the appendices at the end of this exam. (10 marks)
C0 D0 C0 E0 C0 00 E9 29 24 32 F8 D8 FE D0 00 D0 E0 D0 D0 22
3
3) Write a subroutine to generate the signal shown below at pin P0.0 of a CV-8052 processor running at 33.333333 MHz. The CV-8052 takes one clock period per machine cycle. Assume the pin is configured as an output, and that the signal is already set to logic zero before the subroutine is called. Use the cycles per instruction in the tables provided at the end of this exam. (10 marks)
90 ns 90 ns 60 ns 120 ns 90 ns
4
4) Write an assembly subroutine for the 8051 microcontroller to perform the operation Z=X−Y, where Z, X, and Y are packed BCD numbers defined as:
DSEG at 040H
X: DS 3 ; six BCD digits for input X
Y: DS 3 ; six BCD digits for input Y
XSEG at 4000H
Z: DS 3 ; six BCD digits for result Z
Assume the least significant BCD digits are stored at the lowest memory location for all the variables. Tip: X−Y =X + nine_complement(Y) + 1. (15 marks)
5
5) A little league baseball scoreboard includes the circuit shown in the figure below to count the number of pitches the current pitcher has thrown. Write an 8051 assembly subroutine to increment the number of pitches stored in register B (in BCD) and display the result using the common-anode 7-segment displays wired as shown in the circuit. (10 marks)
Q5
P0
8051
P1.0 P1.1
8
74HC374
74HC374
1k each Q6
1k each Q6
5V
MSD 5V
LSD
Q4
Q3
D0-D7 E*
Q2
Q1
Q0
Q5
Q4
Q3
D0-D7 E*
Q2
Q1
Q0
Dec7Seg:
DB 40H, 79H, 24H, 30H, 19H, 12H, 02H, 78H, 00H, 10H
6
6) The two look-up tables below can be used to quickly convert a register to its hexadecimal ASCII representation. Write an assembly subroutine for the 8051 microcontroller to convert the value passed in register B to its hexadecimal ASCII representation and store the two ASCII values into registers R6 and R7 where R6 is the least significant digit. If variable UPPER is set to ‘1’ use upper case letters. Otherwise use lower case letters. (10 marks)
BSEG
UPPER: DBIT 1
CSEG
TO_HEX_UPPER: DB ’0123456789ABCDEF’
TO_HEX_LOWER: DB ’0123456789abcdef’
7
7) The 8051 assembly subroutine below configures timer/counter 0 as a 16-bit counter. Write an Interrupt Service Routine for counter 0 that:
a) Increments a 16-bit variable defined in the ISEG called ‘ovf_count’. Assume the variable is located in memory above address 0x7F.
b) Preserves the value of all the used registers. c) Returns properly.
Note: the vector address for counter 0 interrupt is 000BH. (15 marks)
Init_counter_0:
clr EA ; Disable interrupts
clr TR0 ; Stop counter 0
mov TMOD, #05H ; Configure counter 0 in mode 1
clr TF0 ; Clear overflow flag
mov TH0, #0
mov TL0, #0
clr a
mov R0, #ovf_count
mov @R0, a
inc R0
mov @R0, a
setb TR0
setb ET0
setb EA
ret
; Clear overflow counter low
; Clear overflow counter high
; Start counter 0
; Enable counter 0 overflow interrupt
; Enable global interrupts
8
8) The circuit in the figure below can be used to verify that a 74HC86 integrated circuit (IC) operates correctly. The 74HC86 IC consists of four 2-input XOR gates. Write a subroutine for the CV-8052 processor that tests the IC after push button PB1 is pressed and then released. Additionally, the subroutine should: configure the input and output pins, apply power to the IC, test all possible input/output combinations and either turn the green LED on if the IC passes all the tests or the red LED on if the IC fails any test. The subroutine should set the power pin as well as all of the IC inputs to zero before returning so that the IC can be removed safely from the circuit after the tests are completed. TIP: you can test all four gates at once! (20 marks)
P0.0
1 14
3.3V
RED 270
GREEN 270 1k
PB1
VCC
P2.7
P0.1
2
13
P0.7
P2.6
P2.0
3
12
P0.6
P0.2
4
11
P2.3
P2.5
P0.3
5
10
P2.1
6
P0.5
9
P0.4
7
GND
8
P2.2
P2.4
74HC86
9
Appendix 1: CV-8052 Instructions Sorted by Opcode Number
Opcode 00000000 aaa00001 00000010 00000011 00000100 00000101 0000011i 00001rrr 00010000 aaa10001 00010010 00010011 00010100 00010101 0001011i 00011rrr 00100000 00100010 00100011 00100100 00100101 0010011i 00101rrr 00110000 00110010 00110011 00110100 00110101 0011011i 00111rrr 01000000 01000010 01000011 01000100 01000101 0100011i 01001rrr 01010000 01010010 01010011 01010100 01010101 0101011i 01011rrr 01100000 01100010 01100011 01100100 01100101 0110011i 01101rrr 01110000 01110010 01110011 01110100 01110101
Hex CB 0x00 1 1 3 2 0x02 3 3 0x03 1 1 0x04 1 1 0x05 2 2 0x06-0x07 1 1 0x08-0x0F 1 1 0x10 3/4 3 3 2 0x12 3 3 0x13 1 1 0x14 1 1 0x15 2 2 0x16-0x17 1 1 0x18-0x1F 1 1 0x20 3/4 3 0x22 3 1 0x23 1 1 0x24 2 2 0x25 2 2 0x26-0x27 1 1 0x28-0x2F 1 1 0x30 3/4 3 0x32 3 1 0x33 1 1 0x34 2 2 0x35 2 2 0x36-0x37 1 1 0x38-0x3F 1 1 0x40 2/3 2 0x42 2 2 0x43 3 3 0x44 2 2 0x45 2 2 0x46-0x47 1 1 0x48-0x4F 1 1 0x50 2/3 2 0x52 2 2 0x53 3 3 0x54 2 2 0x55 2 2 0x56-0x57 1 1 0x58-0x5F 1 1 0x60 2/3 2 0x62 2 2 0x63 3 3 0x64 2 2 0x65 2 2 0x66-0x67 1 1 0x68-0x6F 1 1 0x70 2/3 2 0x72 2 2 0x73 2 1 0x74 2 2 0x75 3 3
Mnemonic
NOP
AJMP paged_addr LJMP abs_addr RRA
INC A
INC data
INC @Ri
INC Rn
JBC bit,rel ACALL paged_addr LCALL abs_addr RRC A
DEC A
DEC data
DEC @Ri
DEC Rn
JB bit,rel
RET
RLA
ADD A,#val
ADD A,data
ADD A,@Ri
ADD A,Rn
JNB bit,rel RETI
RLC A
ADDC A,#val ADDC A,data ADDC A,@Ri
ADDC A,Rn
JC rel
ORL data,A
ORL data,#val ORL A,#val
ORL A,data
ORL A,@Ri
ORL A,Rn
JNC rel
ANL data,A
ANL data,#val ANL A,#val
ANL A,data
ANL A,@Ri
ANL A,Rn
JZ rel
XRL data,A
XRL data,#val XRL A,#val
XRL A,data
XRL A,@Ri
XRL A,Rn
JNZ rel
ORL C,bit
JMP @A+DPTR
MOV A,#val
MOV data,#val
Opcode 0111011i 01111rrr 10000000 10000010 10000011 10000100 10000101 1000011i 10001rrr 10010000 10010010 10010011 10010100 10010101 1001011i 10011rrr 10100000 10100010 10100011 10100100 1010011i 10101rrr 10110000 10110010 10110011 10110100 10110101 1011011i 10111rrr 11000000 11000010 11000011 11000100 11000101 1100011i 11001rrr 11010000 11010010 11010011 11010100 11010101 1101011i 11011rrr 11100000 1110001i 11100100 11100101 1110011i 11101rrr 11110000 1111001i 11110100 11110101 1111011i 11111rrr
HexCB Mnemonic 0x76-0x77 2 2 MOV @Ri,#val 0x78-0x7F 2 2 MOV Rn,#val 0x80 3 2 SJMP rel
0x82 2 2 ANL C,bit
0x83 4 1 MOVC A,@A+PC
0x84 10 1 DIV AB
0x85 3 3 MOV data,data
0x86-0x87 2 2 MOV data,@Ri 0x88-0x8F 2 2 MOV data,Rn 0x90 3 3 MOV DPTR,#val
0x92 2 2 MOV bit,C
0x93 4 1 MOVC A,@A+DPTR
0x94 2 2 SUBB A,#val
0x95 2 2 SUBB A,data
0x96-0x97 1 1 SUBB A,@Ri 0x98-0x9F 1 1 SUBB A,Rn 0xA0 2 2 ORL C,/bit
0xA2 2 2 MOV C,bit
0xA3 1 1 INC DPTR
0xA4 1 1 MUL AB
0xA6-0xA7 3 2 MOV @Ri,data 0xA8-0xAF 3 2 MOV Rn,data 0xB0 2 2 ANL C,/bit
0xB2 2 2 CPL bit
0xB3 1 1 CPL C
0xB4 3/4 3 CJNE A,#val,rel
0xB5 3/4 3 CJNE A,data,rel
0xB6-0xB7 3/4 3 CJNE @Ri,#val,rel 0xB8-0xBF 3/4 3 CJNE Rn,#val,rel 0xC0 3 2 PUSH data
0xC2 2 2 CLR bit
0xC3 1 1 CLR C
0xC4 1 1 SWAP A
0xC5 2 2 XCH A,data
0xC6-0xC7 1 1 XCH A,@Ri 0xC8-0xCF 1 1 XCH A,Rn 0xD0 3 2 POP data
0xD2 2 2 SETB bit
0xD3 1 1 SETB C
0xD4 1 1 DAA
0xD5 3/4 3 DJNZ data,rel
0xD6-0xD7 1 1 XCHD A,@Ri 0xD8-0xDF 2/3 2 DJNZ Rn,rel 0xE0 2 1 MOVX A,@DPTR 0xE2-0xE3 2 1 MOVX A,@Ri
0xE4 1 1 CLR A
0xE5 2 2 MOV A,data
0xE6-0xE7 1 1 MOV A,@Ri 0xE8-0xEF 1 1 MOV A,Rn 0xF0 1 1 MOVX @DPTR,A 0xF2-0xF3 1 1 MOVX @Ri,A
0xF4 1 1 CPL A
0xF5 2 2 MOV data,A
0xF6-0xF7 1 1 MOV @Ri,A 0xF8-0xFF 1 1 MOV Rn,A
10
Appendix 2: CV-8052 Instructions Sorted by Name
Opcode aaa10001 00100100 0010011i 00100101 00101rrr 00110100 0011011i 00110101 00111rrr aaa00001 01010100 0101011i 01010101 01011rrr 10110000 10000010 01010011 01010010 1011011i 10110100 10110101 10111rrr 11100100 11000010 11000011 11110100 10110010 10110011 11010100 0001011i 00010100 00010101 00011rrr 10000100 11010101 11011rrr 0000011i 00000100 00000101 10100011 00001rrr 00100000 00010000 01000000 01110011 00110000 01010000 01110000 01100000 00010010 00000010 0111011i 1111011i 1010011i 01110100 1110011i
HexCB Mnemonic
3 2 ACALL paged_addr
0x24 2 2 ADD A,#val 0x26-0x27 1 1 ADD A,@Ri 0x25 2 2 ADD A,data 0x28-0x2F 1 1 ADD A,Rn 0x34 2 2 ADDC A,#val 0x36-0x37 1 1 ADDC A,@Ri 0x35 2 2 ADDC A,data 0x38-0x3F 1 1 ADDC A,Rn
3 2 AJMP paged_addr 0x54 2 2 ANL A,#val
0x56-0x57 1 1 ANL A,@Ri
0x55 2 2 ANL A,data 0x58-0x5F 1 1 ANL A,Rn
0xB0 2 2 ANL C,/bit
0x82 2 2 ANL C,bit
0x53 3 3 ANL data,#val 0x52 2 2 ANL data,A 0xB6-0xB7 3/4 3 CJNE @Ri,#val,rel 0xB4 3/4 3 CJNE A,#val,rel 0xB5 3/4 3 CJNE A,data,rel 0xB8-0xBF 3/4 3 CJNE Rn,#val,rel 0xE4 1 1 CLR A
0xC2 2 2 CLR bit
0xC3 1 1 CLR C
0xF4 1 1 CPL A
0xB2 2 2 CPL bit
0xB3 1 1 CPL C
0xD4 1 1 DAA 0x16-0x17 1 1 DEC @Ri
0x14 1 1 DEC A
0x15 2 2 DEC data 0x18-0x1F 1 1 DEC Rn
0x84 10 1 DIV AB
0xD5 3/4 3 DJNZ data,rel 0xD8-0xDF 2/3 2 DJNZ Rn,rel 0x06-0x07 1 1 INC @Ri
0x04 1 1 INC A
0x05 2 2 INC data
0xA3 1 1 INC DPTR 0x08-0x0F 1 1 INC Rn
0x20 3/4 3 JB bit,rel 0x10 3/4 3 JBC bit,rel 0x40 2/3 2 JC rel
0x73 2 1 JMP @A+DPTR 0x30 3/4 3 JNB bit,rel 0x50 2/3 2 JNC rel
0x70 2/3 2 JNZ rel
0x60 2/3 2 JZ rel
0x12 3 3 LCALL abs_addr 0x02 3 3 LJMP abs_addr 0x76-0x77 2 2 MOV @Ri,#val 0xF6-0xF7 1 1 MOV @Ri,A 0xA6-0xA7 3 2 MOV @Ri,data 0x74 2 2 MOV A,#val 0xE6-0xE7 1 1 MOV A,@Ri
Opcode 11100101 11101rrr 10010010 10100010 01110101 1000011i 11110101 10000101 10001rrr 10010000 01111rrr 11111rrr 10101rrr 10010011 10000011 11110000 1111001i 11100000 1110001i 10100100 00000000 01000100 0100011i 01000101 01001rrr 10100000 01110010 01000011 01000010 11010000 11000000 00100010 00110010 00100011 00110011 00000011 00010011 11010010 11010011 10000000 10010100 1001011i 10010101 10011rrr 11000100 1100011i 11000101 11001rrr 1101011i 01100100 0110011i 01100101 01101rrr 01100011 01100010
HexCB Mnemonic 0xE5 2 2 MOV A,data 0xE8-0xEF 1 1 MOV A,Rn
0x92 2 2 MOV bit,C 0xA2 2 2 MOV C,bit 0x75 3 3 MOV data,#val 0x86-0x87 2 2 MOV data,@Ri 0xF5 2 2 MOV data,A 0x85 3 3 MOV data,data 0x88-0x8F 2 2 MOV data,Rn 0x90 3 3 MOV DPTR,#val 0x78-0x7F 2 2 MOV Rn,#val 0xF8-0xFF 1 1 MOV Rn,A 0xA8-0xAF 3 2 MOV Rn,data 0x93 4 1 MOVC A,@A+DPTR 0x83 4 1 MOVC A,@A+PC 0xF0 1 1 MOVX @DPTR,A 0xF2-0xF3 1 1 MOVX @Ri,A 0xE0 2 1 MOVX A,@DPTR 0xE2-0xE3 2 1 MOVX A,@Ri 0xA4 1 1 MUL AB
0x00 1 1 NOP
0x44 2 2 ORL A,#val 0x46-0x47 1 1 ORL A,@Ri 0x45 2 2 ORL A,data 0x48-0x4F 1 1 ORL A,Rn 0xA0 2 2 ORL C,/bit 0x72 2 2 ORL C,bit 0x43 3 3 ORL data,#val 0x42 2 2 ORL data,A 0xD0 3 2 POP data 0xC0 3 2 PUSH data 0x22 3 1 RET
0x32 3 1 RETI
0x23 1 1 RLA
0x33 1 1 RLC A
0x03 1 1 RRA
0x13 1 1 RRC A
0xD2 2 2 SETB bit 0xD3 1 1 SETB C
0x80 3 2 SJMP rel 0x94 2 2 SUBB A,#val 0x96-0x97 1 1 SUBB A,@Ri 0x95 2 2 SUBB A,data 0x98-0x9F 1 1 SUBB A,Rn 0xC4 1 1 SWAP A 0xC6-0xC7 1 1 XCH A,@Ri 0xC5 2 2 XCH A,data 0xC8-0xCF 1 1 XCH A,Rn 0xD6-0xD7 1 1 XCHD A,@Ri 0x64 2 2 XRL A,#val 0x66-0x67 1 1 XRL A,@Ri 0x65 2 2 XRL A,data 0x68-0x6F 1 1 XRL A,Rn 0x63 3 3 XRL data,#val 0x62 2 2 XRL data,A
11