Data Sheet
ADuC845/ADuC847/ADuC848
FEATURES
High resolution Σ-Δ ADCs
2 independent 24-bit ADCs on the ADuC845 Single 24-bit ADC on the ADuC847 and
single 16-bit ADC on the ADuC848
Up to 10 ADC input channels on all devices
24-bit no missing codes
22-bit rms (19.5 bit p-p) effective resolution
Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled
Memory
62-kbyte on-chip Flash/EE program memory 4-kbyte on-chip Flash/EE data memory
Flash/EE, 100-year retention, 100 kcycle endurance 3 levels of Flash/EE program memory security In-circuit serial download (no external hardware) High speed user download (5 sec)
2304 bytes on-chip data RAM
8051-based core
8051-compatible instruction set
High performance single-cycle core
32 kHz external crystal
On-chip programmable PLL (12.58 MHz max) 3 × 16-bit timer/counter
24 programmable I/O lines, plus 8 analog or
digital input lines
11 interrupt sources, two priority levels
Dual data pointer, extended 11-bit stack pointer
On-chip peripherals
Internal power-on reset circuit
12-bit voltage output DAC
Dual 16-bit Σ-Δ DACs
On-chip temperature sensor (ADuC845 only)
Dual excitation current sources (200 μA)
Time interval counter (wake-up/RTC timer)
UART, SPI®, and I2C® serial I/O
High speed dedicated baud rate generator (incl. 115,200) Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.8 mA max at 3.6 V (core CLK = 1.57 MHz) Power-down: 20 μA max with wake-up timer running Specified for 3 V and 5 V operation
Package and temperature range:
52-lead MQFP (14 mm × 14 mm), −40°C to +125°C 56-lead LFCSP (8 mm × 8 mm), −40°C to +85°C
APPLICATIONS
Multichannel sensor monitoring Industrial/environmental instrumentation
Weigh scales, pressure sensors, temperature monitoring Portable instrumentation, battery-powered systems Data logging, precision system monitoring
FUNCTIONAL BLOCK DIAGRAM
MicroConverter® Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
PRIMARY 24-BIT - ADC
MUX
A
AUXILIARY 24-BIT - ADC
TEMP SENSOR
EXTERNAL
VREF DETECT
POR
INTERNAL BAND GAP VREF
SINGLE-CYCLE 8061-BASED MCU
62 kBYTES FLASH/EE PROGRAM MEMORY 4 kBYTES FLASH/EE DATA MEMORY 2304 BYTES USER RAM
CURRENT SOURCE
MUX
PLL AND PRG CLOCK DIV
3 16 BIT TIMERS BAUD RATE TIMER
POWER SUPPLY MON WATCHDOG TIMER
OSC
WAKE-UP/ RTC TIMER
4 PARALLEL PORTS
UART, SPI, AND I 2C SERIAL I/O
AVCO
IEXC1 IEXC2
BUF DAC
PWM0
PWM1
ADuC845
AVDD
12-BIT DAC
DUAL 16-BIT - DAC
DUAL 16-BIT PWM
AIN1
AIN10 AINCOM
REFIN2+ REFIN2–
REFIN– REFIN+
RESET DVDD DGND
BUF
PGA
GND
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
XTAL1 XTAL2
Figure 1. ADuC845 Functional Block Diagram
04741-001
ADuC845/ADuC847/ADuC848 Data Sheet
TABLE OF CONTENTS
Features …………………………………………………………………………………. 1 Applications …………………………………………………………………………… 1 Revision History ……………………………………………………………………. 3 Specifications…………………………………………………………………………. 4 Abosolute Maximum Ratings ………………………………………………. 10
ESD Caution…………………………………………………………………….. 10 Pin Configurations and Function Descriptions ……………………. 11 General Description …………………………………………………………….. 15
8052 Instruction Set …………………………………………………………. 18 Timer Operation………………………………………………………………. 18 ALE ………………………………………………………………………………….. 18 External Memory Access………………………………………………….. 18 Complete SFR Map ………………………………………………………….. 19
Functional Description ………………………………………………………… 20 8051 Instruction Set …………………………………………………………. 20 Memory Organization ……………………………………………………… 22 Special Function Registers (SFRs)…………………………………….. 24 ADC Circuit Information…………………………………………………. 26 Auxiliary ADC (ADuC845 Only) …………………………………….. 32 Reference Inputs ………………………………………………………………. 32 Burnout Current Sources …………………………………………………. 32 Reference Detect Circuit ………………………………………………….. 33 Sinc Filter Register (SF) ……………………………………………………. 33 Σ-Δ Modulator …………………………………………………………………. 33 Digital Filter …………………………………………………………………….. 33 ADC Chopping ………………………………………………………………… 34 Calibration……………………………………………………………………….. 34 Programmable Gain Amplifier …………………………………………. 35 Bipolar/Unipolar Configuration ………………………………………. 35 Data Output Coding ………………………………………………………… 36 Excitation Currents ………………………………………………………….. 36
ADC Power-On ……………………………………………………………….. 36 Typical Performance Characteristics ……………………………………. 37 Functional Description………………………………………………………… 39
ADC SFR Interface…………………………………………………………… 39 ADCSTAT (ADC Status Register) ……………………………………. 40 ADCMODE (ADC Mode Register)………………………………….. 41 ADC0CON1 (Primary ADC Control Register)………………… 43 ADC0CON2 (Primary ADC Channel Select Register) …….. 44 SF (ADC Sinc Filter Control Register) ……………………………… 46 ICON (Excitation Current Sources Control Register) ………. 47 Nonvolatile Flash/EE Memory Overview …………………………. 48 Flash/EE Program Memory ……………………………………………… 49 User Download Mode (ULOAD)……………………………………… 50 Using Flash/EE Data Memory ………………………………………….. 51 Flash/EE Memory Timing ……………………………………………….. 52 DAC Circuit Information…………………………………………………. 53 Pulse-Width Modulator (PWM)………………………………………. 55 On-Chip PLL (PLLCON) …………………………………………………. 60 I2C Serial Interface …………………………………………………………… 61 SPI Serial Interface …………………………………………………………… 63 Using the SPI Interface …………………………………………………….. 66 Dual Data Pointers …………………………………………………………… 67 Power Supply Monitor ……………………………………………………… 68 Watchdog Timer ………………………………………………………………. 69 Time Interval Counter (TIC)……………………………………………. 70 8052-Compatible On-Chip Peripherals ……………………………. 73 Timers/Counters ……………………………………………………………… 75 UART Serial Interface………………………………………………………. 80 Interrupt System ………………………………………………………………. 87 Interrupt Priority……………………………………………………………… 88 Interrupt Vectors ……………………………………………………………… 88
Rev. D | Page 2 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Hardware Design Considerations ………………………………………….89 External Memory Interface………………………………………………..89 Power Supplies …………………………………………………………………..89 Power-On Reset Operation………………………………………………..90 Power Consumption ………………………………………………………….90 Power-Saving Modes …………………………………………………………90 Grounding and Board Layout Recommendations ……………..91
REVISION HISTORY
5/2016—Rev. C to Rev. D
Changed uC004 to AN-1074 ………………………………… Throughout Updated Outline Dimensions………………………………………………108 Changes to Ordering Guide…………………………………………………109
12/2012—Rev. B to Rev. C
Changes to Figure 3 and Table 3 ……………………………………………11 Changes to Burnout Current Sources Section………………………..32 Change to ADCMODE (ADC Mode Register) Section………….42 Changes to Mode 4 (Dual NRZ 16-Bit Σ-Δ DAC) Section …………58 Change to Hardware Slave Mode Section………………………………63 Updated Outline Dimensions………………………………………………104 Changes to Ordering Guide…………………………………………………105
2/2005—Rev. A to Rev. B
Changes to Figure 1…………………………………………………………………1 Changes to the Burnout Current Sources Section………………….32 Changes to the Excitation Currents Section…………………………..36 Changes to Table 30 ………………………………………………………………47 Changes to the Flash/EE Memory on the ADuC845, ADuC847, ADuC848 Section …………………………………………………………………..48 Changes to Figure 39 …………………………………………………………….57 Changes to On-Chip PLL (PLLCON) Section ……………………….60 Added 3 V Part Section Heading …………………………………………..88 Added 5 V Part Section …………………………………………………………88 Changes to Figure 70 …………………………………………………………….91 Changes to Figure 71 …………………………………………………………….93
Other Hardware Considerations………………………………………..92 QuickStart Development System …………………………………………..96 QuickStart-PLUS Development System …………………………….96 Timing Specifications ……………………………………………………………97 Outline Dimensions…………………………………………………………….106 Ordering Guide ……………………………………………………………….107
6/2004—Rev. 0 to Rev. A
Changes to Figure 5 ……………………………………………………………… 17 Changes to Figure 6 ……………………………………………………………… 18 Changes to Figure 7 ……………………………………………………………… 19 Changes to Table 5 ………………………………………………………………..24 Changes to Table 24 ……………………………………………………………… 41 Changes to Table 25 ……………………………………………………………… 43 Changes to Table 26 ……………………………………………………………… 44 Changes to Table 27 ……………………………………………………………… 45 Changes to User Download Mode Section…………………………….50 Added Figure 51 and Renumbered Subsequent Figures…………50 Edits to the DACH/DACL Data Registers Section…………………53 Changes to Table 34 ……………………………………………………………… 56 Added SPIDAT: SPI Data Register Section ……………………………65 Changes to Table 42 ……………………………………………………………… 67 Changes to Table 43 ……………………………………………………………… 68 Changes to Table 44 ……………………………………………………………… 69 Changes to Table 45 ……………………………………………………………… 71 Changes to Table 50 ……………………………………………………………… 75 Changes to Timer/Counter 0 and 1 Data Registers Section………..76 Changes to Table 54 ……………………………………………………………… 80 Added the SBUF—UART Serial Port Data Register Section ………80 Addition to the Timer 3 Generated Baud Rates Section ………..83 Added Table 57 and Renumbered Subsequent Tables ……………84 Changes to Table 61 ……………………………………………………………… 86
4/2004—Revision 0: Initial Version
Rev. D | Page 3 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
SPECIFICATIONS1
AVDD =2.7Vto3.6Vor4.75Vto5.25V,DVDD =2.7Vto3.6Vor4.75Vto5.25V,REFIN(+)=2.5V,REFIN(–)=AGND;AGND= DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz crystal; all specifications TMIN to TMAX, unless otherwise noted. Input buffer on for primary ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted.
Table 1.
Parameter
PRIMARY ADC Conversion Rate
No Missing Codes2
Resolution (ADuC845/ADuC847) Resolution (ADuC848)
Output Noise (ADuC845/ADuC847)
Output Noise (ADuC848) Integral Nonlinearity
Offset Error3
Offset Error Drift vs. Temperature2
Full-Scale Error4 ADuC845/ADuC847 ADuC848
Gain Error Drift vs. Temperature4 Power Supply Rejection
PRIMARY ADC ANALOG INPUTS Differential Input Voltage Ranges 5, 6 Bipolar Mode (ADC0CON1.5 = 0)
Unipolar Mode (ADC0CON1.5 = 1)
ADC Range Matching Common-Mode Rejection DC
On AIN
Common-Mode Rejection 50 Hz/60 Hz2
On AIN
Test Conditions/Comments
Chop on (ADCMODE.3 = 0)
Chop off (ADCMODE.3 = 1)
≤26.7 Hz update rate with chop enabled ≤80.3 Hz update rate with chop disabled
Output noise varies with selected update rates, gain range, and chop status.
Output noise varies with selected update rates, gain range, and chop status.
1 LSB16
Chop on
Chop off, offset error is in the order of the noise for the programmed gain and update rate following a calibration.
Chop on (ADCMODE.3 = 0) Chop off (ADCMODE.3 = 1)
±20 mV to ±2.56 V ±20 mV to ±640 mV ±1.28 V to ±2.56 V
AIN = 1 V, ±2.56 V, chop enabled
AIN = 7.8 mV, ±20 mV, chop enabled AIN = 1 V, ±2.56 V, chop disabled2
Gain = 1 to 128
VREF = REFIN(+) − REFIN(−) or REFIN2(+) − REFIN2(−) (or Int 1.25 VREF)
VREF = REFIN(+) − REFIN(−) or REFIN2(+) − REFIN2(−) (or Int 1.25 VREF)
AIN = 18 mV, chop enabled
Chop enabled, chop disabled
AIN = 7.8 mV, range = ±20 mV AIN = 1 V, range = ±2.56 V
50 Hz/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz update rate, chop enabled, REJ60 enabled
AIN = 7.8 mV, range = ±20 mV AIN = 1 V, range = ±2.56 V
Min Typ Max
Unit
5.4 105 16.06 1365 24
24
See Table 11 and Table 15 See Table 13 and Table 17 See Table 10 and Table 14
See Table 12 and Table 16
±15
±3
±10 ±200
±10 ±10 ±0.5 ±0.5
80
113
80
Hz Hz Bits Bits
μV (rms) μV (rms)
ppm of FSR μV
nV/°C nV/°C
μV
μV LSB16 ppm/°C
dB dB dB
±1.024 × VREF/GAIN
0 – 1.024 × VREF/GAIN ±2
95
113
95 90
V
V
μV
dB dB
dB dB
Rev. D | Page 4 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Min Typ Max
Unit
75
100 67
100
AGND + 0.1
AGND − 0.03
±5 ±15 ±125 ±2
±1 ±5
AVDD − 0.1
AVDD + 0.03
dB
dB dB
dB
nA
nA pA/°C pA/°C nA/V pA/V/°C V
V
1
0.3
2.5
±1 ±0.1
AVDD
0.65
125 90
75 100 67 100
V
V
μA/V nA/V/°C
V
dB dB
dB dB dB dB
5.4 105 16.06 1365 24
24
See Table 19 and Table 21 See Table 18 and Table 20
±15
±3 ±0.25 10 200 ±0.5 ±0.5
80
80
Hz Hz Bits Bits
ppm of FSR μV
LSB16
nV/°C nV/°C
LSB16 ppm/°C dB
dB
Parameter
Normal Mode Rejection 50 Hz/60 Hz2 On AIN
Analog Input Current2 Analog Input Current Drift
Average Input Current Average Input Current Drift Absolute AIN Voltage Limits2
Absolute AIN Voltage Limits2
EXTERNAL REFERENCE INPUTS REFIN(+) to REFIN(–) Voltage REFIN(+) to REFIN(–) Range2 Average Reference Input Current Average Reference Input Current
Drift
NOXREF Trigger Voltage
Common-Mode Rejection DC Rejection
50 Hz/60 Hz Rejection2
Normal Mode Rejection 50 Hz/60 Hz2
AUXILIARY ADC (ADuC845 Only) Conversion Rate
No Missing Codes2
Resolution
Output Noise Integral Nonlinearity Offset Error3
Offset Error Drift2
Full-Scale Error4
Gain Error Drift4
Power Supply Rejection
Test Conditions/Comments
50Hz/60Hz±1Hz,16.6HzFadc,SF=52H,chop on, REJ60 on
50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off, REJ60 on
50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off TMAX = 85°C, buffer on
TMAX = 125°C, buffer on
TMAX = 85°C, buffer on
TMAX = 125°C, buffer on
±2.56 V range, buffer bypassed
Buffer bypassed
AIN1 … AIN10 and AINCOM with buffer enabled
AIN1 … AIN10 and AINCOM with buffer bypassed
REFIN refers to both REFIN and REFIN2 REFIN refers to both REFIN and REFIN2 Both ADCs enabled
NOXREF (ADCSTAT.4) bit active if VREF > 0.3 V, and inactive if VREF > 0.65 V
AIN = 1 V, range = ±2.56 V
50 Hz/60 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V, SF = 82
50 Hz/60 Hz ±1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop on, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V, SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V, SF = 52H, chop off, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V, SF = 52H, chop off
Chop on
Chop off
≤26.7 Hz update rate, chop enabled 80.3 Hz update rate, chop disabled
Output noise varies with selected update rates. 1 LSB16
Chop on
Chop off
Chop on Chop off
AIN = 1 V, range = ±2.56 V, chop enabled AIN = 1 V, range = ±2.56 V, chop disabled
Rev. D | Page 5 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
Min Typ Max
Unit
±VREF
0 – VREF 125
±2
AGND − 0.03
75
100 67
100
AVDD + 0.03
V
V
nA/V pA/V/°C V
dB
dB dB
dB
+1.05 × FS 0.8 × FS 2.1 × FS
−1.05 × FS
V V V
0 – VREF 0 – AVDD 10
100
0.5
50
12
±3
±1
15 10
−1 ±50 ±1
V V kΩ pF Ω μA
Bits LSB LSB mV % %
μs nVs
1.25 − 1% 1.25 45
100
2.5 – 1% 2.5 50
±100
1.25 + 1%
2.5 + 1%
V
dB ppm/°C
±1% V dB ppm/°C
±2 90 52
°C °C/W °C/W
Parameter
AUXILIARY ADC ANALOG INPUTS (ADuC845 ONLY)
Differential Input Voltage Ranges5, 6 Bipolar Mode (ADC1CON.5 = 0) Unipolar Mode (ADC1CON.5 = 1) Average Analog Input Current Analog Input Current Drift Absolute AIN/AINCOM Voltage
Limits2, 7
Normal Mode Rejection 50 Hz/60 Hz2
On AIN and REFIN
ADC SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span
DAC
Voltage Range
Resistive Load Capactive Load Output Impedance ISINK
DC Specifications8 Resolution
Relative Accuracy Differential Nonlinearity Offset Error
Gain Error
AC Specifications2, 8
Voltage Output Settling Time Digital-to-Analog Glitch Energy
INTERNAL REFERENCE ADC Reference
Reference Voltage Power Supply Rejection Reference Tempco
DAC Reference
Reference Voltage Power Supply Rejection Reference Tempco
TEMPERATURE SENSOR (ADuC845 ONLY)
Accuracy
Thermal Impedance
Test Conditions/Comments
REFIN = REFIN(+) − REFIN(−) (or Int 1.25 VREF) REFIN = REFIN(+) − REFIN(−) (or Int 1.25 VREF)
50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on, REJ60 on
50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off, REJ60 on
50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off
DACCON.2 = 0
DACCON.2 = 1
From DAC output to AGND From DAC output to AGND
Guaranteed 12-bit monotonic
AVDD range VREF range
Settling time to 1 LSB of final value 1 LSB change at major carry
Chop enabled
Initial tolerance @ 25°C, VDD = 5 V
Initial tolerance @ 25°C, VDD = 5 V
MQFP LFCSP
Rev. D | Page 6 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Min Typ Max
Unit
−100
100
±10 0.03
nA
nA
% %/°C
200 ±10 200 ±1 20 1 0.1
AGND
AVDD − 0.6
μA
% ppm/°C % ppm/°C μA/V μA/V
V
2.63 4.63 ±3.0 ±4.0 2.63 4.63 ±3.0 ±4.0
V % % V % %
0.8 0.4
3.5 2.5
18 18
V V V V pF pF
2.0
1.3 0.95 0.8 0.4 0.3
35
−180 −20
0.8 0.4
3.0 2.5 1.4 1.1 0.85
±10 ±10
105 ±10 −660 −75
10
V V V
V V V V V
μA μA
μA μA μA μA pF
Parameter
TRANSDUCER BURNOUT CURRENT SOURCES
AIN+ Current AIN− Current
Initial Tolerance at 25°C
Drift
EXCITATION CURRENT SOURCES
Output Current
Initial Tolerance at 25°C
Drift
Initial Current Matching at 25°C Drift Matching
Line Regulation (AVDD)
Load Regulation
Output Compliance2
POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Trip Point Accuracy
DVDD Trip Point Selection Range DVDD Trip Point Accuracy
CRYSTAL OSCILLATOR (XTAL1 AND XTAL2)
Logic Inputs, XTAL1 Only2 VINL, Input Low Voltage
VINH, Input Low Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance LOGIC INPUTS
All Inputs Except SCLOCK, RESET, and XTAL12
VINL, Input Low Voltage
VINH, Input Low Voltage
SCLOCK and RESET Only (Schmidt Triggered Inputs)2
VT+
VT−
VT+ − VT−
Input Currents Port0,P1.0toP1.7,EA RESET
Port 2, Port 3
Test Conditions/Comments
AIN+ is the selected positive input (AIN4 or AIN6
only) to the primary ADC
AIN− is the selected negative input (AIN5 or AIN7 only) to the primary ADC
Available from each current source
Matching between both current sources AVDD = 5 V ± 5%
Four trip points selectable in this range TMAX = 85°C
TMAX = 125°C
Four trip points selectable in this range TMAX = 85°C
TMAX = 125°C
DVDD =5V DVDD =3V DVDD =5V DVDD =3V
DVDD =5V DVDD =3V
DVDD =5V
DVDD =3V
DVDD =5V
DVDD =3V
DVDD =5Vor3V
VIN =0VorVDD
VIN =0V,DVDD =5V
VIN = DVDD, DVDD = 5 V, internal pull-down VIN =DVDD,DVDD =5V
VIN =2V,DVDD =5V
VIN =0.45V,DVDD =5V
All digital inputs
Input Capacitance
Rev. D | Page 7 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
Min Typ Max
Unit
2.4 2.4
0.4 0.4 ±10
10
V V V V μA pF
600 3
2
20 20 20
30 30
ms ms ms
μs μs μs
μs μs
100,000 100
Cycles Years
2.7 3.6 4.75 5.25 2.7 3.6 4.75 5.25
10 25 31
180
40 53 50
20 33 30
1 3
1 0.5 30 60 200
−20 10
V V V V
mA mA μA
μA
μA
μA
μA
μA
μA
mA mA μA μA μA
μA μA
Parameter
LOGIC OUTPUTS (ALL DIGITAL OUTPUTS EXCEPT XTAL2) VOH, Output High Voltage2
VOL, Output Low Voltage
Floating State Leakage Current2
Floating State Output Capacitance START-UP TIME
At Power-On
After Ext RESET in Normal Mode After WDT RESET in Normal Mode From Power-Down Mode
Oscillator Running
Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with TIC Interrupt
Oscillator Powered Down Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS
Endurance9
Data Retention10 POWER REQUIREMENTS
Power Supply Voltages AVDD 3 V Nominal AVDD 5 V Nominal DVDD 3 V Nominal DVDD 5 V Nominal
5 V Power Consumption Normal Mode11, 12
DVDD Current
AVDD Current Power-Down Mode11, 12
DVDD Current
AVDD Current
Typical Additional Peripheral Currents (AIDD and DIDD) Primary ADC
Auxiliary ADC (ADuC845 Only) Power Supply Monitor
DAC
Dual Excitation Current Sources
ALE Off WDT
Test Conditions/Comments
DVDD=5V,ISOURCE=80μA DVDD = 3 V, ISOURCE = 20 μA ISINK = 8 mA, SCLOCK, SDATA ISINK = 1.6 mA on P0, P1, P2
Controlled via WDCON SFR PLLCON.7 = 0
PLLCON.7 = 1
4.75V
The modes of operation for the ADC are fully differential mode or pseudo differential mode. In fully differential mode, AIN1 to AIN2 are one differential pair, and AIN3 to AIN4 are another pair (AIN5 to AIN6, AIN7 to AIN8, and AIN9 to AIN10 are the others). In differential mode, all AIN(−) pin names imply the negative analog input of the selected differential pair, that is, AIN2, AIN4, AIN6, AIN8, AIN10. The term AIN(+) implies the positive input of the selected differential pair, that is, AIN1, AIN3, AIN5, AIN7, AIN9. In pseudo differential mode, each analog input is paired with the AINCOM pin, which can be biased up or tied to AGND. In this mode, the AIN(−) implies AINCOM, and AIN(+) implies any one of the ten analog input channels.
The configuration of the inputs (unipolar vs. bipolar) is shown in Figure 17.
FULLY DIFFERENTIAL FULLY DIFFERENTIAL
FULLY DIFFERENTIAL FULLY DIFFERENTIAL FULLY DIFFERENTIAL
Figure 17. Unipolar and Bipolar Channel Pairs
AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
AINCOM
AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
AINCOM
Rev. D | Page 35 of 110
INPUT 9 INPUT 10
04741-017
INPUT 7 INPUT 8
INPUT 5 INPUT 6
INPUT 3 INPUT 4
ADuC845/ADuC847/ADuC848 CSP PACKAGE
ADuC845/ADuC847/ADuC848 CSP PACKAGE
INPUT 1 INPUT 2
ADuC845/ADuC847/ADuC848 Data Sheet
DATA OUTPUT CODING
When the primary ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differ- ential input voltage resulting in a code of 000…000, a midscale voltage resulting in a code of 100…000, and a full-scale voltage resulting in a code of 111…111. The output code for any analog input voltage on the main ADC can be represented as follows:
Code – (AIN × GAIN × 2N)/(1.024 × VREF) where:
AIN is the analog input voltage.
GAIN is the PGA gain setting, that is, 1 on the 2.56 V range and 128 on the 20 mV range, and N = 24 (16 on the ADuC848).
The output code for any analog input voltage on the auxiliary ADC can be represented as follows:
Code = (AIN × 2N)/(VREF)
with the same definitions as used for the primary ADC above.
When the primary ADC is configured for bipolar operation, the coding is offset binary with negative full-scale voltage resulting in a code of 000…000, a zero differential voltage resulting in a code of 800…000, and a positive full-scale voltage resulting in a code of 111…111. The output from the primary ADC for any analog input voltage can be represented as follows:
Code = 2N−1[(AIN × GAIN)/(1.024 ×VREF) + 1] where:
AIN is the analog input voltage.
GAIN is the PGA gain, that is, 1 on the ±2.56 V range and 128 on the ±20 mV range.
N = 24 (16 on the ADuC848).
The output from the auxiliary ADC in bipolar mode can be represented as follows:
Code = 2N−1 [(AIN/VREF) + 1]
EXCITATION CURRENTS
The ADuC845/ADuC847/ADuC848 contain two matched, software-configurable 200 μA current sources. Both source current from AVDD, which is directed to either or both of the IEXC1 (Pin 11 whose alternate functions are P1.6/AIN7) or IEXC2 (Pin 12, whose alternate functions are P1.7/AIN8) pins on the device. These currents are controlled via the lower four bits in the ICON register (Table 30). These bits not only enable the current sources but also allow the configuration of the currents such that 200 μA can be sourced individually from both pins or can be combined to give a 400 μA source from one or the other of the outputs. These sources can be used to excite external resistive bridge or RTD sensors (see Figure 71).
ADC POWER-ON
The ADC typically takes 0.5 ms to power up from an initial start-up sequence or following a power-down event.
Rev. D | Page 36 of 110
Data Sheet
ADuC845/ADuC847/ADuC848
TYPICAL PERFORMANCE CHARACTERISTICS
00
–10 –20 –30 –40 –50 –60 –70 –80 –90
–100 –110 –120
0
10
20
30
40
FREQUENCY (Hz)
80
90
100 110
–10 –20 –30 –40 –50 –60 –70 –80 –90
–100 –110 –120
10
30 50 70 90
110 130 150 170 190 210 230 250 SF (Decimal)
50
60
70
Figure 18. Filter Response, Chop On, SF = 69 Decimal
Figure 21. 60 Hz Normal Mode Rejection vs. SF, Chop On
–10 –30 –50 –70 –90
–110
–130
10 –10 –30 –50 –70 –90 –110 –130 –150
10 –10 –30 –50 –70 –190 –110 –130 –150
–150
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
Figure 19. Filter Response, Chop On, SF = 255 Decimal
0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120
10 30 50 70 90 110130150170190210230250 SF (Decimal)
Figure 20. 50 Hz Normal Mode Rejection vs. SF Word, Chop On
FREQUENCY (Hz)
Figure 22. Chop Off, Fadc = 50 Hz, SF = 52H
04741-020
04741-019
04741-018
0.1 10.1 20.1 30.1 40.1 50.1 60.1 70.1 80.1 90.1 100.1 110.1 120.1 130.1 140.1 150.1 160.1 170.1
0.1 10.1 20.1 30.1 40.1 50.1 60.1 70.1 80.1 90.1 100.1 110.1 120.1 130.1 140.1 150.1 160.1 170.1
04741-023
04741-022
04741-021
GAIN (dB)
AMPLITUDE (dB)
GAIN (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
GAIN (dB)
Rev. D | Page 37 of 110
FREQUENCY (Hz)
Figure 23. Chop Off, SF = 52H, REJ60 Enabled
ADuC845/ADuC847/ADuC848
Data Sheet
00
–20 –40 –60 –80
–100 –120
–20 –40 –60 –80
–100 –120
FREQUENCY (Hz)
Figure 24. Chop On, Fadc = 16.6 Hz, SF = 52H
FREQUENCY (Hz)
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
04741-024
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
04741-025
0
0
AMPLITUDE (dB)
AMPLITUDE (dB)
Rev. D | Page 38 of 110
Figure 25. Chop On, Fadc = 16.6 Hz, SF = 52H, REJ60 Enabled
Data Sheet ADuC845/ADuC847/ADuC848
FUNCTIONAL DESCRIPTION
ADC SFR INTERFACE
The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following sections.
Table 22. ADC SFR Interface
Name
ADCSTAT ADCMODE ADC0CON1 ADC0CON2 ADC1CON SF
ICON ADC0L/M/H
ADC1L/M/H OF0L/M/H OF1L/H GN0L/M/H GN1L/H
Description
ADC Status Register. Holds the general status of the primary and auxiliary (ADuC845 only) ADCs.
ADC Mode Register. Controls the general modes of operation for primary and auxiliary (ADuC845 only) ADCs.
Primary ADC Control Register 1. Controls the specific configuration of the primary ADC.
Primary ADC Control Register 2. Controls the specific configuration of the primary ADC.
Auxiliary ADC Control Register. Controls the specific configuration of the auxiliary ADC. ADuC845 only.
Sinc Filter Register. Configures the decimation factor for the Sinc3 filter and, therefore, the primary and auxiliary (ADuC845
only) ADC update rates.
Current Source Control Register. Allows user control of the various on-chip current source options.
Primary ADC 24-bit (16-bit on the ADuC848) conversion result is held in these three 8-bit registers. ADC0L is not available on the ADuC848.
Auxiliary ADC 24-bit conversion result is held in these two 8-bit registers. ADuC845 only.
Primary ADC 24-bit offset calibration coefficient is held in these three 8-bit registers. OF0L is not available on the ADuC848. Auxiliary ADC 16-bit offset calibration coefficient is held in these two 8-bit registers. ADuC845 only.
Primary ADC 24-bit gain calibration coefficient is held in these three 8-bit registers. GN0L is not available on the ADuC848. Auxiliary ADC 16-bit gain calibration coefficient is held in these two 8-bit registers. ADuC845 only.
Rev. D | Page 39 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
ADCSTAT (ADC STATUS REGISTER)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions including REFIN± reference detect and conversion overflow/underflow flags.
SFR Address: D8H Power-On Default: 00H Bit Addressable: Yes
Table 23. ADCSTAT SFR Bit Designation
Name
RDY0
RDY1 CAL
NOXREF
ERR0
ERR1 ––– –––
Bit No.
7
6 5
4
3
2 1 0
Description
Ready Bit for the Primary ADC.
Set by hardware on completion of conversion or calibration.
Cleared directly by the user, or indirectly by a write to the mode bits, to start calibration. The primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared.
Ready Bit for Auxiliary (ADuC845 only) ADC.
Same definition as RDY0 referred to the auxiliary ADC. Valid on the ADuC845 only.
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
Note that calibration with the temperature sensor selected (auxiliary ADC on the ADuC845 only) fails to complete. No External Reference Bit (only active if primary or auxiliary (ADuC845 only) ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When set, conversion results are clamped to all 1s. Only detects invalid REFIN±, does not check REFIN2±.
Cleared to indicate valid VREF.
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all 0s or all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. Valid on the ADuC845 only.
Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care.
Rev. D | Page 40 of 110
Data Sheet ADuC845/ADuC847/ADuC848
ADCMODE (ADC MODE REGISTER)
Used to control the operational mode of both ADCs.
SFR Address: D1H Power-On Default: 08H Bit Addressable: No
Table 24. ADCMODE SFR Bit Designations
Name
––– REJ60
ADC0EN
ADC1EN (ADuC845 only)
CHOP
MD2, MD1, MD0
Bit No.
7 6
5
4
3
2, 1, 0
Description
Not Implemented. Write Don’t Care. Automatic 60 Hz Notch Select Bit.
Setting this bit places a notch in the frequency response at 60 Hz, allowing simultaneous 50 Hz and 60 Hz rejection at an SF word of 82 decimal. This 60 Hz notch can be set only if SF ≥68 decimal, that is, the regular filter notch must be ≤60 Hz. This second notch is placed at 60 Hz only if the device clock is at 32.768 kHz. Primary ADC Enable.
Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0.
Cleared by the user to place the primary ADC into power-down mode.
Auxiliary (ADuC845 only) ADC Enable.
Set by the user to enable the auxiliary (ADuC845 only) ADC and place it in the mode selected in MD2–MD0. Cleared by the user to place the auxiliary (ADuC845 only) ADC in power-down mode.
Chop Mode Disable.
Set by the user to disable chop mode on both the primary and auxiliary (ADuC845 only) ADC allowing a three times higher ADC data throughput. SF values as low as 3 are allowed with this bit set, giving up to 1.3 kHz ADC update rates.
Cleared by the user to enable chop mode on both the primary and auxiliary (ADuC845 only) ADC. Primary and Auxiliary (ADuC845 only) ADC Mode Bits.
These bits select the operational mode of the enabled ADC as follows: MD2 MD1 MD0
0 0 0 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 1 1 1
ADC Power-Down Mode (Power-On Default).
Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided.
Single Conversion Mode. In single conversion mode, a single conversion is performed on the enabled ADC. Upon completion of a conversion, the ADC data registers (ADC0H/M/L and/or ADC1H/M/L (ADuC845 only)) are updated. The relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2−MD0 accordingly being written to 000.
Note that ADC0L is not available on the ADuC848.
Continuous Conversion. In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate (see the Sinc Filter SFR Bit Designations in Table 28).
Internal Zero-Scale Calibration. Internal short automatically connected to the enabled ADC input(s).
Internal Full-Scale Calibration. Internal or external REFIN± or REFIN2± VREF (as determined by XREF bits in ADC0CON2 and/or AXREF (ADuC845 only) in ADC1CON (ADuC845 only) is automatically connected to the enabled ADC input(s) for this calibration.
System Zero-Scale Calibration. User should connect system zero-scale input to the enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the ADC0CON2 and ADC1CON (ADuC845 only) registers.
System Full-Scale Calibration. User should connect system full-scale input to the enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the ADC0CON2 and ADC1CON (ADuC845 only) registers.
Rev. D | Page 41 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
Notes on the ADCMODE Register
Any change to the MD bits immediately resets both ADCs (auxiliary ADC only applicable to the ADuC845). A write to the MD2–MD0 bits with no change in contents is also treated as a reset. (See the exception to this in the third note of this section.)
If ADC1CON1 and ADC1CON2 are written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, both ADCs are also immediately reset. In other words, the primary ADC is given priority over the auxiliary ADC and any change requested on the primary ADC is immediately responded to. Only applicable to the ADuC845.
On the other hand, if ADC1CON is written to or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from the primary ADC, the auxiliary ADC falls into step with the outputs of the primary ADC. The result is that the first conversion time for the auxiliary ADC is delayed by up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC. Only applicable to ADuC845. If the ADC1CON write occurs after the primary ADC has completed its operation, the auxiliary ADC can respond immediately without having to fall into step with the primary ADCs output cycle.
If the devices are powered down via the PD bit in the PCON register, the current ADCMODE bits are preserved, that is, they are not reset to default state. Upon a subsequent resumption of normal operating mode, the ADCs restarts the selected operation defined by the ADCMODE register.
Once ADCMODE has been written with a calibration mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–MD0 bits are reset to 000B to indicate that the ADC is back in power-down mode.
Any calibration request of the auxiliary ADC while the temperature sensor is selected fails to complete. Although the RDY1 bit is set at the end of the calibration cycle, no update of the calibration SFRs takes place, and the ERR1 bit is set. ADuC845 only.
Calibrations performed at maximum SF (see Table 28) value (slowest ADC throughput rate) help to ensure optimum calibration.
The duration of a calibration cycle is 2/Fadc for chop-on mode and 4/Fadc for chop-off mode.
Rev. D | Page 42 of 110
Data Sheet ADuC845/ADuC847/ADuC848
ADC0CON1 (PRIMARY ADC CONTROL REGISTER)
ADC0CON1 is used to configure the primary ADC for buffer, unipolar, or bipolar coding, and ADC range configuration.
SFR Address: D2H Power-On Default: 07H Bit Addressable: No
Table 25. ADC0CON1 SFR Bit Designations
Name
BUF1, BUF0
UNI
–––
–––
RN2, RN1, RN0
Bit No.
7, 6
5
4
3
2, 1, 0
Description
Buffer Configuration Bits. BUF1 BUF0
0 0
0 1
1 0
1 1
Primary ADC Unipolar Bit.
Set by the user to enable unipolar coding; zero differential input results in 000000H output. Cleared by the user to enable bipolar coding; zero differential input results in 800000H output. Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Primary ADC Range Bits. Written by the user to select the primary ADC input range as follows:
RN2 RN1 RN0 0 0 0
0 0 1
0 1 0
0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Selected primary ADC input range (VREF = 2.5 V) ±20 mV (0 mV to 20 mV in unipolar mode)
±40 mV (0 mV to 40 mV in unipolar mode)
±80 mV (0 mV to 80 mV in unipolar mode) ±160 mV (0 mV to 160 mV in unipolar mode) ±320 mV (0 mV to 320 mV in unipolar mode) ±640 mV (0 mV to 640 mV in unipolar mode) ±1.28 V (0 V to 1.28 V in unipolar mode)
±2.56 V (0 V to 2.56 V in unipolar mode)
Buffer Configuration
ADC0+ and ADC0− are buffered Reserved
Buffer Bypass
Reserved
Rev. D | Page 43 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
ADC0CON2 (PRIMARY ADC CHANNEL SELECT REGISTER)
ADC0CON2 is used to select a reference source and channel for the primary ADC.
SFR Address: E6H Power-On Default: 00H Bit Addressable: No
Table 26. ADC0CON2 SFR Bit Designations
Name
XREF1, XREF0
–––
–––
CH3, CH2, CH1, CH0
Bit No.
7, 6
5
4
3, 2, 1, 0
Description
Primary ADC External Reference Select Bit.
Set by the user to enable the primary ADC to use the external reference via REFIN± or REFIN2±. Cleared by the user to enable the primary ADC to use the internal band gap reference (VREF = 1.25 V). XREF1 XREF0
0 0 Internal 1.25 V Reference.
0 1 REFIN±Selected.
1 0 REFIN2± (AIN3/AIN4) Selected.
1 1 Reserved.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Primary ADC Channel Select Bits. Written by the user to select the primary ADC channel as follows:
CH3 CH2 CH1 CH0 0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0
1 1 1 1
Selected Primary ADC Input Channel. AIN1–AINCOM
AIN2–AINCOM
AIN3–AINCOM
AIN4–AINCOM
AIN5–AINCOM
AIN6–AINCOM
AIN7–AINCOM
AIN8–AINCOM
AIN9–AINCOM (LFCSP package only; not a valid selection on the MQFP package)
AIN10–AINCOM (LFCSP package only; not a valid selection on the MQFP package)
AIN1–AIN2
AIN3–AIN4
AIN5–AIN6 AIN7–AIN8
AIN9–AIN10 (LFCSP package only; not a valid selection on the MQFP package)
AINCOM–AINCOM
Note that because the reference-detect does not operate on the REFIN2± pair, the REFIN2± pins can go below 1 V.
Rev. D | Page 44 of 110
Data Sheet ADuC845/ADuC847/ADuC848
ADC1CON (AUXILIARY ADC CONTROL REGISTER) (ADUC845 ONLY)
ADC1CON is used to configure the auxiliary ADC for reference, channel selection, and unipolar or bipolar coding. The auxiliary ADC is
available only on the ADuC845.
SFR Address: D3H Power-On Default: 00H Bit Addressable: No
Table 27. ADC1CON SFR Bit Designations
Name
––– AXREF
AUNI
–––
ACH3, ACH2, ACH1, ACH0
Bit No.
7 6
5
4
3, 2, 1, 0
Description
Not Implemented. Write Don’t Care.
Auxiliary (ADuC845 only) ADC External Reference Bit.
Set by the user to enable the auxiliary ADC to use the external reference via REFIN±. Cleared by the user to enable the auxiliary ADC to use the internal band gap reference. Auxiliary ADC cannot use the REFIN2± reference inputs.
Auxiliary (ADuC845 only) ADC Unipolar Bit.
Set by the user to enable unipolar coding, that is, zero input results in 000000H output. Cleared by the user to enable bipolar coding, zero input results in 800000H output.
Not Implemented. Write Don’t Care.
Auxiliary ADC Channel Select Bits. Written by the user to select the auxiliary ADC channel.
ACH3 ACH2 ACH1 ACH0 0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Selected Auxiliary ADC Input Range (VREF = 2.5 V). AIN1–AINCOM
AIN2–AINCOM
AIN3–AINCOM
AIN4–AINCOM
AIN5–AINCOM
AIN6–AINCOM
AIN7–AINCOM
AIN8–AINCOM
AIN9–AINCOM (not a valid selection on the MQFP package) AIN10–AINCOM (not a valid selection on the MQFP package) AIN1–AIN2
AIN3–AIN4 AIN5–AIN6 AIN7–AIN8 Temperature Sensor1 AINCOM–AINCOM
1 Note the following about the temperature sensor:
When the temperature sensor is selected, user code must select the internal reference via the AXREF bit and clear the AUNI bit (ADC1CON.5) to select bipolar coding. Chop mode must be enabled for correct temperature sensor operation.
The temperature sensor is factory calibrated to yield conversion results 800000H at 0°C (ADC chop on).
A +1°C change in temperature results in a +1 LSB change in the ADC1H register ADC conversion result
The temperature sensor is not available on the ADuC847 or ADuC848.
Rev. D | Page 45 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
SF (ADC SINC FILTER CONTROL REGISTER)
The SF register is used to configure the decimation factor for the ADC, and therefore, has a direct influence on the ADC throughput rate.
SFR Address: D4H Power-On Default: 45H Bit Addressable: No
Table 28. Sinc Filter SFR Bit Designations
SF.7 SF.0
01
The bits in this register set the decimation factor of the ADC. This has a direct bearing on the throughput rate of the ADC along with the chop setting. The equations used to determine the ADC throughput rate are
SF.6
SF.5
SF.4
SF.3
SF.2
SF.1
1
0
0
0
1
0
Fadc (Chop On) = 1 × 32.768 kHz 3 8 SFword
where SFword is in decimal.
Fadc (Chop Off) = 1 × 32.768 kHz
8 SFword where SFword is in decimal.
Table 29. SF SFR Bit Examples
Chop Enabled (ADCMODE.3 = 0) SF (Decimal)
131
69
82 255
Chop Disabled (ADCMODE.3 = 1) SF (Decimal)
3
69
82 255
1 With chop enabled, if an SF word smaller than 13 is written to this SF register, the filter automatically defaults to 13.
Tsettle (ms)
19.04 101.1 120.1 373.54
Tsettle (ms)
2.2 50.52 60.06 186.8
SF (Hexadecimal)
Fadc (Hz)
Tadc (ms)
0D 45 52 FF
105.3 19.79 16.65 5.35
9.52 50.53 60.06 186.77
SF (Hexadecimal)
Fadc (Hz)
Tadc (ms)
03 45 52 FF
1365.3 59.36 49.95 16.06
0.73 16.84 20.02 62.25
During ADC calibration, the user-programmed value of SF word is used. The SF word does not default to the maximum setting (255) as it did on previous MicroConverter® products. However, for optimum calibration results, it is recommended that the maximum SF word be set.
Rev. D | Page 46 of 110
Data Sheet ADuC845/ADuC847/ADuC848
ICON (EXCITATION CURRENT SOURCES CONTROL REGISTER)
The ICON register is used to configure the current sources and the burnout detection source.
SFR Address: D5H Power-On Default: 00H Bit Addressable: No
Table 30. Excitation Current Source SFR Bit Designations
Name
––– ICON.6
ICON.5 ICON.4 ICON.3 ICON.2 ICON.1 ICON.0
Bit No.
7 6
5 4 3 2 1 0
Description
Not Implemented. Write Don’t Care.
Burnout Current Enable Bit.
When set, this bit enables the sensor burnout current sources on primary ADC channels AIN5/AIN6 or AIN7/AIN8. Not available on any other ADC input pins or on the auxiliary ADC (ADuC845 only).
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
IEXC2 Pin Select. 0 selects AIN8, 1 selects AIN7 IEXC1 Pin Select. 0 selects AIN7, 1 selects AIN8 IEXC2 Enable Bit (0 = disable).
IEXC1 Enable Bit (0 = disable).
A write to the ICON register has an immediate effect but does not reset the ADCs. Therefore, if a current source is changed while an ADC is already converting, the user must wait until the third or fourth output at least (depending on the status of the chop mode) to see a fully settled new output.
Both IEXC1 and IEXC2 can be configured to operate on the same output pin thereby increasing the current source capability to 400 μA.
Rev. D | Page 47 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
NONVOLATILE FLASH/EE MEMORY OVERVIEW
The ADuC845/ADuC847/ADuC848 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable code and data memory space.
Like EEPROM, flash memory can be programmed in-system at the byte level, although it must first be erased, in page blocks. Thus, flash memory is often and more correctly referred to as Flash/EE memory.
No ULOAD mode is available on the 8-kbyte part since the bootload area on the 8-kbyte part is 8 kbytes long, so no usable user program space remains. The kernel still resides in the protected area from 62 kbytes to 64 kbytes.
Flash/EE Memory Reliability
The Flash/EE program and data memory arrays on the ADuC845/ADuC847/ADuC848 are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events:
1. Initial page erase sequence
2. Read/verify sequence
3. Byte program sequence
4. Second read/verify sequence
In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00H to FFH until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory.
As indicated in the Specifications table, the ADuC845/ADuC847/ ADuC848 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of – 40°C, +25°C, +85°C, and +125°C. (The LFCSP package is qualified to +85°C only.) The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25°C.
Retention is the ability of the Flash/EE memory to retain its programmed data over time. Again, the devices have been qualified in accordance with the formal JEDEC Retention Lifetime Specifi- cation (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ as shown in Figure 27.
EPROM TECHNOLOGY
SPACE EFFICIENT/ DENSITY
EEPROM TECHNOLOGY
IN-CIRCUIT REPROGRAMMABLE
FLASH/EE MEMORY TECHNOLOGY
Figure 26. Flash/EE Memory Development
Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. The Flash/EE memory technology allows the user to update program code space in- circuit, without needing to replace onetime programmable (OTP) devices at remote operating nodes.
Flash/EE Memory on the ADuC845, ADuC847, ADuC848
The ADuC845/ADuC847/ADuC848 provide two arrays of Flash/EE memory for user applications—up to 62 kbytes of Flash/EE program space and 4 kbytes of Flash/EE data memory space. Also, 8-kbyte and 32-kbyte program memory options are available. All examples and references in this datasheet use the 62-kbyte option; however, similar protocols and procedures are applicable to the 32-kbyte and 8-kbyte options unless otherwise noted, provided that the difference in memory size is taken into account.
The 62 kbytes Flash/EE code space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed in-circuit, using the serial download mode provided, using conventional third party memory programmers, or via any user-defined protocol in user download (ULOAD) mode.
The 4-kbyte Flash/EE data memory space can be used as a general-purpose, nonvolatile scratchpad area. User access to this area is via a group of seven SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte pages.
All the following sections use the 62-kbyte program space as an example when referring to program and ULOAD mode. For the 64-kbyte part, the ULOAD area takes up the top 6 kbytes of the program space, that is, from 56 kbytes to 62 kbytes. For the 32-kbyte part, the ULOAD space moves to the top 8 kbytes of the on-chip program memory, that is., from 24 kbytes to 32 kbytes.
Rev. D | Page 48 of 110
04741-026
Data Sheet ADuC845/ADuC847/ADuC848
300 250
200 150 100
50
0
40 50 60 70 80 90 100 110
TJ JUNCTION TEMPERATURE (C) Figure 27. Flash/EE Memory Data Retention
FLASH/EE PROGRAM MEMORY
The ADuC845/ADuC847/ADuC848 contain a 64-kbyte array of Flash/EE program memory. The lower 62 kbytes of this program memory are available to the user for program storage or as additional NV data memory.
The upper 2 kbytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download, serial debug, and nonintrusive single-pin emulation. These 2 kbytes of embedded firmware also contain a power-on configuration routine that downloads factory cali- brated coefficients to the various calibrated peripherals such as ADC, temperature sensor, current sources, band gap, and references.
These 2 kbytes of embedded firmware are hidden from the user code. Attempts to read this space read 0s; therefore, the embed- ded firmware appears as NOP instructions to user code.
In normal operating mode (power-on default), the 62 kbytes of user Flash/EE program memory appear as a single block. This block is used to store the user code as shown in Figure 28.
EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 kBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS NOP INSTRUCTIONS TO USER CODE.
USER PROGRAM MEMORY
62 kBYTES OF FLASH/EE PROGRAM MEMORY ARE AVAILABLE TO THE USER. ALL OF THIS SPACE CAN BE PROGRAMMED FROM THE PERMANENTLY EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN PARALLEL PROGRAMMING MODE.
Figure 28. Flash/EE Program Memory Map in Normal Mode
In normal mode, the 62 kbytes of Flash/EE program memory can be programmed by serial downloading and by parallel programming.
Serial Downloading (In-Circuit Programming)
The ADuC845/ADuC847/ADuC848 facilitate code download via the standard UART serial port. The devices enter serial download mode after a reset or a power cycle if the PSEN pin is pulled low through an external 1 kΩ resistor. Once in serial download mode, the hidden embedded download kernel executes. This allows the user to download code to the full
62 kbytes of Flash/EE program memory while the device is in circuit in its target application hardware.
A PC serial download executable (WSD.EXE) is provided as part of the ADuC845/ADuC847/ADuC848 Quick Start development system. The AN-1074 Application Note fully describes the serial download protocol that is used by the embedded download kernel.
Parallel Programming
The parallel programming mode is fully compatible with conventional third-party flash or EEPROM device programmers. A block diagram of the external pin configuration required to support parallel programming is shown in Figure 29. In this mode, Ports 0 and 2 operate as the external address bus interface, P3 operates as the external data bus interface, and P1.0 operates as the write enable strobe. P1.1, P1.2, P1.3, and P1.4 are used as general configuration ports that configure the device for various program and erase operations during parallel programming.
ADI SPECIFICATION 100 YEARS MIN. AT TJ = 55C
+5V
ADuC845/ ADuC847/ ADuC848
P1.4–P1.1
P3.7–P3.0
COMMAND
TIMING ENABLE
DATA
P1.7–P1.5
P1.0 RESET
EA
GND VDD
Figure 29. Flash/EE Memory Parallel Programming
The command words that are assigned to P1.1, P1.2, P1.3, and P1.4 are described in Table 31.
Table 31. Flash/EE Memory Parallel Programming Modes
FFFFH 2kBYTE F800H
F7FFH 62kBYTE 0000H
Port 1 Pins
P1.4 P1.3 P1.2 P1.1
0 0 0 0
Programming Mode
Erase Flash/EE Program, Data, and Security Mode
1 0 1 0
0 0 1 0
1 0 1 1
0 0 1 1
1 1 0 0 ProgramSecurityModes
Program Code Byte Program Data Byte Read Code Byte Read Data Byte
1 1 0 1 All other codes
Read/Verify Security Modes Redundant
Rev. D | Page 49 of 110
04741-029
04741-030
04741-028
RETENTION (Years)
ADuC845/ADuC847/ADuC848 Data Sheet
USER DOWNLOAD MODE (ULOAD)
Figure 28 shows that it is possible to use the 62 kbytes of Flash/EE program memory available to the user as one single block of memory. In this mode, all the Flash/EE memory is read-only to user code.
However, most of the Flash/EE program memory can also be written to during run time simply by entering ULOAD mode. In ULOAD mode, the lower 56 kbytes of program memory can be erased and reprogrammed by the user software as shown in Figure 30. ULOAD mode can be used to upgrade the code in the field via any user-defined download protocol. By configuring the SPI port on the ADuC845/ADuC847/ADuC848 as a slave, it is possible to completely reprogram the 56 kbytes of Flash/EE program memory in under 5 s (see the AN-1074 Application Note).
Alternatively, ULOAD mode can be used to save data to the
56 kbytes of Flash/EE memory. This can be extremely useful in data logging applications where the devices can provide up to 60 kbytes of data memory on-chip (4 kbytes of dedicated Flash/EE data memory also exist).
The upper 6 kbytes of the 62 kbytes of Flash/EE program memory (8 kbytes on the 32-kbyte parts) are programmable only via serial download or parallel programming. This means that this space appears as read-only to user code; therefore, it cannot be accidentally erased or reprogrammed by erroneous code execution, making it very suitable to use the 6 kbytes as a bootloader. A bootload enable option exists in the Windows® serial downloader (WSD) to “Always RUN from E000H after Reset.” If using a bootloader, this option is recommended to ensure that the bootloader always executes correct code after reset.
Programming the Flash/EE program memory via ULOAD mode is described in the Flash/EE Memory Control SFR section of ECON and also in the AN-1074 Application Note.
EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 kBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS NOP INSTRUCTIONS TO USER CODE.
The 32-kbyte memory parts have the user bootload space starting at 6000H. The memory mapping is shown in Figure 31.
EMBEDDED DOWNLOAD/DEBUG KERNEL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 32 kBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS NOP INSTRUCTIONS TO USER CODE.
FFFFH 2kBYTE F800H
8000H 8kBYTE 6000H
5FFFH 24kBYTE 0000H
32 kBYTES OF USER CODE MEMORY
NOT AVAILABLE TO USER
USER BOOTLOADER SPACE
THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE
USER DOWNLOADER SPACE EITHER THE DOWNLOAD/DEBUG KERNEL OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE
FFFFH 2kBYTE F800H
F7FFH 6kBYTE E000H
dFFFH 56kBYTE 0000H
62 kBYTES OF USER CODE MEMORY
USER BOOTLOADER SPACE THE USER BOOTLOADER
SPACE CAN BE PROGRAMMED IN DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE
USER DOWNLOADER SPACE EITHER THE DOWNLOAD/DEBUG
KERNEL OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE
Figure 31. Flash/EE Program Memory Map in ULOAD Mode (32-kbyte Part)
ULOAD mode is not available on the 8-kbyte Flash/EE program memory parts.
Flash/EE Program Memory Security
The ADuC845/ADuC847/ADuC848 facilitate three modes of Flash/EE program memory security: the lock, secure, and serial safe modes. These modes can be independently activated, restricting access to the internal code space. They can be enabled as part of serial download protocol, as described in the AN-1074 Application Note, or via parallel programming.
Lock Mode
This mode locks the code memory, disabling parallel program- ming of the program memory. However, reading the memory in parallel mode and reading the memory via a MOVC command from external memory are still allowed. This mode is deactivated by initiating an ERASE CODE AND DATA command in serial download or parallel programming modes.
Secure Mode
This mode locks the code memory, disabling parallel program- ming of the program memory. Reading/verifying the memory in parallel mode and reading the internal memory via a MOVC command from external memory are also disabled. This mode is deactivated by initiating an ERASE CODE AND DATA command in serial download or parallel programming modes.
Serial Safe Mode
This mode disables serial download capability on the device. If serial safe mode is activated and an attempt is made to reset the device into serial download mode, that is, RESET asserted (pulled high) and de-asserted (pulled low) with PSEN low, the device interprets the serial download reset as a normal reset only. It therefore does not enter serial download mode, but executes only a normal reset sequence. Serial safe mode can be disabled only by initiating an ERASE CODE AND DATA command in parallel programming mode.
Figure 30. Flash/EE Program Memory Map in ULOAD Mode (62-kbyte Part)
Rev. D | Page 50 of 110
04741-031
04741-074
Data Sheet ADuC845/ADuC847/ADuC848
USING FLASH/EE DATA MEMORY
The 4 kbytes of Flash/EE data memory are configured as 1024 pages, each of 4 bytes. As with the other ADuC845/ADuC847/ ADuC848 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) holds the 4 bytes of data at each page. The page is addressed via the EADRH and EADRL registers. Finally, ECON is an 8-bit control register that can be written to with one of nine Flash/EE memory access commands to trigger various read, write, erase, and verify functions. A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 32.
ECON—Flash/EE Memory Control SFR
Programming either Flash/EE data memory or Flash/EE program memory is done through the Flash/EE memory control SFR (ECON). This SFR allows the user to read, write,
Table 32. ECON—Flash/EE Memory Commands
ECON Value
01H Read 02H Write
03H
04H Verify
05H Erase Page
06H Erase All 81H ReadByte
82H WriteByte 0FH EXULOAD F0H ULOAD
erase, or verify the 4 kbytes of Flash/EE data memory or the 56 kbytes of Flash/EE program memory.
BYTE 1 (0FFCH)
3FFH 3FEH
03H 02H 01H 00H
BYTE 1 (0FF8H)
BYTE 1 (000CH)
BYTE 1 (0008H)
BYTE 1 (0004H)
BYTE 1 (0000H)
BYTE 2 (0FFDH)
BYTE 2 (0FF9H)
BYTE 2 (000DH)
BYTE 2 (0009H)
BYTE 2 (0005H)
BYTE 2 (0001H)
BYTE 3 (0FFEH)
BYTE 3 (0FFAH)
BYTE 3 (000EH)
BYTE 3 (000AH)
BYTE 3 (0006H)
BYTE 3 (0002H)
BYTE 4
(0FFFH)
BYTE 4 (0FFBH)
BYTE 4 (000FH)
BYTE 4 (000BH)
BYTE 4 (0007H)
BYTE 4 (0003H)
BYTE ADDRESSES ARE GIVEN IN BRACKETS
Figure 32. Flash/EE Data Memory Control and Configuration
Command Description (ULOAD Mode)
Not implemented. Use the MOVC instruction.
Bytes 0 to 255 of internal XRAM are written to the 256 bytes of Flash/EE program memory at the page address given by EADRH/L (0 ≤ EADRH/L < E0H).
Note that the 256 bytes in the page being addressed must be pre-erased.
Reserved.
Not implemented. Use the MOVC and MOVX instructions to verify the Write in software.
64-byte page of FLASH/EE program memory addressed by the byte address EADRH/L is erased. A new page starts when EADRL is equal to 00H, 80H, or C0H.
The entire 56 kbytes of ULOAD are erased. Not implemented. Use the MOVC command.
The byte in EDATA1 is written into Flash/EE program memory at the byte address EADRH/L (0 ≤ EADRH/L ≤ DFFFH).
Enters normal mode, directing subsequent ECON instructions
to operate on the Flash/EE data memory.
Enables the ECON instructions to operate on the Flash/EE program memory. ULOAD entry mode.
Command Description (Normal Mode, Power-On Default)
4 bytes in the Flash/EE data memory, addressed by the page address EADRH/L, are read into EDATA1–4.
Results in 4 bytes in EDATA1–4 being written to the Flash/EE data memory, at the page address given by EADRH (0 ≤ EADRH < 0400H). Note that the 4 bytes in the page being addressed must be pre-erased.
Reserved.
Verifies that the data in EDATA1–4 is contained in the page address given by EADRH/L. A subsequent read of the ECON SFR results in a 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification.
4-byte page of Flash/EE data memory address is erased by the page address EADRH/L.
4 kbytes of Flash/EE data memory are erased.
The byte in the Flash/EE data memory, addressed by the
byte address EADRH/L, is read into EDATA1 (0 ≤ EADRH/L ≤
0FFFH).
The byte in EDATA1 is written into Flash/EE data memory at the byte address EADRH/L.
Configures the ECON instructions (above) to operate on
Flash/EE data memory.
Enters ULOAD mode; subsequent ECON instructions operate on Flash/EE program memory.
Rev. D | Page 51 of 110
EDATA1 SFR
EDATA2 SFR
EDATA3 SFR
EDATA4 SFR
04741-032
PAGE ADDRESS (EADRH/L)
ADuC845/ADuC847/ADuC848 Data Sheet
Example: Programming the Flash/EE Data Memory
A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of the Flash/EE data array involves
1. Setting EADRH/L with the page address.
2. Writing the data to be programmed to the EDATA1–4.
3. Writing the ECON SFR with the appropriate command.
Step 1: Set Up the Page Address
Address registers EADRH and EADRL hold the high byte address and the low byte address of the page to be addressed. The assembly language to set up the address may appear as
MOV EADRH, #0 ;Set Page Address Pointer MOV EADRL, #03H
Step 2: Set Up the EDATA Registers
Write the four values to be written into the page into the four SFRs EDATA1–4. Unfortunately, the user does not know three of them. Thus, the user must read the current page and overwrite the second byte.
MOV ECON, #1 ;Read Page into EDATA1-4 MOV EDATA2, #0F3H ;Overwrite Byte 2
Step 3: Program Page
A byte in the Flash/EE array can be programmed only if it has previously been erased. Specifically, a byte can be programmed only if it already holds the value FFH. Because of the Flash/EE architecture, this erasure must happen at a page level; therefore, a minimum of 4 bytes (1 page) are erased when an erase command is initiated. Once the page is erased, the user can program the 4 bytes in-page and then perform a verification of the data.
FLASH/EE MEMORY TIMING
Typical program and erase times for the devices are as follows:
Normal Mode (Operating on Flash/EE Data Memory)
MOV ECON, #5
MOV ECON, #2
MOV ECON, #4
MOV A, ECON
;ERASE Page
;WRITE Page
;VERIFY Page
;Check if ECON = 0 (OK!)
Although the 4 kbytes of Flash/EE data memory are factory pre- erased, that is, byte locations set to FFH, it is good programming practice to include an ERASEALL routine as part of any configuration/set-up code running on the devices. An ERASEALL command consists of writing 06H to the ECON SFR, which initiates an erase of the 4-kbyte Flash/EE array. This command coded in 8051 assembly language would appear as
MOV ECON, #06H ;ERASE all Command
;2ms duration
Rev. D | Page 52 of 110
Command
READPAGE WRITEPAGE VERIFYPAGE ERASEPAGE ERASEALL READBYTE WRITEBYTE
Bytes Affected
4 bytes 4 bytes 4 bytes 4 bytes 4 kbytes 1 byte
1 byte
25 machine cycles 380 μs
25 machine cycles 2ms
2 ms
10 machine cycles 200 μs
ULOAD Mode (Operating on Flash/EE Program Memory)
WRITEPAGE ERASEPAGE ERASEALL WRITEBYTE
256 bytes 64 bytes 56 kbytes 1 byte
15 ms 2 ms 2 ms 200 μs
A given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation is idled until the requested program/read or erase mode is completed. In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine-cycle MOV instruction (to write to the ECON SFR), the next instruction is not executed until the Flash/EE operation is complete. This means that the core cannot respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions such as counter/timers continue to count as configured throughout this period.
Data Sheet ADuC845/ADuC847/ADuC848
DAC CIRCUIT INFORMATION
The ADuC845/ADuC847/ADuC848 incorporate a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF, and has two selectable ranges, 0 V to VREF and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 14 (DAC) or Pin 13 (AINCOM).
DACCON Control Register
SFR Address: FDH Power-On Default: 00H Bit Addressable: No
Table 33. DACCON—DAC Configuration Commands
In 12-bit mode, the DAC voltage output is updated as soon as the DACL data SFR is written; therefore, the DAC data registers should be updated as DACH first, followed by DACL. The 12- bit DAC data should be written into DACH/L right-justified such that DACL contains the lower 8 bits, and the lower nibble of DACH contains the upper 4 bits.
Name
–––
–––
––– DACPIN
DAC8
DACRN
DACCLR
DACEN
Bit No.
7 6 5 4
3
2
1
0
Description
Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care. DAC Output Pin Select.
Set to 1 by the user to direct the DAC output to Pin 13 (AINCOM).
Cleared to 0 by the user to direct the DAC output to Pin 14 (DAC).
DAC 8-Bit Mode Bit.
Set to 1 by the user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to 0.
Cleared to 0 by the user to enable 12-bit DAC operation. In this mode, the 8 LSBs of the result are routed to DACL, and the upper 4 MSB bits are routed to the lower 4 bits of DACH.
DAC Output Range Bit.
Set to 1 by the user to configure the DAC range of 0 V to AVDD.
Cleared to 0 by the user to configure the DAC range of 0 V to 2.5 V (VREF). DAC Clear Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to reset the DAC data registers DACL/H to 0. DAC Enable Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to power down the DAC.
DACH/DACL Data Registers
These DAC data registers are written to by the user to update the DAC output.
SFR Address:
Power-On Default: Bit Addressable:
DACL (DAC data low byte)—FBH DACH (DAC data high byte)—FCH 00H (both registers)
No (both registers)
Rev. D | Page 53 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is shown in Figure 33.
VDD VDD–50mV VDD–100mV
100mV 50mV 0mV
AVDD VREF
R R R
R R
OUTPUT BUFFER
HIGH-Z DISABLE (FROM MCU)
14
000H FFFH
Figure 33. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. As shown in Figure 33, the reference source for the DAC is user-selectable in software. It can be either AVDD or VREF. In 0 V-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode, the DAC output transfer function spans from 0 V to the internal VREF (2.5 V). The DAC output buffer amplifier features a true rail-to-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both AVDD and ground. Moreover, the DAC’s linearity specification (when driving a 10 kΩ resistive load to ground) is guaranteed through the full transfer function except Codes 0 to 48 in 0 V-to-VREF mode; Codes 0 to 100; and Codes 3950 to 4095 in 0 V-to-VDD mode.
Linearity degradation near ground and VDD is caused by satura- tion of the output amplifier; a general representation of its effects (neglecting offset and gain error) is shown in Figure 34. The dotted line indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier.
Note that Figure 34 represents a transfer function in 0-to-VDD mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the ideal line to the end, showing no signs of the high-end endpoint linearity error.
Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities shown in Figure 34 become worse as a function of output loading. Most data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom, respectively, of Figure 34 become larger. With larger current demands, this can significantly limit output voltage swing. Figure 35 and Figure 36 illustrate this behavior. Note that the upper trace in each of these figures is valid only for an output range selection of 0 V to AVDD. In 0 V- to-VREF mode, DAC loading does not cause high-side voltage nonlinearities while the reference voltage remains below the upper trace in the corresponding figure. For example, if AVDD = 3 V and VREF = 2.5 V, the high-side voltage is not affected by loads of less than 5 mA. But around 7 mA, the upper curve in Figure 36 drops below 2.5 V (VREF), indicating that at these higher currents, the output is not capable of reaching VREF.
5
4
3
2
1
0
Figure 35. Source and Sink Current Capability with VREF = AVDD = 5 V
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
Rev. D | Page 54 of 110
0 5 10 15 SOURCE/SINK CURRENT (mA)
04741-035
OUTPUT VOLTAGE (V)
04741-033
04741-034
Data Sheet ADuC845/ADuC847/ADuC848
3
2
1
0
Figure 36. Source and Sink Current Capability with VREF = AVDD = 3 V
For larger loads, the current drive capability may not be suffi- cient. To increase the source and sink current capability of the DAC, an external buffer should be added as shown in Figure 37.
4
Figure 37. Buffering the DAC Output
The internal DAC output buffer also features a high impedance disable function. In the chip’s default power-on state, the DAC is disabled and its output is in a high impedance state (or three- state) where it remains inactive until enabled in software. This means that if a zero output is desired during power-on or power-down transient conditions, a pull-down resistor must be added to each DAC output. Assuming that this resistor is in place, the DAC output remains at ground potential whenever the DAC is disabled.
PULSE-WIDTH MODULATOR (PWM)
The ADuC845/ADuC847/ADuC848 has a highly flexible PWM offering programmable resolution and an input clock. The PWM can be configured in six different modes of operation. Two of these modes allow the PWM to be configured as a Σ-Δ DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 38.
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
CLOCK SELECT
0 5 10 15 SOURCE/SINK CURRENT (mA)
12.583MHz (FVCO) EXTERNAL CLOCK ON P2.7 32.768kHz (FXTAL) 32.768kHz/15
Figure 38. PWM Block Diagram
The PWM uses control SFR, PWMCON, and four data SFRs: PWM0H, PWM0L, PWM1H, and PWM1L.
PWMCON (as described in Table 34) controls the different modes of operation of the PWM as well as the PWM clock frequency. PWM0H/L and PWM1H/L are the data registers that determine the duty cycles of the PWM outputs at P2.5 and P2.6.
To use the PWM user software, first write to PWMCON to select the PWM mode of operation and the PWM input clock. Writing to PWMCON also resets the PWM counter. In any of the 16-bit modes of operation (Modes 1, 3, 4, 6), user software should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress. The values written to these 16-bit registers are then used in the next PWM cycle.
PROGRAMMABLE DIVIDER
16-BIT PWM COUNTER
COMPARE
P2.5 P2.6
MODE
PWM0H/L
PWM1H/L
ADuC845/ ADuC847/ DAC 1 ADuC848
Rev. D | Page 55 of 110
04741-037
04741-038
04741-036
OUTPUT VOLTAGE (V)
ADuC845/ADuC847/ADuC848 Data Sheet
PWMCON PWM Control SFR
SFR Address: AEH Power-On Default: 00H Bit Addressable: No
Table 34. PWMCON PWM Control SFR
Name
–––
PWM2, PWM1, PWM0
PWS1, PWS0
PWC1, PWC0
Bit No.
7
6, 5, 4
3, 2
1, 0
Description
0 0 1 0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
PWM Clock Source Divider. PWS1 PWS0
Not Implemented. Write Don’t Care. PMW Mode Selection.
PWM2 PWM1 PWM0
0 0 0
PWM disabled.
Single 16-bit output with programmable pulse and cycle time. Twin 8-bit outputs.
Twin 16-bit outputs.
Dual 16-bit pulse density outputs.
Dual 8-bit outputs.
Dual 16-bit pulse density RZ outputs.
PWM counter reset with outputs not used.
0 0
0 1
1 0
1 1
PWM Clock Source Selection. PWC1 PWC0
0 0
0 1
1 0
1 1
FXTAL/15 (2.184 kHz). FXTAL (32.768 kHz). External input on P2.7. FVCO (12.58 MHz).
Mode 0: Mode 1: Mode 2: Mode 3: Mode 4: Mode 5: Mode 6: Mode 7:
Selectedclock.
Selected clock divided by 4. Selected clock divided by 16. Selected clock divided by 64.
PWM Pulse Width High Byte (PWM0H)
SFR Address: B2H Power-On Default: 00H Bit Addressable: No
Table 35. PWM0H: PWM Pulse Width High Byte
PWM0H.7
PWM0H.0
PWM0H.6
PWM0H.5
PWM0H.4
PWM0H.3
PWM0H.2
PWM0H.1
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
00
R/W
PWM Pulse Width Low Byte (PWM0L)
SFR Address: B1H Power-On Default: 00H Bit Addressable: No
R/W
Rev. D | Page 56 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Table 36. PWM0L: PWM Pulse Width Low Byte
PWM0L.7 PWM0L.0
00 R/W R/W
PWM Cycle Width High Byte (PWM1H)
SFR Address: B4H Power-On Default: 00H Bit Addressable: No
Table 37. PWM1H: PWM Cycle Width High Byte
PWM1H.7 PWM1H.0
00 R/W R/W
PWM0L.6
PWM0L.5
PWM0L.4
PWM0L.3
PWM0L.2
PWM0L.1
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
PWM1H.6
PWM1H.5
PWM1H.4
PWM1H.3
PWM1H.2
PWM1H.1
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
PWM Cycle Width Low Byte (PWM1L)
SFR Address: B3H Power-On Default: 00H Bit Addressable: No
Table 38. PWM1L: PWM Cycle Width Low Byte
PWM1L.7
PWM1L.0
PWM1L.6
PWM1L.5
PWM1L.4
PWM1L.3
PWM1L.2
PWM1L.1
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
00
R/W
Mode 0
In Mode 0, the PWM is disabled, allowing P2.5 and P2.6 to be used as normal digital I/Os.
Mode 1 (Single-Variable Resolution PWM)
In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM. For example, setting PWM1H/L to 65536 gives a 16-bit PWM with a maximum output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L to 4096 gives a 12-bit PWM with a maximum output rate of 3072 Hz (12.583 MHz/4096).
PWM0H/L sets the duty cycle of the PWM output waveform as shown in Figure 39.
R/W
PWM1H/L PWM0H/L
0 P2.5
PWM COUNTER
Rev. D | Page 57 of 110
Figure 39. PWM in Mode 1
Mode 2 (Twin 8-Bit PWM)
In Mode 2, the duty cycle and the resolution of the PWM outputs are programmable. The maximum resolution of the PWM output is 8 bits.
PWM1L sets the period for both PWM outputs. Typically, this is set to 255 (FFH) to give an 8-bit PWM, although it is possible to reduce this as necessary. A value of 100 can be loaded here to give a percentage PWM, that is, the PWM is accurate to 1%.
04741-039
ADuC845/ADuC847/ADuC848 Data Sheet
The outputs of the PWM at P2.5 and P2.6 are shown in Figure 40. As can be seen, the output of PWM0 (P2.5) goes low when the PWM counter equals PWM0L. The output of PWM1 (P2.6) goes high when the PWM counter equals PWM1H and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously.
Mode 4 (Dual NRZ 16-Bit Σ-∆ DAC)
Mode 4 provides a high speed PWM output similar to that of a Σ-Δ DAC. Typically, this mode is used with the PWM clock equal to 12.58 MHz.
In this mode, P2.5 and P2.6 are updated every PWM clock
(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM), PWM0 (P2.5) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly, PWM1 (P2.6) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
If PWM1H is set to 4010H (slightly above one-quarter of FS), typically P2.6 is low for three clocks and high for one clock (each clock is approximately 80 ns). Over every 65536 clocks, the PWM compromises for the fact that the output should be slightly above one-quarter of full scale, by having a high cycle followed by only two low cycles.
PWM1L
PWM0H PWM0L
PWM1H 0
P2.5 P2.6
PWM COUNTER
Figure 40. PWM Mode 2
Mode 3 (Twin 16-Bit PWM)
CARRY OUT AT P2.5
PWM0H/L = C000H
111
In Mode 3, the PWM counter is fixed to count from 0 to 65536, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P2.5 and P2.6 are independently programmable.
As shown in Figure 41, while the PWM counter is less than PWM0H/L, the output of PWM0 (P2.5) is high. Once the PWM counter equals PWM0H/L, PWM0 (P2.5) goes low and remains low until the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/L, the output of PWM1 (P2.6) is high. Once the PWM counter equals PWM1H/L, PWM1 (P2.6) goes low and remains low until the PWM counter rolls over.
In this mode, both PWM outputs are synchronized, that is, once the PWM counter rolls over to 0, both PWM0 (P2.5) and PWM1 (P2.6) go high.
16-BIT
16-BIT
12.583MHz
16-BIT
16-BIT
PWM1H/L = 4000H
16-BIT
16-BIT
0 011
80s
0000
LATCH
1
CARRY OUT AT P2.6
80s Figure 42. PWM Mode 4
65536 PWM1H/L
PWM0H/L 0
P2.5 P2.6
For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write 0001 to the 4 LSBs. This means that a 12-bit accurate Σ-Δ DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate Σ-Δ DAC output at 49 kHz.
PWM COUNTER
Figure 41. PWM Mode 3
Rev. D | Page 58 of 110
04741-041
04741-040
04741-042
Data Sheet ADuC845/ADuC847/ADuC848
Mode 5 (Dual 8-Bit PWM)
In Mode 5, the duty cycle and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is 8 bits.
The output resolution is set by the PWM1L and PWM1H SFRs for the P2.5 and P2.6 outputs, respectively. PWM0L and PWM0H set the duty cycles of the PWM outputs at P2.5 and P2.6, respectively. Both PWMs have the same clock source and clock divider.
PWM1L
PWM1H PWM0L
PWM0H 0
P2.5 P2.6
CARRY OUT AT P2.5
00
318s
PWM COUNTERS
PWM0H/L = C000H
1
1
1
1
1
LATCH
Figure 43. PWM Mode 5
Mode 6 (Dual RZ 16-Bit Σ-∆ DAC)
16-BIT
16-BIT
3.146MHz
16-BIT
0, 3/4, 1/2, 1/4, 0
16-BIT
PWM1H/L = 4000H
Mode 7
16-BIT
16-BIT
CARRY OUT AT P2.6
000 000
1
Mode 6 provides a high speed PWM output similar to that of a Σ-Δ DAC. Mode 6 operates very similarly to Mode 4; however, the key difference is that Mode 6 provides return to zero (RZ) Σ-Δ DAC output. Mode 4 provides non-return-to-zero Σ-Δ DAC outputs. RZ mode ensures that any difference in the rise and fall times does not affect the Σ-Δ DAC INL. However, RZ mode halves the dynamic range of the Σ-Δ DAC outputs from 0 V− to AVDD down to 0 V to AVDD/2. For best results, this mode should be used with a PWM clock divider of 4.
If PWM1H is set to 4010H (slightly above one-quarter of FS), typically P2.6 is low for three full clocks (3 × 80 ns), high for one-half a clock (40 ns), and then low again for one-half a clock (40 ns) before repeating itself. Over every 65536 clocks, the PWM compromises for the fact that the output should be slightly above one-quarter of full scale by leaving the output high for two half clocks in four every so often.
For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write 0001 to the 4 LSBs. This means that a 12-bit accurate Σ-Δ DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate Σ-Δ DAC output at 49 kHz.
318s Figure 44. PWM Mode 6
Rev. D | Page 59 of 110
In Mode 7, the PWM is disabled, allowing P2.5 and P2.6 to be used as normal.
04741-044
04741-043
ADuC845/ADuC847/ADuC848 Data Sheet
ON-CHIP PLL (PLLCON)
The ADuC845/ADuC847/ADuC848 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when maximum core performance is not required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz. The ADC clocks are also derived from the PLL clock, with the modulator rate being the same as the crystal oscillator frequency. The control register for the PLL is called PLLCON and is described as follows.
Table 39. PLLCON PLL Control Register
The 5 V parts can be set to a maximum core frequency of 12.58 MHz (CD2...0 = 000) while at 3 V, the maximum core clock rate is 6.29 MHz (CD2...0 = 001). The CD bits should not be set to 000b on the 3 V parts.
The 3 V parts are limited to a core clock speed of 6.29 MHz (CD = 1).
PLLCON PLL Control Register
SFR Address: D7H Power-On Default: 53H Bit Addressable: No
Name
OSC_PD
LOCK
––– LTEA FINT
CD2, CD1, CD0
Bit No.
7
6
5 4 3
2, 1, 0
Description
Oscillator Power-Down Bit.
If low, the 32 kHz crystal oscillator continues running in power-down mode.
If high, the 32.768 kHz oscillator is powered down.
When this bit is low, the seconds counter continues to count in power-down mode and can interrupt the CPU to exit power-down. The oscillator is always enabled in normal mode.
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. After power- down, this bit can be polled to wait for the PLL to lock.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This might be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58 MHz ± 20%. After the device wakes up from power-down, user code can poll this bit to wait for the PLL to lock. If LOCK = 0, the PLL is not locked.
Not Implemented. Write Don’t Care.
EA Status. Read-only bit. Reading this bit returns the state of the external EA pin latched at reset or power-on. Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency. Cleared by the user to disable the fast interrupt response feature.
This function must not be used on 3 V parts.
CPU (Core Clock) Divider Bits. This number determines the frequency at which the core operates.
CD2 CD1 CD0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1 1 1 0 1 1 1
Core Clock Frequency (MHz)
12.582912. Not a valid selection on 3 V parts.
6.291456 (Maximum core clock rate allowed on the 3 V parts) 3.145728
1.572864 (Default core frequency)
0.786432
0.393216
0.196608
0.098304
On 3 V parts (ADuC84xBCPxx-3 or ADuC84xBSxx-3), the CD settings can be only CD = 1; CD = 0 is not a valid selection. If CD = 0 is selected on a 3 V part by writing to PLLCON, the instruction is ignored, and the previous CD value is retained.
The Fast Interrupt bit (FINT) must not be used on 3 V parts since it automatically sets the CD bits to 0, which is not a valid setting.
Rev. D | Page 60 of 110
Data Sheet ADuC845/ADuC847/ADuC848
I2C SERIAL INTERFACE
The ADuC845/ADuC847/ADuC848 support a fully licensed I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27 on the MQFP package and Pin 29 on the LFCSP package) is the data I/O pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the LFCSP package) is the serial interface clock for the SPI interface. The I2C interface on the devices is fully independent of all other pin/function multiplexing. The I2C interface incorporated on the ADuC845/ADuC847/ADuC848 also includes a second address register (I2CADD1) at SFR Address F2H with a default power-on value of 7FH. The I2C interface is always available to the user and is not multiplexed with any other I/O functionality on the chip. This means that the I2C and SPI interfaces can be used at the same time.
Table 40. I2CCON SFR Bit Designations
Note that when using the I2C and SPI interfaces simultaneously, they both use the same interrupt routine (Vector Address 3BH). When an interrupt occurs from one of these, it is necessary to interrogate each interface to see which one has triggered the ISR request.
The four SFRs that are used to control the I2C interface are described next.
I2CCON—I2C Control Register
SFR Address: E8H Power-On Default: 00H Bit Addressable: Yes
Name
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
Bit No.
7
6
5
4
3
2
1
0
Description
I2C Software Master Data Output Bit (master mode only).
This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on the SDATA pin if the data output enable bit (MDE) is set.
I2C Software Output Enable Bit (master mode only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx). I2C Software Master Clock Output Bit (master mode only).
This bit is used to implement the SCLK for a master I2C transmitter in software. Data written to this bit is output on the SCLK pin.
I2C Software Master Data Input Bit (master mode only).
This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on an SCLK transition if the data output enable (MDE) bit is 0.
I2C Master/Slave Mode Bit.
Set by the user to enable I2C software master mode.
Cleared by the user to enable I2C hardware slave mode. I2C Reset Bit (slave mode only).
Set by the user to reset the I2C interface.
Cleared by the user code for normal I2C operation.
I2C Direction Transfer Bit (slave mode only).
Set by the MicroConverter if the I2C interface is transmitting.
Cleared by the MicroConverter if the I2C interface is receiving.
I2C Interrupt Bit (slave mode only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared by the MicroConverter when the user code reads the I2CDAT SFR. I2CI should not be cleared by user code.
Rev. D | Page 61 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
I2CADD—I2C Address Register 1
Function:
SFR Address: Power-On Default: Bit Addressable:
Holds one of the I2C peripheral addresses for the device. It may be overwritten by user code. The uC001 Application Note describes the format of the I2C standard 7-bit address.
9BH
55H
No
I2CADD1—I2C Address Register 2
Function:
SFR Address: Power-On Default: Bit Addressable:
Same as the I2CADD. F2H
7FH
No
I2CDAT—I2C Data Register
Function:
SFR Address: Power-On Default: Bit Addressable:
The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User code should access I2CDAT only once per interrupt cycle.
9AH
00H No
The main features of the MicroConverter I2C interface are
Only two bus lines are required: a serial data line (SDATA) and a serial clock line (SCLOCK).
An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment.
The ability to respond to two separate addresses when operating in slave mode.
On-chip filtering rejects <50 ns spikes on the SDATA and the SCLOCK lines to preserve data integrity.
DVDD
Figure 45. Typical I2C System
Software Master Mode
The ADuC845/ADuC847/ADuC848 can be used as an I2C master device by configuring the I2C peripheral in master mode and writing software to output the data bit-by-bit. This is referred to as a software master. Master mode is enabled by setting the I2CM bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable the output driver on the SDATA pin. If MDE is set, the SDATA pin is pulled high or low depending on whether the MDO bit is set or cleared. MCO controls the SCLOCK pin and is always configured as an output in master mode. In master mode, the SCLOCK pin is pulled high or low depending on the whether MCO is set or cleared.
To receive data, MDE must be cleared to disable the output driver on SDATA. Software must provide the clocks by toggling the MCO bit and reading the SDATA pin via the MDI bit. If MDE is cleared, MDI can be used to read the SDATA pin. The value of the SDATA pin is latched into MDI on a rising edge of SCLOCK. MDI is set if the SDATA pin is high on the last rising edge of SCLOCK. MDI is cleared if the SDATA pin is low on the last rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to generate the start condition, slave address, acknowledge bits, data bytes, and stop conditions. These functions are described in the uC001 Application Note.
I2C MASTER
I2C SLAVE 1
I2C SLAVE 2
Rev. D | Page 62 of 110
04741-045
Data Sheet ADuC845/ADuC847/ADuC848
Hardware Slave Mode
After reset, the ADuC845/ADuC847/ADuC848 default to hardware slave mode. Slave mode is enabled by clearing the I2CM bit in I2CCON. The devices have a full hardware slave. In slave mode, the I2C address is stored in the I2CADD register. Data received or to be transmitted is stored in the I2CDAT register.
Once enabled in I2C slave mode, the slave controller waits for
a start condition. If the parts detect a valid start condition, followed by a valid address, followed by the R/W bit, then the I2CI interrupt bit is automatically set by hardware. The I2C peripheral generates a core interrupt only if the user has pre- configured the I2C interrupt enable bit in the IEIP2 SFR as well as the global interrupt bit, EA, in the IE SFR. Therefore,
When a stop condition is received, the interface resets to a state in which it is waiting to be addressed (idle). Similarly, if the interface receives a NACK at the end of a sequence, it also returns to the default idle state. The I2CRS bit can be used to reset the I2C interface. This bit can be used to force the interface back to the default idle state.
SPI SERIAL INTERFACE
The ADuC845/ADuC847/ADuC848 integrate a complete hardware serial peripheral interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. Note that the SPI pins are multiplexed with the Port 2 pins, P2.0, P2.1, P2.2, and P2.3. These pins have SPI functionality only if SPE is set. Otherwise, with SPE cleared, standard Port 2 functionality is maintained. SPI can be configured for master or slave operation and typically consists of Pins SCLOCK, MISO, MOSI, and SS.
SCLOCK (Serial Clock I/O Pin)
Pin 28 (MQFP Package), Pin 30 (LFCSP Package)
The master clock (SCLOCK) is used to synchronize the data transmitted and received through the MOSI and MISO data lines.
A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The SCLOCK pin is configured as an output in master mode and as an input in slave mode. In master mode, the bit rate, polarity, and phase of the clock are controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see Table 41). In slave mode, the SPICON register must be config- ured with the same phase and polarity (CPHA and CPOL) as the master. The data is transmitted on one edge of the SCLOCK signal and sampled on the other.
MISO (Master In, Slave Out Pin)
Pin 30 (MQFP Package), Pin 32 (LFCSP Package)
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
Pin 29 (MQFP Package), Pin31 (LFCSP Package)
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte-wide (8-bit) serial data, MSB first.
MOV IEIP2, #01h
SETB EA
;Enable I2C Interrupt
An autoclear of the I2CI bit is implemented on the devices so that this bit is cleared automatically upon read or write access to the I2CDAT SFR.
MOV I2CDAT, A
MOV A, I2CDAT
;I2CI auto-cleared
;I2CI auto-cleared
If for any reason the user tries to clear the interrupt more than once, that is, access the data SFR more than once per interrupt, the I2C controller stops. The interface then must be reset by using the I2CRS bit.
The user can choose to poll the I2CI bit or to enable the interrupt. In the case of the interrupt, the PC counter vectors to 003BH at the end of each complete byte. For the first byte, when the user gets to the I2CI ISR, the 7-bit address and the R/W bit appear in the I2CDAT SFR.
The I2CTX bit contains the R/W bit sent from the master. If I2CTX is set, the master is ready to receive a byte; therefore the slave transmits data by writing to the I2CDAT register. If I2CTX is cleared, the master is ready to transmit a byte; therefore the slave receives a serial byte. Software can interrogate the state of I2CTX to determine whether it should write to or read from I2CDAT.
Once the device has received a valid address, hardware holds SCLOCK low until the I2CI bit is cleared by software. This allows the master to wait for the slave to be ready before transmitting the clocks for the next byte.
The I2CI interrupt bit is set every time a complete data byte is received or transmitted, provided that it is followed by a valid ACK. If the byte is followed by a NACK, an interrupt is not generated.
The device continues to issue interrupts for each complete data byte transferred until a stop condition is received or the interface is reset.
Rev. D | Page 63 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
SS (Slave Select Input Pin)
Pin 31 (MQFP Package), Pin 33 (LFCSP Package)
The SS pin is used only when the ADuC845/ADuC847/ ADuC848 are configured in SPI slave mode. This line is active
low. Data is received or transmitted in slave mode only when the SS pin is low, allowing the devices to be used in single- master, multislave SPI configurations. If CPHA = 1, the SS input
can be pulled low permanently. If CPHA = 0, the SS input must be driven low before the first bit in a byte-wide transmission or
reception and must return high again after the last bit in that byte-wide transmission or reception. In SPI slave mode, the logic level on the external SS pin (Pin 31/Pin 33) can be read via the SPR0 bit in the SPICON SFR.
The SFR register in Table 41 is used to control the SPI interface.
Rev. D | Page 64 of 110
Data Sheet ADuC845/ADuC847/ADuC848
SPICON—SPI Control Register
SFR Address: F8H Power-On Default: 05H Bit Addressable: Yes
Table 41. SPICON SFR Bit Designations
Name
ISPI
WCOL
SPE
SPIM
CPOL1
CPHA1
SPR1, SPR0
Bit No.
7
6
5
4
3
2
1, 0
Description
SPI Interrupt Bit.
Set by the MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit.
Set by the MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code.
SPI Interface Enable Bit.
Set by user code to enable SPI functionality.
Cleared by user code to enable standard Port 2 functionality.
SPI Master/Slave Mode Select Bit.
Set by user code to enable master mode operation (SCLOCK is an output).
Cleared by user code to enable slave mode operation (SCLOCK is an input).
Clock Polarity Bit.
Set by user code to enable SCLOCK idle high.
Cleared by user code to enable SCLOCK idle low.
Clock Phase Select Bit.
Set by user code if the leading SCLOCK edge is to transmit data.
Cleared by user code if the trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Bits.
SPR1 SPR0
00 fcore/2
01 fcore/4
10 fcore/8
11 fcore/16
Selected Bit Rate
1 The CPOL and CPHA bits should both contain the same values for master and slave devices.
Note that both SPI and I2C use the same ISR (Vector Address 3BH); therefore, when using SPI and I2C simultaneously, it is necessary to check the interfaces following an interrupt to determine which one caused the interrupt.
SPIDAT: SPI Data Register
SFR Address: 7FH Power-On Default: 00H Bit Addressable: No
Rev. D | Page 65 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
USING THE SPI INTERFACE
Depending on the configuration of the bits in the SPICON SFR shown in Table 41, the SPI interface transmits or receives data in a number of possible modes. Figure 46 shows all possible ADuC845/ADuC847/ADuC848 SPI configurations and the timing relationships and synchronization among the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication.
SCLOCK (CPOL = 1)
SCLOCK (CPOL = 0)
SS
SAMPLE INPUT DATA OUTPUT
ISPI FLAG SAMPLE INPUT DATA OUTPUT
ISPI FLAG
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. Also note that the SS pin is not used in master mode. If the devices need to assert the SS pin on an external slave device, use a port digital output pin.
In master mode, a byte transmission or reception is initiated by a byte write to SPIDAT. The hardware automatically generates eight clock periods via the SCLOCK pin, and the data is transmitted via MOSI. With each SCLOCK period, a data bit is also sampled via MISO. After eight clocks, the transmitted byte is completely transmitted (via MOSI), and the input byte (if required) is waiting in the input shift register (after being received via MISO). The ISPI flag is set automatically, and an interrupt occurs if enabled. The value in the input shift register is latched into SPIDAT.
SPI Interface—Slave Mode
In slave mode, the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication. Trans- mission is also initiated by a write to SPIDAT. In slave mode, a data bit is transmitted via MISO, and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte is completely transmitted, and the input byte is waiting in the input shift register. The ISPI flag is set automatically, and an interrupt occurs, if enabled. The value in the shift register is latched into SPIDAT only when the trans- mission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received if CPHA = 1, or when SS returns high if CPHA = 0.
(CPHA = 1)
(CPHA = 0)
? MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
Figure 46. SPI Timing, All Modes
Rev. D | Page 66 of 110
04741-046
Data Sheet ADuC845/ADuC847/ADuC848
DUAL DATA POINTERS
The devices incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON features automatic hardware post-increment and post-decrement as well as an automatic data pointer toggle.
Table 42. DPCON SFR Bit Designations
DPCON—Data Pointer Control SFR
SFR Address: A7H Power-On Default: 00H Bit Addressable: No
Name
---- DPT
DP1m1, DP1m0
DP0m1, DP0m0
---- DPSEL
Bit No.
7 6
5, 4
3, 2
1 0
Note the following:
The Dual Data Pointer section is the only place in which main and shadow data pointers are distinguished. Whenever the DPTR is mentioned elsewhere in this data sheet, active DPTR is implied.
Only the MOVC/MOVX @DPTR instructions automatically post-increment and post-decrement the DPTR. Other MOVC/MOVX instructions, such as MOVC PC or MOVC @Ri, do not cause the DPTR to automatically post-increment and post-decrement.
To illustrate the operation of DPCON, the following code copies 256 bytes of code memory at Address D000H into XRAM, starting from Address 0000H.
Description
Not Implemented. Write Don’t Care.
Data Pointer Automatic Toggle Enable.
Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution.
DP1m1 DP1m0 0 0
0 1
1 0
1 1
Behavior of the Shadow Data Pointer
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)
Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution.
DP0m1 DP0m0 0 0
0 1
1 0
1 1
Behavior of the Main Data Pointer
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for moving 8-bit blocks to/from 16-bit devices.)
Not Implemented. Write Don’t Care. Data Pointer Select.
Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are
placed into the DPL, DPH, and DPP SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register appear in the DPL, DPH, and DPP SFRs.
Rev. D | Page 67 of 110
MOV DPTR,#0
MOV DPCON,#55H
;Main DPTR = 0
;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
MOV DPTR,#0D000H ;DPTR = D000H
MOVELOOP: CLR A
MOVC A,@A+DPTR
MOVX @DPTR,A
MOV A, DPL
JNZ MOVELOOP
;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
;Put ACC in XRAM
;Increment main DPTR
;Swap Shadow DPTR(Code)
ADuC845/ADuC847/ADuC848 Data Sheet
POWER SUPPLY MONITOR
The power supply monitor, once enabled, monitors the DVDD and AVDD supplies on the devices. It indicates when any of the supply pins drop below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the power supply monitor function, AVDD must be equal to or greater than 2.63 V. Monitor function is controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor interrupts the core by using the PSMI bit in the PSMCON SFR. This bit is not cleared until the failing power supply returns above the trip point for at least 250 ms.
The monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution does not resume until a
Table 43. PSMCON SFR Bit Designations
safe supply level is well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit.
The 5 V part has an internal POR trip level of 4.63 V, which means that there are no usable DVDD PSM trip levels on the 5 V part. The 3 V part has a POR trip level of 2.63 V following a reset and initialization sequence, allowing all relevant PSM trip points to be used.
PSMCON—Power Supply Monitor Control Register
SFR Address: DFH Power-On Default: DEH Bit Addressable: No
Name
CMPD
CMPA
PSMI
TPD1, TPD0
TPA1, TPA0
PSMEN
Bit No.
7
6
5
4, 3
2, 1
0
Description
DVDD Comparator Bit.
This read-only bit directly reflects the state of the DVDD comparator.
Read 1 indicates that the DVDD supply is above its selected trip point.
Read 0 indicates that the DVDD supply is below its selected trip point.
AVDD Comparator Bit.
This read-only bit directly reflects the state of the AVDD comparator.
Read 1 indicates that the AVDD supply is above its selected trip point.
Read 0 indicates that the AVDD supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
Set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The PSMI
bit can be used to interrupt the processor. Once CMPD and/or CMPA returns (and remains) high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
DVDD Trip Point Selection Bits.
A 5 V part has no valid PSM trip points. If the DVDD supply falls below the 4.63 V point, the device resets (POR). For a 3 V part, all relevant PSM trip points are valid. The 3 V POR trip point is 2.63 V (fixed).
These bits select the DVDD trip point voltage as follows:
TPD1 TPD0 0 0
0 1
1 0
1 1
AVDD Trip Point Selection Bits. These bits select the AVDD trip point voltage as follows:
TPA1 TPA0 0 0
0 1
1 0
Selected AVDD Trip Point (V) 4.63
3.08
2.93
Selected DVDD Trip Point (V) 4.63
3.08
2.93
2.63
1 1
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the user to disable the power supply monitor circuit.
2.63
Rev. D | Page 68 of 110
Data Sheet ADuC845/ADuC847/ADuC848
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADuC845/ADuC847/ ADuC848 enters an erroneous state, possibly due to a program- ming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR. When enabled, the watchdog circuit generates a system reset or interrupt (WDS) if the user program fails to set the WDE bit within a predetermined amount of time (see the PRE3...0 bits in Table 44). The
Table 44. WDCON SFR Bit Designations
watchdog timer is clocked from the 32 kHz external crystal connected between the XTAL1 and XTAL2 pins. The WDCOM SFR can be written only by user software if the double write sequence described in WDWR is initiated on every write access to the WDCON SFR.
WDCON—Watchdog Control Register
SFR Address: C0H Power-On Default: 10H Bit Addressable: Yes
Name
PRE3, PRE2, PRE1, PRE0
WDIR
WDS
WDE
WDWR
Bit No.
7, 6, 5, 4
Description
Watchdog Timer Prescale Bits.
The watchdog timeout period is given by the equation tWD = (2PRE × (29/ fXTAL)) (0 ≤ PRE ≤ 7; fXTAL = 32.768 kHz)
3
2
1
0
watchdog generates an interrupt response instead of a system reset when the watchdog timeout period expires. This interrupt is not disabled by the CLR EA instruction,
PRE3 PRE2 PRE1 PRE0 0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
0 1 1 1
1 0 0 0
PRE3–PRE0 > 1000b Watchdog Interrupt Response If this bit is set by the user, the
Timeout Period (ms) 15.6
31.2
62.5
125 250 500 1000 2000 0.0
Enable Bit.
Action
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Reset or interrupt
Immediate reset
Reserved. Not a valid selection.
and it is also a fixed, high priority interrupt. If the watchdog timer is not being used to monitor the system, it can be used alternatively as a timer. The prescaler is used to set the timeout period in which an interrupt is generated.
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset. Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog timeout period, the watchdog timer generates a reset or interrupt, depending on WDIR.
Cleared under the following conditions: user writes 0; watchdog reset (WDIR = 0); hardware reset; PSM interrupt.
Watchdog Write Enable Bit.
Writing data to the WDCON SFR involves a double instruction sequence. Global interrupts must first be disabled. The WDWR bit is set with the very next instruction, a write to the WDCON SFR. For example:
CLR EA ;Disable Interrupts while configuring to WDT
SETB WDWR ;Allow Write to WDCON
MOV WDCON, #72H ;Enable WDT for 2.0s timeout
SETB EA ;Enable Interrupts again (if required)
Rev. D | Page 69 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
TIME INTERVAL COUNTER (TIC)
A TIC is provided on-chip for counting longer intervals than the standard 8051-compatible timers can count. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Also, this counter is clocked by the external 32.768 kHz crystal rather than by the core clock, and it can remain active in power-down mode and time long power-down intervals. This has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. Note that instructions to the TIC SFRs are also clocked at 32.768 kHz, so sufficient time must be allowed in user code for these instructions to execute.
Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow clocks the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt, if enabled. If the device is in power-down mode, again with TIC interrupt enabled, the TII bit wakes up the device and resumes code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC-related SFRs are described in Table 45. Note also that the time based SFRs can be written initially with the current time; the TIC can then be controlled and accessed by user software. In effect, this facilitates the implementation of a real-time clock. A basic block diagram of the TIC is shown in Figure 47.
Because the TIC is clocked directly from a 32 kHz external crystal on the devices, instructions that access the TIC registers are also clocked at 32 kHz (not at the core frequency). The user must ensure that sufficient time is given for these instructions to execute.
TCEN
32.768kHz EXTERNAL CRYSTAL
ITS0 ITS1
8-BIT PRESCALER
HUNDREDTHS COUNTER HTHSEC
INTERVAL
TIMEBASE SELECTION MUX
TIEN
SECOND COUNTER SEC
MINUTE COUNTER MIN
HOUR COUNTER HOUR
8-BIT INTERVAL COUNTER
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
EQUAL?
Rev. D | Page 70 of 110
Figure 47. TIC Simplified Block Diagram
INTVAL SFR
04741-047
Data Sheet ADuC845/ADuC847/ADuC848
TIMECON—TIC Control Register
SFR Address: A1H Power-On Default: 00H Bit Addressable: No
Table 45. TIMECON SFR Bit Designations
Name
—- TFH
ITS1, ITS0
ST1
TII
TIEN
TCEN
Bit No.
7 6
5, 4
3
2
1
0
Description
Not Implemented. Write Don’t Care.
Twenty-Four Hour Select Bit.
Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to enable the hour counter to count from 0 to 255. Interval Timebase Selection Bits.
ITS1 ITS0 0 0
0 1
1 0
Interval Timebase 1/128 Second Seconds
Minutes
1 1
Single Time Interval Bit.
Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit.
Cleared by the user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout.
TIC Interrupt Bit.
Set when the 8-bit interval counter matches the value in the INTVAL SFR.
Cleared by user software.
Time Interval Enable Bit.
Set by the user to enable the 8-bit time interval counter.
Cleared by the user to disable the interval counter.
Time Clock Enable Bit.
Set by the user to enable the time clock to the time interval counters.
Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is low.
Hours
Rev. D | Page 71 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
INTVAL—User Timer Interval Select Register
Function:
SFR Address: Power-On Default: Bit Addressable: Valid Value:
User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt, if enabled.
A6H
00H
No
0 to 255 decimal
HTHSEC—Hundredths of Seconds Time Register
Function:
SFR Address: Power-On Default: Bit Addressable: Valid Value:
This register is incremented in 1/128-second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register.
A2H
00H
No
0 to 127 decimal
SEC—Seconds Time Register
Function:
SFR Address: Power-On Default: Bit Addressable: Valid Value:
This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register.
A3H
00H
No
0 to 59 decimal
MIN—Minutes Time Register
Function
SFR Address: Power-On Default: Bit Addressable: Valid Value:
This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN SFR counts from 0 to 59 before rolling over to increment the HOUR time register.
A4H
00H
No
0 to 59 decimal
HOUR—Hours Time Register
Function:
SFR Address: Power-On Default: Bit Addressable: Valid Value:
This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0.
A5H
00H
No
0 to 23 decimal
To enable the TIC as a real-time clock, the HOUR, MIN, SEC, and HTHSEC registers can be loaded with the current time. Once the TCEN bit is high, the TIC starts. To use the TIC as a time interval counter, select the count interval—hundredths of seconds, seconds, minutes, and hours via the ITS0 and ITS1 bits in the TIMECON SFR. Load the count required into the INTVAL SFR.
Note that INTVAL is only an 8-bit register, so user software must take into account any intervals longer than are possible with 8 bits. Therefore, to count an interval of 20 seconds, use the following procedure:
MOV TIMECON, #0D0H ;Enable 24Hour mode, count seconds, Clear TCEN.
MOV INTVAL, #14H ;Load INTVAL with required count interval…in this case 14H = 20
MOV TIMECON, #0D3H ;Start TIC counting and enable the 8bit INTVAL counter.
Rev. D | Page 72 of 110
Data Sheet ADuC845/ADuC847/ADuC848
8052-COMPATIBLE ON-CHIP PERIPHERALS
This section gives a brief overview of the various secondary peripheral circuits that are available to the user on-chip. These features are mostly 8052-compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions.
Parallel I/O
The ADuC845/ADuC847/ADuC848 use four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of external memory operations, while others are multiplexed with alternate functions for the peripheral functions available on-chip. In general, when a peripheral is enabled, that pin cannot be used as a general-purpose I/O pin.
Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port that is directly controlled via the Port 0 SFR (80H). Port 0 is also the multiplexed low-order address and data bus during accesses to external data memory.
Figure 48 shows a typical bit latch and I/O buffer for a Port 0 pin. The bit latch (one bit in the SFRof the port) is represented as a Type D flip-flop, which clocks in a value from the internal bus in response to a write to latch signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in response to a read latch signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU. Some instructions that read a port activate the read latch signal, and others activate the read pin signal. See the Read-Modify-Write Instructions section for details.
In general-purpose I/O port mode, Port 0 pins that have 1s written to them via the Port 0 SFR are configured as open-drain and, therefore, float. In this state, Port 0 pins can be used as high impedance inputs. This is represented in Figure 48 by the NAND gate whose output remains high as long as the control signal is low, thereby disabling the top FET. External pull-up resistors are, therefore, required when Port 0 pins are used as general-purpose outputs. Port 0 pins with 0s written to them drive a logic low output voltage (VOL) and are capable of sinking 1.6 mA.
Port 1
Port 1 is also an 8-bit port directly controlled via the P1 SFR (90H). Port 1 digital output capability is not supported on this device. Port 1 pins can be configured as digital inputs or analog inputs. By (power-on) default, these pins are configured as analog inputs, that is, 1 is written to the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a 0 to these port bits to configure the corre- sponding pin as a high impedance digital input. These pins also have various secondary functions aside from their analog input capability, as described in Table 46.
Table 46. Port 1 Alternate Functions
Pin No.
P1.2 P1.3 P1.6 P1.7
Port 2
Alternate Function
REFIN2+ (second reference input, postive) REFIN2− (second reference input, negative) IEXC1 (200 μA excitation current source) IEXC2 (200 μA excitation current source)
ADDR/DATA CONTROL
LATCH
DVDD
READ LATCH
INTERNAL BUS
WRITE TO LATCH
READ PIN
READ LATCH
INTERNAL BUS
WRITE TO LATCH
READ PIN
P0.x PIN
LATCH
P1.x TO ADC PIN
Rev. D | Page 73 of 110
DQ CL Q
DQ CL Q
Figure 49. Port 1 Bit Latch and I/O Buffer
Figure 48. Port 0 Bit Latch and I/O Buffer
Port 2 is a bidirectional port with internal pull-up resistors directly controlled via the P2 SFR. Port 2 also emits the middle- and high-order address bytes during accesses to the 24-bit external data memory space.
In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups as shown in Figure 50 and, in that state, can be used as inputs. As inputs, Port 2 pins pulled externally low source current because of the internal pull-up resistors. Port 2 pins with 0s written to them drive a logic low output voltage (VOL) and are capable of sinking 1.6 mA.
As shown in Figure 48, the output drivers of Port 0 pins are switchable to an internal ADDR and ADDR/DATA bus by an internal control signal for use in external memory accesses. During external memory accesses, the P0 SFR has 1s written to it; therefore, all its bit latches become 1. When accessing external memory, the control signal in Figure 48 goes high, enabling push-pull operation of the output pin from the internal address or data bus (ADDR/DATA line). Therefore, no external pull- ups are required on Port 0 for it to access external memory.
04741-048
04741-068
ADuC845/ADuC847/ADuC848 Data Sheet
P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can act as an alternate PWM clock source. When selected as the PWM outputs, they overwrite anything written to P2.5 or P2.6.
ALTERNATE READ OUTPUT
DVDD
INTERNAL PULL-UP
LATCH
INTERNAL BUS
WRITE TO LATCH
FUNCTION
P3.x PIN
DQ CL Q
Table 47. Port 2 Alternate Functions
Pin No.
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
INTERNAL BUS
WRITE TO LATCH
READ PIN
Port 3
Alternate Function
SCLOCK for SPI
MOSI for SPI
MISO for SPI
SS and T2 clock input
T2EX alternate control for T2 PWM0 output
PWM1 output PWMCLK
ADDR CONTROL
LATCH
LATCH
READ
PIN ALTERNATE
INPUT FUNCTION
Figure 51. Port 3 Bit Latch and I/O Buffer
Read-Modify-Write Instructions
READ LATCH
DVDD DVDD
Some 8051 instructions read the latch while others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and rewrite it to the latch. These are called read-modify-write instructions, which are listed in Table 49. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin.
Table 49. Read-Modify-Write Instructions
Instruction Description
INTERNAL PULL-UP
P2.x PIN
DQ CL Q
Figure 50. Port 2 Bit Latch and I/O Buffer
ANL ORL XRL JBC
CPL INC DEC DJNZ
MOV PX.Y, C1 CLR PX.Y1
Logical AND, for example, ANL P1, A
Logical OR, for example, ORL P2, A
Logical EX-OR, for example, XRL P3, A
Jump if Bit = 1 and clear bit, for example, JBC P1.1, LABEL
Complement bit, for example, CPL P3.0 Increment, for example, INC P2 Decrement, for example, DEC P2
Decrement and jump if not zero, for example, DJNZ P3, LABEL
Move Carry to Bit Y of Port X
Clear Bit Y of Port X
Port 3 is a bidirectional port with internal pull-ups directly controlled via the P3 SFR (B0H). Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and, in that state, can be used as inputs. As inputs, Port 3 pins pulled externally low source current because of the internal pull-ups.
Port 3 pins with 0s written to them drive a logic low output voltage (VOL) and are capable of sinking 4 mA. Port 3 pins also have various secondary functions as described in Table 48. The alternate functions of Port 3 pins can be activated only if the corresponding bit latch in the P3 SFR contains a 1. Otherwise, the port pin remains at 0.
Table 48. Port 3 Alternate Functions
SETB PX.Y1 ___________________________________________
SetBitYofPortX
Pin No.
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Alternate Function
RxD (UART input pin, or serial data I/O in Mode 0)
TxD (UART output pin, or serial clock output in Mode 0) INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
T0 (Timer/Counter 0 external input)
T1 (Timer/Counter 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
1 These instructions read the port byte (all 8 bits), modify the addressed bit, and write the new byte back to the latch.
Read-modify-write instructions are directed to the latch rather than to the pin to avoid a possible misinterpretation of the voltage level of a pin. For example, a port pin might be used to drive the base of a transistor. When 1 is written to the bit, the transistor is turned on. If the CPU reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as Logic 0. Reading the latch rather than the pin returns the correct value of 1.
Rev. D | Page 74 of 110
04741-069
04741-071
Data Sheet ADuC845/ADuC847/ADuC848
TIMERS/COUNTERS
The ADuC845/ADuC847/ADuC848 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three can be configured to operate either as timers or as event counters.
When functioning as a timer, the TLx register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency.
When functioning as a counter, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin:
TMOD—Timer/Counter 0 and 1 Mode Register
SFR Address: 89H Power-On Default: 00H Bit Addressable: No
Table 50. TMOD SFR Bit Designation
T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input signal, but, to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. User configuration and control of all timer operating modes is achieved via three SFRs:
TMOD, TCON—Control and Configuration for Timers 0 and 1 T2CON—Control and Configuration for Timer 2.
Name
Gate
C/T
M1, M0
Gate
C/T
M1, M0
Bit No.
7
6
5, 4
3
2
1, 0
Description
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select Bits.
M1 M0
0 0
0 1
1 0
1 1
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
Timer 0 Mode Select Bits.
Description
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows.
Timer/Counter 1 Stopped.
M1 M0 0 0
0 1
1 0
1 1
Description
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows.
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
Rev. D | Page 75 of 110
ADuC845/ADuC847/ADuC848 Data Sheet
TCON—Timer/Counter 0 and 1 Control Register
SFR Address: 88H Power-On Default: 00H Bit Addressable: Yes
Table 51. TCON SFR Bit Designations
Name
TF1
TR1
TF0
TR0
IE11
IT11
IE01
IT01
Bit No.
7
6
5
4
3
2
1
0
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the
state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on the statue of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition- activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level.
1 These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined into a single 16-bit register, depending on the timers’ mode configuration.
TH0 and TL0—Timer 0 high and low bytes.
SFR Address: 8CH and 8AH, respectively. Power-On Default: 00H and 00H, respectively.
TH1 and TL1—Timer 1 high and low bytes.
SFR Address: 8DH and 8BH, respectively. Power-On Default: 00H and 00H, respectively.
Rev. D | Page 76 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 52 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single-cycle core.
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 54. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
C/T = 0
C/T = 1
TR0
INTERRUPT
C/T = 0
C/T = 1
TR0
P3.4/T0
GATE
P3.2/INT0 NOTES
CONTROL
INTERRUPT
P3.4/T0
GATE P3.2/IN T0
CONTROL
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 52. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag, TF0. TF0 can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to be controlled by external input INT0 to facilitate pulse- width measurements. TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in Figure 53.
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 54. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 55. TL0 uses the Timer 0 Control Bits C/T, Gate, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Therefore, TH0 then controls the Timer 1 interrupt. Mode 3
is provided for applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or it can still be used by the serial interface as a baud rate generator. In fact, it can be used in any application not requiring an interrupt from Timer 1 itself.
CORE CLK/12
C/T = 0
C/T = 1
C/T=0
C/T=1
INTERRUPT
INTERRUPT
TL0 (8 BITS)
TH0 (8 BITS)
INTERRUPT
P3.4/T0
GATE
P3.2/INT0
CORE CLK/12
TR1
CONTROL
TR0
P3.4/T0
GATE
P3.2/INT0
TR0
CONTROL
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 53. Timer/Counter 0, Mode 1
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Rev. D | Page 77 of 110
CORE CLK1
Figure 55. Timer/Counter 0, Mode 3
TL0 (8 BITS)
TF0
CORE CLK1
TL0 (5 BITS)
TH0 (8 BITS)
TF0
CORE CLK1
RELOAD TH0 (8 BITS)
CORE CLK1
TL0
(8 BITS)
TF0
TF0
TH0 (8 BITS)
TF1
04741-052
04741-050 04741-049
04741-051
ADuC845/ADuC847/ADuC848 Data Sheet
T2CON—Timer/Counter 2 Control Register
SFR Address: C8H Power-On Default: 00H Bit Addressable: Yes
Table 52. T2CON SFR Bit Designations
Name
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
Bit No.
7
6
5
4
3
2
1
0
Description
Timer 2 Overflow Flag.
Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1.
Cleared by user software.
Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
Cleared by user software.
Receive Clock Enable Bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3.
Cleared by the user to enable Timer 1 overflow to be used for the receive clock.
Transmit Clock Enable Bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3.
Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.
Timer 2 External Enable Flag.
Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being
used to clock the serial port.
Cleared by the user for Timer 2 to ignore events at T2EX.
Timer 2 Start/Stop Control Bit.
Set by the user to start Timer 2.
Cleared by the user to stop Timer 2.
Timer 2 Timer or Counter Function Select Bit.
Set by the user to select the counter function (input from external T2 pin).
Cleared by the user to select the timer function (input from on-chip core clock).
Timer 2 Capture/Reload Select Bit.
Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and as timer capture/reload registers.
TH2 and TL2—Timer 2 data high byte and low byte. SFR Address: CDH and CCH respectively. Power-On Default: 00H and 00H, respectively.
RCAP2H and RCAP2L—Timer 2 capture/reload byte and low byte.
SFR Address: CBH and CAH, respectively. Power-On Default: 00H and 00H, respectively.
Rev. D | Page 78 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 53.
16-Bit Capture Mode
Capture mode has two options that are selected by Bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into Registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Capture mode is shown in Figure 57. The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1.
In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur, so they do not have to be disabled. In this mode, the EXF2 flag can, however, still cause interrupts, which can be used as a third external interrupt. Baud rate generation is described as part of the UART serial port operation in the following section.
Table 53. T2CON Operating Modes
RCLK (or) TCLK
Mode
CAP2
TR2
0 1 X X
1 1 1 0
0 16-BitAutoreload
0 1 X
16-Bit Autoreload Mode
16-Bit Capture Baud Rate
Off
Autoreload mode has two options that are selected by bit EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input T2EX also triggers the 16-bit reload and sets EXF2. Autoreload mode is shown in Figure 56.
CORE CLK1
TL2 (8 BITS)
TH2 (8 BITS)
T2 PIN
T2EX PIN
C/T2 = 0
C/T2 = 1
CONTROL
TR2
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H
TF2 EXF2
TIMER INTERRUPT
CONTROL EXEN2
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 56. Timer/Counter 2, 16-Bit Autoreload Mode
CORE CLK1
TL2 (8 BITS)
TH2 (8 BITS)
TF2
T2 PIN
T2EX PIN
C/T2 = 0
C/T2 = 1
CONTROL
TR2
CAPTURE
TRANSITION DETECTOR
TIMER INTERRUPT
RCAP2L
RCAP2H
EXF2
CONTROL EXEN2
*NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 57. Timer/Counter 2, 16-Bit Capture Mode
Rev. D | Page 79 of 110
04741-054
04741-053
ADuC845/ADuC847/ADuC848 Data Sheet
UART SERIAL INTERFACE
The serial port is full duplex, meaning that it can transmit and receive simultaneously. It is also receive buffered, meaning that it can begin receiving a second byte before a previously received byte is read from the receive register. However, if the first byte is still not read by the time reception of the second byte is complete, the first byte is lost. The physical interface to the serial data network is via Pins RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART comprises SBUF and SCON, as described in this section.
Table 54. SCON SFR Bit Designations
SBUF SFR
Both the serial port receive and transmit registers are accessed through the SBUF SFR (SFR address = 99H). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
SCON UART—Serial Port Control Register
SFR Address: 98H Power-On Default: 00H Bit Addressable: Yes
Name
SM0, SM1
SM2
REN TB8
RB8 TI
RI
Bit No.
7, 6
5
4 3
2 1
0
Description
UART Serial Mode Select Bits. These bits select the serial port operating mode as follows:
SM0 SM1 0 0
0 1
1 0
Selected Operating Mode.
Mode 0: Shift register, fixed baud rate (Core_Clk/2).
Mode 1: 8-bit UART, variable baud rate.
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16). Mode 3: 9-bit UART, variable baud rate.
1 1
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received.
In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data is received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. Cleared by user software to disable serial port reception.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
SBUF—UART Serial Port Data Register
SFR Address: 99H Power-On Default: 00H Bit Addressable: No
Rev. D | Page 80 of 110
Data Sheet ADuC845/ADuC847/ADuC848
Mode 0 (8-Bit Shift Register Mode)
Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared, the data is clocked into the RxD line, and the clock pulses are output from the TxD line as shown in Figure 58.
All of the following conditions must be met at the time the final shift pulse is generated:
RI=0
EitherSM2=0orSM2=1
Received stop bit = 1
If any of these conditions is not met, the received frame is irretrievably lost, and RI is not set.
Mode 2 (9-Bit UART with Fixed Baud Rate)
Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by default, although by setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received: a start bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1). The 9th bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required.
To transmit, the 8 data bits must be written into SBUF. The ninth bit must be written to TB8 in SCON. When transmission is initiated, the 8 data bits (from SBUF) are loaded into the transmit shift register (LSB first). The contents of TB8 are loaded into the 9th bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The TI flag is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The 8 data bytes are input at RxD (LSB first) and loaded onto the receive shift register. When all 8 bits have been clocked in, the following events occur:
The 8 bits in the receive shift register are latched into SBUF.
The 9th data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
All of the following conditions must be met at the time the final shift pulse is generated:
RI=0
EitherSM2=0orSM2=1
Received stop bit = 1
If any of these conditions is not met, the received frame is irretrievably lost, and RI is not set.
RxD (DATA OUT)
TxD (SHIFT CLOCK)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
Figure 58. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore, 10 bits are transmitted on TxD or are received on RxD. The baud rate is set by the Timer 1 or Timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception).
Transmission is initiated by writing to SBUF. The write to SBUF signal also loads a 1 (stop bit) into the 9th bit position of the transmit shift register. The data is output bit-by-bit until the stop bit appears on TxD and the transmit interrupt flag (TI) is automatically set as shown in Figure 59.
START
BIT D0 D1 D2 D3 D4 D5 D6 D7
STOP BIT
TxD
TI (SCON.1)
SET INTERRUPT
I.E., READY FOR MORE DATA
Figure 59. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming that a valid start bit is detected, character reception continues. The start bit is skipped and the 8 data bits are clocked into the serial port shift register. When all 8 bits have been clocked in, the following events occur:
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
Rev. D | Page 81 of 110
04741-056
04741-055
ADuC845/ADuC847/ADuC848 Data Sheet
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The opera- tion of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
CoreClock Frequency Mode 0 Baud Rate = 12
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock:
2SMOD
Mode 2 Baud Rate = 32 × Core Clock Frequency
Modes 1 and 3 Baud Rate Generation
The baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or in both (one for transmit and the other for receive).
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows:
The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the formula
Modes1and3BaudRate= 2SMODCoreClockFrequency 32 (256 TH1)
Timer 2 Generated Baud Rates
Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible.
1
Modes 1 and 3 Baud Rate = 16 × Timer 2 Overflow Rate
Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible.
Timer 2 is selected as the baud rate generator by setting the TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 60.
In this case, the baud rate is given by the formula
Modes 1 and 3 Baud Rate = Core Clock Frequency
16 65536 RCAP 2H : RCAP 2L TIMER 1
Modes 1 and 3 Baud Rate =
T2 PIN
T2EX PIN
2SMOD 32
× Timer 1 Overflow Rate
OVERFLOW
1
TCLK
2
CORE CLK1
CONTROL
TR2
SMOD
C/T2 = 0 C/T2 = 1
TIMER 2 OVERFLOW
RELOAD
1
0
RX CLOCK
TX CLOCK
10
RCLK 16
16
RCAP2L
RCAP2H
EXF 2
TIMER 2 INTERRUPT
TRANSITION DETECTOR
CONTROL EXEN2
NOTES
1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 60. Timer 2, UART Baud Rates
Rev. D | Page 82 of 109
0
TL2 (8 BITS)
TH2 (8 BITS)
04741-057
Data Sheet ADuC845/ADuC847/ADuC848
Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high speed baud rates are not always possible. Also, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the UART is required. To address this problem, the ADuC845/ADuC847/ADuC848 have a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. Timer 3 can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400. Timer 3 also allows a much wider range of baud rates to be obtained. In fact, every desired bit rate from 12 bps to 393216 bps can be generated to within an error of ±0.8%. Timer 3 also frees up the other three timers, allowing them to be used for different applications. A block diagram of Timer 3 is shown in Figure 61.
The appropriate value to write to the DIV2-1-0 bits can be calculated using the following formula where fCORE is defined in PLLCON SFR. Note that the DIV value must be rounded down.
log DIV=
16 Baud Rate
Core Clock Frequency
CORE CLK
FRACTIONAL DIVIDER
TIMER 1/TIMER 2 Tx CLOCK
T3FD is the fractional divider ratio required to achieve the required baud rate. The appropriate value for T3FD can be calculated with the following formula:
T3FD= 2CoreClockFrequency−64 2DIV 1 Baud Rate
Note that T3FD should be rounded to the nearest integer. Once the values for DIV and T3FD are calculated, the actual baud rate can be calculated with the following formula:
ActualBaudRate= 2CoreClockFrequency
log (2)
(1 + T3FD/64)
2DIV
TIMER 1/TIMER 2 Rx CLOCK
10
10
DIV 1
For example, to get a baud rate of 9600 while operating at a core
(T3FD 64) clock frequency of 1.5725 MHz, that is, CD = 3,
2
16
T3 Rx/Tx
CLOCK
Rx CLOCK
T3EN
Tx CLOCK
DIV = log(1572500/(16 × 9600))/log2 = 3.35 = 3 Note that the DIV result is rounded down.
T3FD = (2 × 1572500)/(23−1 × 9600) − 64 = 18 = 12H Therefore, the actual baud rate is 9588 bps, which gives an error
of 0.12%.
The T3CON and T3FD registers are used to control Timer 3.
T3CON – Timer 3 Control Register
SFR Address: 9EH Power-On Default: 00H Bit Addressable: No
Figure 61. Timer 3, UART Baud Rate
Two SFRs (T3CON and T3FD) are used to control Timer 3. T3CON is the baud rate control SFR, allowing Timer 3 to be used to set up the UART baud rate, and to set up the binary divider (DIV).
Rev. D | Page 83 of 109
04741-058
ADuC845/ADuC847/ADuC848 Data Sheet
Table 55. T3CON SFR Bit Designations
Name
T3BAUDEN
DIV2, DIV1, DIV0
Bit No.
7
6
5
4
3
2, 1, 0
Description
T3UARTBAUD Enable.
Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are ignored. Cleared to let the baud rate be generated as per a standard 8052.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care.
Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care. Binary Divider
DIV2 DIV1 DIV0
0 0 0 0 0 1
0 1
1 0
1 0 1 1
0 1 0 1 0 1 0
Binary Divider 0. See Table 57. Binary Divider 1. See Table 57. Binary Divider 2. See Table 57. Binary Divider 3. See Table 57. Binary Divider 4. See Table 57. Binary Divider 5. See Table 57. Binary Divider 6. See Table 57.
T3FD—Timer 3 Fractional Divider Register
See Table 57 for values.
SFR Address: 9DH Power-On Default: 00H Bit Addressable: No
Table 56. T3FD SFR Bit Designations
Bit No.
7 6 5 4 3 2 1 0
Description
Not Implemented. Write Don’t Care. Not Implemented. Write Don’t Care. Timer 3 Fractional Divider Bit 5. Timer 3 Fractional Divider Bit 4. Timer 3 Fractional Divider Bit 3. Timer 3 Fractional Divider Bit 2. Timer 3 Fractional Divider Bit 1. Timer 3 Fractional Divider Bit 0.
Name
—-
—- T3FD.5 T3FD.4 T3FD.3 T3FD.2 T3FD.1 T3FD.0
Rev. D | Page 84 of 109
Data Sheet ADuC845/ADuC847/ADuC848
Table 57. Common Baud Rates Using Timer 3 with a 12.58 MHz PLL Clock
Ideal Baud
% Error
CD
DIV
T3CON
T3FD
0
0 1
0 1 2
0 1 2 3
0 1 2 3 4
0 1 2 3 4 5
1
2 1
3 2 1
4 3 2 1
5 4 3 2 1
6 5 4 3 2 1
81H
82H 81H
83H 82H 81H
84H 83H 82H 81H
85H 84H 83H 82H 81H
86H 85H 84H 83H 82H 81H
2DH
2DH 2DH
2DH 2DH 2DH
12H 12H 12H 12H
12H 12H 12H 12H 12H
12H 12H 12H 12H 12H 12H
230400 0.18
115200 0.18 115200 0.18
57600 0.18 57600 0.18 57600 0.18
38400 0.12 38400 0.12 38400 0.12 38400 0.12
19200 0.12 19200 0.12 19200 0.12 19200 0.12 19200 0.12
9600 0.12 9600 0.12 9600 0.12 9600 0.12 9600 0.12 9600 0.12
Rev. D | Page 85 of 109
ADuC845/ADuC847/ADuC848 Data Sheet
INTERRUPT SYSTEM
The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs:
IE Interrupt Enable Register
IP Interrupt Priority Register
IEIP2 Secondary Interrupt Enable Register
IE—Interrupt Enable Register
SFR Address: A8H Power-On Default: 00H Bit Addressable: Yes
Table 58. IE SFR Bit Designations
Name
EA EADC ET2 ES ET1 EX1 ET0 EX0
Bit No.
7 6 5 4 3 2 1 0
IP—Interrupt Priority Register
SFR Address: B8H Power-On Default: 00H Bit Addressable: Yes
Table 59. IP SFR Bit Designations
Bit No.
7 6 5 4 3 2 1 0
Description
Not Implemented. Write Don’t Care.
ADC Interrupt Priority (1 = High; 0 = Low).
Timer 2 Interrupt Priority (1 = High; 0 = Low).
UART Serial Port Interrupt Priority (1 = High; 0 = Low). Timer 1 Interrupt Priority (1 = High; 0 = Low).
INT0 (External Interrupt 1) priority (1 = High; 0 = Low). Timer 0 Interrupt Priority (1 = High; 0 = Low).
INT0 (External Interrupt 0) Priority (1 = High; 0 = Low).
Description
Set by the user to enable all interrupt sources.
Cleared by the user to disable all interrupt sources.
Set by the user to enable the ADC interrupt.
Cleared by the user to disable the ADC interrupt.
Set by the user to enable the Timer 2 interrupt.
Cleared by the user to disable the Timer 2 interrupt.
Set by the user to enable the UART serial port interrupt. Cleared by the user to disable the UART serial port interrupt. Set by the user to enable the Timer 1 interrupt.
Cleared by the user to disable the Timer 1 interrupt.
Set by the user to enable External Interrupt 1 (INT0).
Cleared by the user to disable External Interrupt 1 (INT0). Set by the user to enable the Timer 0 interrupt.
Cleared by the user to disable the Timer 0 interrupt.
Set by the user to enable External Interrupt 0 (INT0).
Cleared by the user to disable External Interrupt 0 (INT0).
Name
—– PADC PT2 PS PT1 PX1 PT0 PX0
Rev. D | Page 86 of 109
Data Sheet ADuC845/ADuC847/ADuC848
IEIP2—Secondary Interrupt Enable Register
SFR Address: A9H Power-On Default: A0H Bit Addressable: No
Table 60. IEIP2 Bit Designations
Name
—- PTI PPSM PSI —- ETI
EPSMI ESI
Bit No.
7 6 5 4 3 2
1 0
Description
Not Implemented. Write Don’t Care.
Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low). Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low). SPI/I2C Interrupt Priority Setting (1 = High, 0 = Low).
This bit must contain 0.
Set by the user to enable the time interval counter interrupt. Cleared by the user to disable the time interval counter interrupt. Set by the user to enable the power supply monitor interrupt. Cleared by the user to disable the power supply monitor interrupt. Set by the user to enable the SPI/I2C serial port interrupt.
Cleared by the user to disable the SPI/I2C serial port interrupt.
INTERRUPT PRIORITY
The interrupt enable registers are written by the user to enable individual interrupt sources; the interrupt priority registers allow the user to select one of two priority levels for each interrupt. A high priority interrupt can interrupt the service routine of a low priority interrupt, and if two interrupts of different priorities occur at the same time, the higher level interrupt is serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in Table 61, is observed.
Table 61. Priority within Interrupt Level
Source Description
PSMI Power Supply Monitor Interrupt WDS Watchdog Timer Interrupt
IE0 External Interrupt 0
RDY0/RDY1 ADC Interrupt
TF0 Timer/Counter 0 Interrupt IE1 External Interrupt 1
TF1 Timer/Counter 1 Interrupt ISPI/I2CI SPI/I2C Interrupt
RI/TI UART Serial Port Interrupt TF2/EXF2 Timer/Counter 2 Interrupt
TII Timer Interval Counter Interrupt
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are shown in Table 62.
Table 62. Interrupt Vector Addresses
Source
Vector Address
IE0 0003H TF0 000BH IE1 0013H TF1 001BH
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADuC845 only) ISPI/I2CI
PSMI
TII
WDS
0023H 002BH 0033H 003BH 0043H 0053H 005BH
Priority
1 (Highest) 2
2
3
4
5
6
7
8
9
11 (Lowest)
Rev. D | Page 87 of 109
ADuC845/ADuC847/ADuC848 Data Sheet
HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC845/ADuC847/ADuC848 into any hardware system.
EXTERNAL MEMORY INTERFACE
In addition to their internal program and data memories, the devices can access up to 16 Mbytes of external data memory (SRAM). No external program memory access is available.
To begin executing code, tie the EA (external access) pin high. When EA is high (pulled up to VDD—see Figure 70), user
program execution starts at Address 0 in the internal 62-kbyte Flash/EE code space. When executing from internal code space, accesses to the program space above F7FFH (62 kbytes) are read as NOP instructions.
Note that a second very important function of the EA pin is described in the Single-Pin Emulation Mode section under the Other Hardware Considerations section.
Figure 62 shows a hardware configuration for accessing up to 64 kbytes of external data memory. This interface is standard to any 8051-compatible MCU.
In either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL) as an address, which is latched by ALE prior to data being placed on the bus by the devices (write operation) or the external data memory (read operation). Port 2 (P2) provides the data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the SRAM, and the 8051 standard of 64-kbyte external data memory access is maintained.
The following example shows the code used to write data to external data memory.
MOV DPP, #10h ;Set addr to 100000h
MOV DPH, #00h
MOV DPL, #00h
MOV A, #’B’ ;Write Char ‘B’ (42h)
MOVX @DPTR,A ;Move to DPP:DPH:DPL addr
POWER SUPPLIES
The operational power supply voltage range of the device is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V and 4.75 V to 5.25 V (±5% of the nominal 5 V level), the chip functions equally well at any power supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of the noisy digital signals often present on a system DVDD line. In this mode, the device can also operate with split supplies, that is, using different voltage supply levels for each supply. For example, the system can be designed to operate with a DVDD voltage level of 3 V and the AVDD level can be at 5 V, or vice versa, if required. A typical split-supply configuration is shown in Figure 64.
ADuC845/ ADuC847/ ADuC848 P0
ALE
P2
RD WR
SRAM
D0–D7 (DATA)
A0–A7
A8–A15
OE WE
LATCH
Figure 62. External Data Memory Interface (64-kbyte Address Space)
DIGITAL SUPPLY
ANALOG SUPPLY
10F
+–
0.1F
5
AGND
6
If access to more than 64 kbytes of RAM is desired, a feature 10F
unique to the MicroConverter allows addressing up to 16 Mbytes +– ofexternalRAMsimplybyaddinganotherlatchasshownin6DVDDAVDD4 Figure 63.
0.1
As an alternative to providing two separate power supplies, AVDD can be kept quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 65. In this configuration, other analog circuitry (such
22
1 23
ADuC845/ ADuC847/ ADuC848
3
F
5
ADuC845/ ADuC847/ P0 ADuC848
ALE P2
RD WR
SRAM
D0–D7 (DATA)
A0–A7
A8–A15 A16–A23
OE WE
37 DGND 38
50
LATCH
Figure 64. External Dual-Supply Connections (56-Lead LFCSP Pin Numbering)
LATCH
Figure 63. External Data Memory Interface (16-Mbtye Address Space)
Rev. D | Page 88 of 109
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04741-061
Data Sheet ADuC845/ADuC847/ADuC848
as op amps and voltage reference) can be powered from the AVDD supply line as well.
5 V Part
For DVDD below 4.5 V, the internal POR holds the device in reset. As DVDD rises above 4.5 V, an internal timer times out for approximately 128 ms before the device is released from reset. The user must ensure that the power supply has reached a stable 4.75 V minimum level by this time. Likewise on power-down, the internal POR holds the device in reset until the power supply drops below 1 V. Figure 67 illustrates this operation.
DIGITAL SUPPLY
+–
0.1
BEAD 1.6 6 DVDD
DD
10F
0.1F
10F
2
3
2
1 3
7 DGND 0
AV 4 ADuC845/
F
5
2 3 38 5
ADuC847/
ADuC848
5 6
AGND
DVDD
4.5V TYP 1.0V TYP
128ms TYP
128ms TYP
1.0V TYP
Figure 65. External Single-Supply Connections (56-Lead LFCSP Pin Numbering)
Notice that in both Figure 64 and Figure 65 a large value (10 μF) reservoir capacitor sits on DVDD and a separate 10 μF capacitor sits on AVDD. Also, local decoupling capacitors (0.1 μF) are located at each VDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are closer than the 10 μF capacitors to each VDD pin with lead lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, note that, at all times, the analog and digital ground pins on the device must be referenced to the same system ground reference point. It is recommended that the LFCSP paddle be soldered to ensure mechanical stability but be floated with respect to system VDDs or grounds.
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the ADuC845/ADuC847/ADuC848.
3 V Part
For DVDD below 2.63 V, the internal POR holds the device in reset. As DVDD rises above 2.63 V, an internal timer times out for typically 128 ms before the device is released from reset. The user must ensure that the power supply has at least reached a stable 2.7 V minimum level by this time. Likewise on power- down, the internal POR holds the device in reset until the power supply drops below 1 V. Figure 66 illustrates the operation of the internal POR.
INTERNAL CORE RESET
2.63V TYP
DVDD
INTERNAL CORE RESET
128ms TYP
128ms TYP
1.0V TYP
The DVDD power supply current consumption is specified in normal and power-down modes. The AVDD power supply current is specified with the analog peripherals disabled. The normal mode power consumption represents the current drawn from DVDD by the digital core. The other on-chip peripherals (such as the watchdog timer and power supply monitor) consume negligible current and are therefore included with the normal operating current. The user must add any currents sourced by the parallel and serial I/O pins, and those sourced by the DAC to determine the total current needed at the ADuC845/ ADuC847/ADuC848 DVDD and AVDD supply pins. Also, current drawn from the DVDD supply increases by approximately 5 mA during Flash/EE erase and program cycles.
POWER-SAVING MODES
Setting the power-down mode bit, PCON.1, in the PCON SFR described in Table 6, allows the chip to be switched from normal mode into full power-down mode.
In power-down mode, both the PLL and the clock to the core are stopped. The on-chip oscillator can be halted or can continue to oscillate, depending on the state of the oscillator power-down bit (OSC_PD) in the PLLCON SFR. The TIC, driven directly from the oscillator, can also be enabled during power-down. However, all other on-chip peripherals are shut down. Port pins retain their logic levels in this mode, but the DAC output goes to a high impedance state (three-state) while ALE and PSEN outputs are held low. There are five ways to terminate power-down mode:
Asserting the RESET Pin
Returns to normal mode. All registers are set to their reset default value and program execution starts at the reset vector once the RESET pin is de-asserted.
1.0V TYP
POWER CONSUMPTION
Figure 67. 5 V Part POR Operation
Figure 66. 3 V Part POR operation
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ADuC845/ADuC847/ADuC848 Data Sheet
Cycling Power
All registers are set to their default state and program exe- cution starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz oscillator remains powered up even in power-down mode. If the time interval counter (wake-up/RTC timer) is enabled, a TIC interrupt wakes the device from power-down mode. The CPU services the TIC interrupt. The RETI at the end of the TIC ISR returns the core to the next instruction after that one the enabled power-down.
SPI Interrupt
If the SERIPD bit in the PCON SFR is set, an SPI interrupt, if enabled, wakes up the device from power-down mode. The CPU services the SPI interrupt. The RETI at the end of the ISR returns the core to the next instruction after the one that enabled power-down.
INT0 Interrupt
If the INT0PD bit in the PCON SFR is set, an external interrupt 0, if enabled, wakes up the device from power- down. The CPU services the interrupt. The RETI at the end of the ISR returns the core to the next instruction after the one that enabled power-down.
Wake-Up from Power-Down Latency
Even with the 32 kHz crystal enabled during power-down, the PLL takes some time to lock after a wake-up from power-down. Typically, the PLL takes about 1 ms to lock. During this time, code executes, but not at the specified frequency. Some opera- tions, for example, UART communications, require an accurate clock to achieve the specified 50 Hz/60 Hz rejection from the ADCs. Therefore, it is advisable to wait until the PLL has locked before proceeding with normal code execution. The following code can be used to wait for the PLL to lock:
WAITFORLOCK: MOV A, PLLCON
JNB ACC.6, WAITFORLOCK
If the crystal is powered down during power-down, an additional delay is associated with the startup of the crystal oscillator before the PLL can lock. Typically taking about 150 ms, 32 kHz crystals are inherently slow to oscillate. During this time before lock, code executes, but the exact frequency of the clock cannot be guaranteed. For any timing-sensitive operations, it is recommended to wait for lock by using the lock bit in PLLCON as previously shown.
An alternative way of saving power in power-down mode is to slow down the core clock by using the CD bits in the PLLCON register.
GROUNDING AND BOARD LAYOUT RECOMMENDATIONS
As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC845/ ADuC847/ADuC848-based designs to achieve optimum performance from the ADCs and DAC.
Although the devices have separate pins for analog and digital ground (AGND and DGND), the user must not tie these to separate ground planes unless the two ground planes are connected together very close to the device as shown in the simplified example in Figure 68 (a). In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply, for example), they cannot be connected again near the device since a ground loop would result. In these cases, tie the AGND and DGND pins of the device to the analog ground plane, as shown in Figure 68 (b). In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The parts can then be placed between the digital and analog sections, as shown in Figure 68 (c).
In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 68 (b) with DVDD since that would force return currents from DVDD to flow through AGND. Also, try to avoid digital currents flowing under analog circuitry, which may happen if the user placed a noisy digital chip on the left half of the board in Figure 68 (c). Whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. Make all connections directly to the ground plane, with little or no trace separating the pin from its via to ground.
Rev. D | Page 90 of 109
Data Sheet
ADuC845/ADuC847/ADuC848
a.
b.
c.
PLACE ANALOG COMPONENTS HERE
AGND
PLACE ANALOG COMPONENTS HERE
AGND
PLACE ANALOG COMPONENTS HERE
PLACE DIGITAL COMPONENTS HERE
DGND
PLACE DIGITAL COMPONENTS HERE
DGND
PLACE DIGITAL COMPONENTS HERE
Table 63. CHIPID Values for Σ-Δ MicroConverter Products
Device CHIPID
ADuC816 1xH ADuC824 0xH ADuC836 3xH ADuC834 2xH ADuC845/ADuC847/ADuC848 AxH
Clock Oscillator
As described earlier, the core clock frequency for the ADuC845/ ADuC847/ADuC848 is generated from an on-chip PLL that locks onto a multiple (384 times) of 32.768 kHz. The latter is generated from an internal clock oscillator. To use the internal clock oscillator, connect a 32.768 kHz parallel resonant crystal between XTAL1 and XTAL2 as shown in Figure 69.
GND
XTAL1 32.768kHz
XTAL2
32
33
ADuC845/ADuC847/ADuC848 12pF
TO INTERNAL PLL
04741-064
04741-065
Figure 68. System Grounding Schemes
If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the digital inputs of the ADuC845/ADuC847/ADuC848 add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the input pins of the device. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capacitively into the device and affecting the accuracy of ADC conversions.
When using the LFCSP package, it is recommended that the paddle underneath the chip be soldered to the board to provide maximum mechanical stability. However, it is recommended that this paddle not be grounded but left floating. All results and specifications contained in this data sheet are taken or recorded with the paddle floating.
System Self-Identification
In some hardware designs, it may be advantageous for the software to be able to identify the host MicroConverter.
The CHIPID SFR is a read-only register located at SFR address C2H. The upper nibble of this SFR designates the MicroConverter within the Σ-Δ ADC family. User software can read this SFR to identify the host MicroConverter and therefore execute slightly different code if required. The CHIPID SFR reads as follows for the Σ-Δ ADC family of MicroConverter products. Note that the ADuC845/ADuC847/ADuC848 are treated as one device as far as the CHIPID is concerned.
Figure 69. Crystal Connectivity to ADuC845/ADuC847/ADuC848
As shown in the typical external crystal connection diagram in Figure 69, two internal 12 pF capacitors are provided on-chip. These are connected internally, directly to the XTAL1 and XTAL2 pins. The total input capacitance at both pins is detailed in the Specifications table. Note that the total capacitance required for a particular crystal must be in accordance with the crystal manufacturer. However, in most cases, no additional external capacitance is required above that already supplied on-chip.
OTHER HARDWARE CONSIDERATIONS
In-Circuit Serial Download Access
Nearly all ADuC845/ADuC847/ADuC848 designs can take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the UART of the devices, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is shown in Figure 70 with a simple ADM3202-based circuit. If users would rather not include an RS-232 chip on the target board, refer to the uC006 Application Note, A 4-Wire UART- to-PC Interface, for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the device.
Rev. D | Page 91 of 109
12pF
ADuC845/ADuC847/ADuC848 Data Sheet
DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN)
1k
1k
5 4
DVDD
200A/400A EXCITATION CURRENT
RTD RREF
EXC
REFIN+
DVDD
RESET ACTIVE HIGH. (NORMALLY OPEN)
2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN)
32.768kHz
1 AVDD
0.1F
8 5
44 43
1 P1.6/I 1/AIN7 ADuC845/ADuC847/ADuC848
4 AVDD
5 AGND AGND
REFIN–
6 P1.0/AIN1
1 P1.1/AIN2
LFCSP PACKAGE
XTAL2 3 XTAL1 3
17 18 19 22 36 51 23 37 38 50
6 7
5.6k
DVDD 0.1F DVDD
RS-232 INTERFACE1 0.1F
0.1F
0.1F
STANDARD D-TYPE SERIAL COMMS CONNECTOR TO PC HOST
ADM3202 C1+ VCC V+ GND C1– T1OUT C2+ R1IN C2– R1OUT V– T1IN T2OUT T2IN R2IN R2OUT
1
2 3 4 5 6 7 8 9
NOTES
1. EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART
OF AN EXTERNAL DONGLE AS DESCRIBED IN APPLICATION NOTE uC006.
In addition to the basic UART connections, users also need a way to trigger the chip into download mode. This is accomplished via a 1 kΩ pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 70. To get the devices into download mode, connect this jumper and power-cycle the device (or manually reset the device, if a manual reset button is available), and it is ready to receive a new program serially. With the jumper removed, the device powers on in normal mode (and runs the program) whenever power is cycled or RESET is toggled. Note that PSEN is normally an output and that it is sampled as an input only on the falling edge of RESET, that is, at power-on or upon an external manual reset. Note also that if any external circuitry unintentionally pulls PSEN low during power-on or reset events, it may cause the chip to enter download mode and fail to begin user code execution. To
prevent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself or the method of download entry in use during a reset or power-cycle condition.
Embedded Serial Port Debugger
From a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described previously. In fact, both serial download and serial port debug modes are essentially one mode of operation used in two different ways.
The serial port debugger is fully contained on the device, unlike ROM monitor type debuggers, and, therefore, no external memory is needed to enable in-system debug sessions.
Figure 70. UART Connectivity in Typical System
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04741-088
RESET RxD TxD
DVDD DGND
PSEN EA
Data Sheet ADuC845/ADuC847/ADuC848
Single-Pin Emulation Mode
Built into the ADuC845/ADuC847/ADuC848 is a dedicated controller for single-pin in-circuit emulation (ICE). In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally on the 8051 standard, this pin is hardwired either high or low to select execution from internal or external program memory space. Note that external program memory or execu- tion from external program memory is not allowed on the devices. To enable single-pin emulation mode, users need to pull the EA pin high through a 1 kΩ resistor as shown in
Figure 70. The emulator then connects to the 2-pin header also shown in Figure 70. To be compatible with the standard connec- tor that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), use a 2-pin 0.1-inch pitch Friction Lock header from Molex (www.molex.com) such as part number 22-27-2021. Be sure to observe the polarity of this header. As shown in Figure 70, when the Friction Lock tab is at the right, the ground pin should be the lower of the two pins when viewed from the top.
Typical System Configuration
A typical ADuC845/ADuC847/ADuC848 configuration is shown in Figure 70. Figure 70 also includes connections for a typical analog measurement application of the devices, namely an interface to a resistive temperature device (RTD). The arrangement shown is commonly referred to as a 4-wire
RTD configuration.
Here, the on-chip excitation current sources are enabled to excite the sensor. The excitation current flows directly through the RTD generating a voltage across the RTD proportional to its resistance. This differential voltage is routed directly to one set of the positive and negative inputs of the ADC (AIN1, AIN2, respectively in this case). The same current that excited the RTD also flows through a series resistance, RREF, generating a ratiometric voltage reference, VREF. The ratiometric voltage reference ensures that variations in the excitation current do not affect the measurement system since the input voltage from the RTD and reference voltage across RREF vary ratiometrically with the excitation current. Resistor RREF must, however, have a low temperature coefficient to avoid errors in the reference voltage overtemperature. RREF must also be large enough to generate at least a 1 V voltage reference.
The preceding example shows just a single differential ADC connection using a single reference input pair. The ADuC845/ ADuC847/ADuC848 have the capability of connecting to five differential inputs directly or ten single-ended inputs (LFCSP package only) as well as having a second reference input. This arrangement means that different sensors with different reference ranges can be connected to the device with the need for external multiplexing circuitry. This arrangement is shown in Figure 71. The bridge sensor shown can be a load cell or a pressure sensor. The RTD is shown using a reference voltage derived from the RREF resistor via the REFIN± inputs, and the bridge sensor is shown using a divided down AVDD reference via the REFIN2± inputs.
Rev. D | Page 93 of 109
ADuC845/ADuC847/ADuC848 Data Sheet
DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN)
1k
1k
DVDD
2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN)
200A/400A EXCITATION CURRENT
EXC
11
4
1 AIN9
RESET ACTIVE HIGH. (NORMALLY OPEN)
RS232 CONNECTION
Figure 71. Dual Reference Typical Connectivity
AVDD
0.1F
ADuC845/ADuC847/ADuC848
44 43
P1.6/I
AVDD 5 AGND AGND
REFIN– 8 REFIN+
1/AIN7
LFCSP PACKAGE
DGND DVDD XTAL2 3
XTAL1 3
56 P1.0/AIN1
1 P1.1/AIN2
2 P1.2/AIN3/REFIN2+
5
6 AIN10
3 P1.3/AIN4/REFIN2–
17 18 19 22 36 51 23 37 38 50
1
RTD RREF
5 4
6 7
5.6k AVDD R
R
DVDD
DVDD 0.1F DVDD
Rev. D | Page 94 of 109
04741-067
RESET RxD TxD
DVDD DGND
PSEN EA
Data Sheet ADuC845/ADuC847/ADuC848
QuickStart DEVELOPMENT SYSTEM
The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC8xx MicroConverter product family. The system consists of the following PC-based (Windows®-compatible) hardware and software development tools:
QuickStart-PLUS DEVELOPMENT SYSTEM
The QuickStart-PLUS development system offers users enhanced nonintrusive debug and emulation tools. The system consists of the following PC-based (Windows-compatible) hardware and software development tools:
Hardware:
Software: Miscellaneous:
Evaluation board and serial port programming cable.
Serial download software.
CD-ROM documentation and prototype evaluation board.
Hardware: Software:
Miscellaneous:
Prototype Board, Accutron NonIntrusive Single-Pin Emulator.
ASPIRE Integrated Development Environment. Features full C and Assembly emulation using the Accutron single-pin emulator.
CD-ROM documentation.
A brief description of some of the software tools and components in the QuickStart system follows.
Download—In-Circuit Serial Downloader
The serial downloader is a Windows application that allows the user to serially download an assembled program (Intel® hexa- decimal format file) to the on-chip program flash memory via the serial COM port on a standard PC. The AN-1074 Application Note details this serial download protocol.
ASPIRE—IDE
The ASPIRE® integrated development environment is a Windows application that allows the user to compile, edit, and debug code in the same environment. The ASPIRE software allows users to debug code execution on silicon using the MicroConverter UART serial port. The debugger provides access to all on-chip peripherals during a typical debug session as well as single-step, animate (automatic single stepping), and break-point code execution control.
Note that the ASPIRE IDE is also included as part of the QuickStart-PLUS system. As part of the QuickStart-PLUS system the ASPIRE IDE also supports mixed level and C source debugging. This is not available in the QuickStart system where the program is limited to assembly only.
Rev. D | Page 95 of 109
ADuC845/ADuC847/ADuC848 Data Sheet
TIMING SPECIFICATIONS
AC inputs during testing are driven at DVDD – 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0 as shown in Figure 72.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 72.
Table 64. CLOCK INPUT (External Clock Driven XTAL1) Parameter
tCK
tCKL tCKH tCKR tCKF 1/tCORE tCORE tCYC
CLOAD for all outputs = 80 pF, unless otherwise noted.
AVDD =2.7Vto3.6Vor4.75Vto5.25V,DVDD =2.7Vto3.6V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.
Unit
μs μs μs ns ns MHz μs μs
32.768 kHz External Crystal
Min Typ Max
XTAL1 Period
XTAL1 Width Low XTAL1 Width High XTAL1 Rise Time XTAL1 Fall Time
Core Clock Frequency1 Core Clock Period2 Machine Cycle Time3
30.52 6.26 6.26 9
9
0.098 1.57 12.58
0.636
10.2 0.636 0.08
1 ADuC845/ADuC847/ADuC848 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
2 This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
3 ADuC845/ADuC847/ADuC848 machine cycle time is nominally defined as 1/Core_Clk.
DVDD – 0.5V 0.45V
0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V
VLOAD – 0.1V VLOAD
VLOAD + 0.1V
TIMING REFERENCE POINTS
VLOAD – 0.1V VLOAD
VLOAD – 0.1V
Figure 72. Timing Waveform Characteristics
Rev. D | Page 96 of 109
04741-077
Data Sheet ADuC845/ADuC847/ADuC848
Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter
12.58 MHz Core Clock
6.29 MHz Core Clock
Min Max
Min Max
RD Pulse Width
Address Valid After ALE Low Address Hold After ALE Low
RD Low to Valid Data In
Data and Address Hold After RD Data Float After RD
ALE Low to Valid Data In Address to Valid Data In
ALE Low to RD or WR Low Address Valid to RD or WR Low RD Low to Address Float
RD or WR High to ALE High
60 60 145
0
130 190
60
48
150 170 230
15
125 120 290
0
255 375
120
100
625 350 470
35
tRLRH
tAVLL tLLAX tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tRLAZ tWHLH
Unit
ns ns
ns ns ns ns ns ns ns ns ns ns
ALE (O)
PSEN (O)
RD (O)
PORT 0 (I/O)
PORT 2 (O)
tWHLH
tRHDZ
tLLDV
tAVWL tLLAX
tLLWL
tRLRH
tRHDX
tRLDV
tRLAZ
A0 A7(OUT)
tAVDV
DATA (IN)
A16 A23
A8 A15
tAVLL
Figure 73. External Data Memory Read Cycle
Rev. D | Page 97 of 109
04741-078
ADuC845/ADuC847/ADuC848 Data Sheet
Table 66. EXTERNAL DATA MEMORY WRITE CYCLE Parameter
12.58 MHz Core Clock
6.29 MHz Core Clock
Min Max
Min Max
WR Pulse Width
Address Valid After ALE Low Address Hold After ALE Low
ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Transition
Data Setup Before WR
Data and Address Hold After WR RD or WR High to ALE High
65 60 65
190
60
120
380
60
130
130 120 135
375
120
250
755
125
260
tWLWH
tAVLL tLLAX tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH
Unit
ns ns
ns ns ns ns ns ns ns
ALE (O)
PSEN (O)
WR (O)
PORT 2 (O)
t
tLLWL
tAVWL LLAX
tQVWX
tWLWH
tQVWH
tWHLH
tWHQX
tAVLL
A0 A7
DATA
A16 A23
V8 A15
Table 67. I2C-COMPATIBLE INTERFACE TIMING Parameter
Parameter
tL
tH tSHD tDSU tDHD tRSU tPSU tBUF tR
tF tSUP1
1 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
Unit
μs μs μs μs μs μs μs μs ns ns ns
Figure 74. External Data Memory Write Cycle
Min Max
SCLCK Low Pulse Width SCLCK High Pulse Width Start Condition Hold Time Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time Between a Stop Condition and a Start Condition Rise Time of Both SCLCK and SDATA
Fall Time of Both SCLCK and SDATA
Pulse Width of Spike Suppressed
1.3 0.6 0.6 100
0.9 0.6
0.6 1.3
300 300 50
Rev. D | Page 98 of 109
04741-079
Data Sheet ADuC845/ADuC847/ADuC848
tBUF
tSUP
LSB
tR
MSB
t tF DHD
SDATA (I/O)
tPSU
MSB
ACK
tDSU
tDHD
tDSU
tSHD
tH
tRSU
tR
tF
SCLK (I) 1 2-7 8 9 1
tL
tSUP
PS
S(R)
STOP START CONDITION CONDITION
REPEATED START
Figure 75. I2C-Compatible Interface Timing
Rev. D | Page 99 of 109
04741-080
ADuC845/ADuC847/ADuC848 Data Sheet
Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter
Unit
Min Typ Max
SCLOCK Low Pulse Width1
SCLOCK High Pulse Width1
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge Data Input Hold Time After SCLOCK Edge Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
635 635
10 25 10 25 10 25 10 25
100 100
50
tSL ns tSH ns tDAV ns tDSU ns tDHD ns tDF ns tDR ns tSR ns tSF ns
1 Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK (CPOL = 0)
SCLOCK (CPOL = 1)
MOSI
MISO
tSH tSL
tSR
tSF
LSB
LSB IN
tDAV
tDF tDR
MSB
BITS 6–1
MSB IN
BITS 6–1
tDSU tDHD
Figure 76. SPI Master Mode Timing (CHPA = 1)
Rev. D | Page 100 of 109
04741-081
Data Sheet ADuC845/ADuC847/ADuC848
Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter
tSL ns tSH ns tDAV ns tDOSU ns tDSU ns tDHD ns tDF ns tDR ns tSR ns tSF ns
1 Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz. b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
Unit
Min Typ Max
SCLOCK Low Pulse Width1
SCLOCK High Pulse Width1
Data Output Valid After SCLOCK Edge
Data Output Setup Before SCLOCK Edge Data Input Setup Time Before SCLOCK Edge Data Input Hold Time After SCLOCK Edge Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
635 635
10 25 10 25 10 25 10 25
50 150
100 100
SCLOCK (CPOL = 0)
SCLOCK (CPOL = 1)
MOSI
MISO
tSH
MSB
tDSU tDHD
tSL
tSR tSF
tDAV
tDF
tDOSU
tDR
BITS 6–1
BITS 6–1
LSB
LSB IN
M
SB IN
Figure 77. SPI Master Mode Timing (CHPA = 0)
Rev. D | Page 101 of 109
04741-082
ADuC845/ADuC847/ADuC848 Data Sheet
Table 70. SPI SLAVE MODE TIMING (CPHA = 1) Parameter
Min Typ Max
SS to SCLOCK Edge
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge Data Input Hold Time After SCLOCK Edge Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SS High After SCLOCK Edge
0
330
100 100
0
330
50
10 25 10 25 10 25 10 25
tSS
tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
Unit
ns ns ns ns ns ns ns ns ns ns ns
SS
SCLOCK (CPOL = 0)
SCLOCK (CPOL = 1)
MISO
MOSI
tSS
tSFS
tSF
tSH
tDAV
tSL
MSB
MSB IN
tDSU tDHD
tSR
tDF tDR
BITS 6–1
BITS 6–1
LSB
LSB IN
Figure 78. SPI Slave Mode Timing (CHPA = 1)
Rev. D | Page 102 of 109
04741-083
Data Sheet ADuC845/ADuC847/ADuC848
Table 71. SPI SLAVE MODE TIMING (CPHA = 0) Parameter
Min Typ Max
SS to SCLOCK Edge
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge Data Input Hold Time After SCLOCK Edge Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
Data Output Valid After SS Edge
SS High After SCLOCK Edge
0
330
100 100
330
50
10 25 10 25 10 25 10 25
20
tSS
tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
SS
SCLOCK (CPOL = 0)
SCLOCK (CPOL = 1)
MISO
MOSI
tSFS
tDOSS
tSS
tSH
tSL
tDAV
tSR
LSB IN
tSF
M
B IN
tDF
tDR
MSB
tDHD
BITS 6–1
LSB
S
tDSU
BITS 6–1
Figure 79. SPI Slave Mode Timing (CHPA = 0)
Rev. D | Page 103 of 109
04741-084
ADuC845/ADuC847/ADuC848 Data Sheet
Table 72. UART TIMING (SHIFT REGISTER MODE) Parameter
12.58 MHz Core_Clk
Variable Core_Clk
Min Typ Max
Serial Port Clock Cycle Time Output Data Setup to Clock Input Data Setup to Clock Input Data Hold After Clock Output Data Hold After Clock
954 662
292 0 22
Min Typ Max
12tcore
TXLXL TQVXH TDVXH TXHDX TXHQX
Unit
ns ns ns ns ns
TxD (OUTPUT CLOCK)
RxD (OUTPUT DATA)
RxD (INPUT DATA)
tQVXH
tXHQX
tXLXL
BIT 6
SET RI OR SET TI
MSB
LSB
LSB
BIT 1
tDVXH
tXHDX
BIT 1
Figure 80. UART Timing in Shift Register Mode
Rev. D | Page 104 of 109
BIT 6
04741-086
Data Sheet ADuC845/ADuC847/ADuC848
OUTLINE DIMENSIONS
2.10 2.00 1.95
1.03 0.88 0.73
2.45 MAX
14.15 13.90 SQ 13.65
52
1 39
40
TOP VIEW (PINS DOWN)
10.20 10.00 SQ
9.80
0.23 0.11
7° 0°
13
27
LEAD WIDTH
0.25 0.15 0.10
14
26
0.38
0.22
0.10 COPLANARITY
VIEW A
0.65 BSC LEAD PITCH
VIEW A ROTATED 90° CCW
PIN 1 INDICATOR
0.80 0.75 0.70
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-112-AC-2
Figure 81. 52-Lead Metric Quad Flat Package [MQFP] (S-52-2)
Dimensions shown in millimeters
8.10 8.00 SQ 7.90
TOP VIEW
0.30 0.23 0.18
BOTTOM VIEW
6.50 REF
43 42
56 1
0.50 BSC
0.50 0.40 0.30
0.05 MAX 0.02 NOM
COPLANARITY 0.08
0.20 REF
*6.25 6.10 SQ 5.95
0.25 MIN
EXPOSED PAD
14 28 15
29
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 82. 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 mm × 8 mm Body and 0.75 mm Package Height (CP-56-11)
Dimensions shown in millimeters
Rev. D | Page 105 of 109
1.95 REF
SEATING PLANE
PIN 1 INDICATOR
PKG-004356
08-23-2013-A
06-10-20014-B
ADuC845/ADuC847/ADuC848 Data Sheet
ORDERING GUIDE Model1, 2, 3
Package Option
Temperature Range
Package Description
−40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
52-Lead MQFP, Lead Free, 62-kbyte, 5 V 52-Lead MQFP, Lead Free, 62-kbyte, 5 V 52-Lead MQFP, Lead Free, 62-kbyte, 3 V 52-Lead MQFP, Lead Free, 8-kbyte, 5 V 52-Lead MQFP, Lead Free, 8-kbyte, 5 V 52-Lead MQFP, Lead Free, 8-kbyte, 3 V 56-Lead LFCSP, Lead Free, 62-kbyte, 5 V 56-Lead LFCSP, Lead Free, 62-kbyte, 3 V 56-Lead LFCSP, Lead Free, 8-kbyte, 5 V 56-Lead LFCSP, Lead Free, 8-kbyte, 3 V
−40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
52-Lead MQFP, Lead Free, 62-kbyte, 5 V 52-Lead MQFP, Lead Free, 62-kbyte, 3 V 52-Lead MQFP, Lead Free, 32-kbyte, 5 V 52-Lead MQFP, Lead Free, 32-kbyte, 3 V 52-Lead MQFP, Lead Free, 8-kbyte, 5 V 52-Lead MQFP, Lead Free, 8-kbyte, 3 V 56-Lead LFCSP, Lead Free, 62-kbyte, 5 V 56-Lead LFCSP, Lead Free, 62-kbyte, 3 V 56-Lead LFCSP, Lead Free, 8-kbyte, 5 V 56-Lead LFCSP, Lead Free, 8-kbyte, 3 V
−40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
52-Lead MQFP, Lead Free, 62-kbyte, 5 V 52-Lead MQFP, Lead Free, 62-kbyte, 3 V 52-Lead MQFP, Lead Free, 32-kbyte, 5 V 52-Lead MQFP, Lead Free, 32-kbyte, 3 V 52-Lead MQFP, Lead Free, 8-kbyte, 5 V 52-Lead MQFP, Lead Free, 8-kbyte, 3 V 56-Lead LFCSP, Lead Free, 62-kbyte, 5 V 56-Lead LFCSP, Lead Free, 62-kbyte, 3 V 56-Lead LFCSP, Lead Free, 8-kbyte, 5 V 56-Lead LFCSP, Lead Free, 8-kbyte, 3 V
QuickStart Development System QuickStart-PLUS Development System QuickStart Development System
ADuC Serial Downloader Cable for UART
ADuC845BSZ62-5 S-52-2 ADuC845BSZ62-5-RL S-52-2 ADuC845BSZ62-3 S-52-2 ADuC845BSZ8-5 S-52-2 ADuC845BSZ8-5-RL S-52-2 ADuC845BSZ8-3 S-52-2 ADuC845BCPZ62-5 CP-56-11 ADuC845BCPZ62-3 CP-56-11 ADuC845BCPZ8-5 CP-56-11 ADuC845BCPZ8-3 CP-56-11 ADuC847BSZ62-5 S-52-2 ADuC847BSZ62-3 S-52-2 ADuC847BSZ32-5 S-52-2 ADuC847BSZ32-3 S-52-2 ADuC847BSZ8-5 S-52-2 ADuC847BSZ8-3 S-52-2 ADuC847BCPZ62-5 CP-56-11 ADuC847BCPZ62-3 CP-56-11 ADuC847BCPZ8-5 CP-56-11 ADuC847BCPZ8-3 CP-56-11 ADuC848BSZ62-5 S-52-2 ADuC848BSZ62-3 S-52-2 ADuC848BSZ32-5 S-52-2 ADuC848BSZ32-3 S-52-2 ADuC848BSZ8-5 S-52-2 ADuC848BSZ8-3 S-52-2 ADuC848BCPZ62-5 CP-56-11 ADuC848BCPZ62-3 CP-56-11 ADuC848BCPZ8-5 CP-56-11 ADuC848BCPZ8-3 CP-56-11 EVAL-ADuC845QSZ
EVAL-ADuC845QSPZ EVAL-ADuC847QSZ EVAL-ADUC-CABLE1Z
1 The -3 and -5 in the Model column indicate the DVDD operating voltage.
2 Z = RoHS Compliant Part.
3 The QuickStart Plus system can only be ordered directly from Accutron. It can be purchased from the website http://www.accutron.com.
Rev. D | Page 106 of 109
Data Sheet ADuC845/ADuC847/ADuC848
NOTES
Rev. D | Page 107 of 109
ADuC845/ADuC847/ADuC848 Data Sheet
NOTES
Rev. D | Page 108 of 109
Data Sheet ADuC845/ADuC847/ADuC848
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04741-0-5/16(D)
Rev. D | Page 109 of 109