Unit 1
¡ñ Given the y86 notation from the textbook, describe in plain English, at a high level, what an instruction does.
¡ñ Map back and forth between y86 assembly language and C.
¡ñ Explain/Define what is meant by the term “Calling Conventions.”
¡ñ Provide an example of a calling convention.
¡ñ When given a calling convention write code that conforms to the calling convention.
¡ñ Describe in plain English what a small piece of Y86 is doing.
¡ñ Explain the purpose and use of the Y86 assembler directives.
¡ñ Given instruction encodings for an ISA, translate in both directions between the
assembly language representation and the hexadecimal representation.
¡ñ Enumerate, in order, the instruction processing stages of the y86 sequential processor.
¡ñ Describe/explain, in plain English, what each stage in the y86 sequential processor
does.
¡ñ Use the notation from the text to describe what happens in each stage of the processor
as the instruction is executed. Some examples are:
¡ð Execute Stage: valE <-- valB + (-8)
¡ð Memory stage: M8[valE] <-- valA
¡ð Write back stage: R[%rsp] <-- valE
¡ñ Given a description of what the processor does at each stage determine what the assembly language level actions are and express the actions using the shorthand used to describe the precise behaviour of an instruction:
R[rB]=R[rA]*R[rB];PC =PC+10;
¡ñ Given a, possibly new, instruction list the operations that need to be performed at each stage as part of the instruction's execution, or explain why the instruction cannot be executed.
Unit 2
¡ñ Explain how a CPU pipeline works and how it can contribute to the efficient execution of a program.
¡ñ Trace the flow of instructions through a pipelined processor. As part of the trace be able to explain what values would be loaded (and when) into the pipeline registers.
¡ñ Appropriately use latency, throughput, and CPI to describe the performance of a pipeline.
¡ñ Perform latency, throughput and CPI calculations for both sequential and pipelined processors as appropriate.
¡ñ Given y86 instructions, identify the dependencies that exist.
¡ñ Given a sequence of assembler instructions identify and classify all dependencies at the
instruction level.
¡ñ Define what a control hazard is and when it occurs.
¡ñ Define what a data hazard is and identify when it occurs.
¡ñ Given a sequence of assembler instructions identify all dependencies that result in hazards at the pipeline level for the pipelined CPU described in class and the text. You should be able to do this for CPUs that use both stalling and/or data forwarding.
¡ñ Explain how a pipelined processor uses stalling, data forwarding, to reduce, eliminate, or mitigate the issues associated with hazards.
¡ñ Define what is meant by a pipeline bubble and explain why/how a bubble is generated.
¡ñ For a sequence of machine language instructions, given an arbitrary execution point,
describe the state of the pipeline:
¡ð When there are no hazards.
¡ð When hazards are handled using only stalling.
¡ð When hazards are handled using stalling and/or data forwarding.
¡ð When hazards are handled using stalling, data forwarding, and/or branch
prediction.
¡ñ Stalling with respect to control hazards:
¡ð Compare and contrast different strategies to handle control hazards for direct jumps and returns; pay particular attention to how incorrect predictions are handled.
¡ð Define and explain the difference between dynamic and static jump prediction.
¡ð For a given dynamic jump prediction strategy, suggest and justify the way in
which the various jump instructions could be used to minimize bubbles under that
strategy.
¡ð Enumerate and describe the challenges that indirect jumps impose
¡ñ Describe and provide examples of techniques other than pipelining for increasing instruction level parallelism (e.g. super scalar, multi-core, hyper threading).
¡ñ Compute CPI given the frequency of instructions that have hazards and the proportion of the instructions that have hazards that result in bubbles.
Unit 3:
¡ñ Justify the need for a memory hierarchy with several different levels on modern computers.
¡ñ Explain why caches are effective in many/most situations.
¡ñ Determine whether or not a piece of code has good or bad temporal or spatial locality.
¡ñ For a given cache be able to determine the mapping between the bits of an address and
their usage for determining the block offset, index, and tag values used in caching.
¡ñ Given a cache configuration and a memory address determine what would be retrieved
from the cache. Be able to do this for direct mapped, N-Way and fully associative
caches.
¡ñ Describe the result of a sequence of memory operations on a cache with a given
configuration. (i.e. what will be in the cache and where after the operations.)
¡ñ Compare and contrast the trade-offs associated with the choice of block size and
associativity, for a fixed cache size
¡ñ Apply Amdahl¡¯s law to compute the speedup obtained by making a change to a given part of a program or computer system.
¡ñ Classify each of a sequence of memory operations using a cache with a given configuration as either a cache hit, a cold (or compulsory) miss, a conflict miss, or a capacity miss.
¡ñ Given a cache configuration and an initially empty cache, estimate the cache miss rate for a piece of code that accesses one or more arrays.
¡ñ Compare and contrast various replacement policies
¡ñ Compare and contrast write-through and write-back policies, as well as write-allocate
and no-write-allocate.
¡ñ Given cache and memory performance parameters compute the average read time for a
particular workload.
¡ñ Given cache and memory performance parameters compute the average write time for a
particular workload.
¡ñ Given a sequence of memory block accesses specify the values of the cache coherency
meta-date for MSI and MESI. Unit 4
V6 means the UNIX v6 file system; ext2 means the Linux ext2 file system, as discussed in class and used in assignment 4.
In the learning goals UFS means Unix File system and both the Linux ext[234] file systems and the Berkeley Fast File System (FFS). From a conceptual level there is very little difference between these systems and differences are in the details (e.g. the number of direct blocks in an inode)
¡ñ Explain why disks are accessed differently from memory.
¡ñ Explain the differences between rotating and solid state disks, and the implications of
these differences on performance.
¡ñ Explain the trade-offs involved with increasing block size on a file system.
¡ñ Compare and contrast the layouts of v6 and ext2.
¡ñ Given a file name, trace how the blocks, or a specific byte of a file. would be located in a
FAT or Unix file system and subsequently retrieved.
¡ñ Given a path name, identify the inodes and (if the information is available) the disk
blocks that will be accessed to locate the inode corresponding to the path.
¡ñ Given a file system layout and a byte offset, describe how to find the block containing
the byte offset.
¡ñ Contrast internal and external fragmentation, and explain briefly how modern file
systems try to minimize the impact of both types of fragmentation.
¡ñ Describe the contents of an Inode and explain how it is used.
¡ñ Given the basic parameters of a v6 or ext2 file system, compute the maximum size a file
could have.
¡ñ Explain what a file descriptor is.
¡ñ Provide a programming example using a file descriptor.
¡ñ Describe the relationship between the file descriptor table, open file table, and v-node
table.
¡ñ Trace the actions that occur with respect to a process's file descriptor table, the open file
table, and v-node table when a file is opened or closed.
¡ñ Explain which of the file descriptor table, the open file table, and the v-node table unique
to a process and which are shared across all processes.
¡ñ Explain what happens to the file descriptor table, the open file table, and the v-node
table on a fork. Unit 5
¡ñ Describe the logical organization of a process (code, heap, data, stack).
¡ñ Compare and contrast the differences between user mode and kernel mode with respect
to what can be done in each mode.
¡ñ Define trap.
¡ñ List the three different kinds of traps.
¡ñ Identify which kinds of traps are synchronous with respect to a process¡¯ execution and
which are asynchronous.
¡ñ Describe the sequence of steps that happen during a trap.
¡ñ Enumerate the rationale for having virtual memory
¡ñ Explain the purpose of virtual address spaces.
¡ñ Summarize the role/purpose of the operating system.
¡ñ Explain how virtual memory addresses each of the following problems:
¡ð Efficient memory usage
¡ð Process isolation
¡ð Given a virtual memory system and the contents of a k-level page table, translate
a virtual address into a physical address.
¡ñ Describe the actions taken by an operating system to handle page faults
¡ñ Explain why a multi-level page table is more efficient than a single-level page table.
¡ñ Describe how the operating system determines which page to evict.
¡ñ Compare and contrast different page replacement strategies such as strict LRU, clock,
and MRU (most recently used).
¡ñ Explain which replacement strategies would or would not be appropriate for a hardware
cache, a file system cache, and a virtual memory system.
¡ñ Describe how the operating system uses reference and modified bits to implement page
replacement.