CS2202 Computer Architecture
Final Examination Total 36 points (01:30hrs.)
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Write Your name and ID * Huayi Tao 6138425
1. (6 Points) Consider a 0.25 nanosecond (ns) MIPS processor system is executing an application program with the following instructions: 800 register-register, 350 branch, 220 load, and 150 store instructions. Similarly, their clock cycle counts are 2, 4, 5, and 5 respectively. Based on the given information, calculate the CPU time and MIPS rate of the given system (write your name and ID a!er the answer). *
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2. (2 Points) Consider two corporate computers with two di”erent brands of CPUs with 3GHz clock speed each. A pa#icular benchmark test on their speed of various loops causes the following ratios: 2.36, 1.88, 3.46, and 4.48. What is the central tendency of these measurements? (Write your name and ID a!er the answer). *
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3. (4 Points) Suppose that you have to choose between DP4600 (a 4-processor system with 2.5 GHz clock speed each) and H6600 (an 8-processor system with 2.5 GHz clock speed each) server systems. Assume that scheduling a task on both servers adds an overhead, which is 30% on the H6600 server whereas the overhead on the DP4600 server is just 20% only. Which system is more e$cient for running your task? (Write your name and ID a!er the answer). *
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4. (1 Point) Why is a Flash memory faster than Electrically Erasable Programmable ROM (EEPROM)? (Write your Name and ID a!er the answer). *
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5. (1 Point) An instruction set with 64 simple instructions would need —– bits to encode the operation. (Write your Name and ID a!er the answer). *
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6. (1 Point) Why is a program store commonly used variables are in registers than in main memory? (Write your Name and ID a!er the answer). *
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7. (1 Point) Why is SRAM (Static Random Access Memory) faster than DRAM (Dynamic RAM)? (Write your name and ID a!er the answer) *
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8. (2 Points) Assume the bit organization of a DRAM (Dynamic RAM) chip is 8Gx8 (8G rows and 8 columns). What is the input size of its address decoder (in bits)? (write your name and ID a!er the answer). *
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9. ( 1 Point) In a 32-bit MIPS system, why is the result of a multiplication instruction is cannot be stored in a single register? (Write your name and ID a!er the answer). *
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10. (1 Point) What is the largest possible result of multiplying two unsigned N-bit numbers? (write your name and ID a!er the answer) *
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11. (2 Points) Di”erentiate the RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architectures. Is the MIPS processor a RISC? Why? (Write your name and ID a!er the answer). *
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12. (2 Points) Brie%y describe the impo#ance of instruction set in a computer system. (write your name and ID a!er the answer). *
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13. (2 Points) Consider the stack memory segment of the MIPS system which is shown in Figure1. (11.1). What is the current value of the Stack Pointer (SP)? (11.2). If the stack is pushed with 0x871E2AB3, and 0x453ACE19 in order along with the current data, then what will be the value of SP. (Write your name and ID a!er the answer). *
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Figure 1 Stack memory segment.
14. (2 Points) Write MIPS assembly code for swapping the contents of two registers, t0 and t1. You may not use any other registers. (Write your name and ID a!er the answer). *
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15. (2 Points) Consider the following MIPS assembly code snippet: add $t0, $s0, $s1 lw $t0, 0x20($t7) addi $s0, $0, −8 (15.1). Which instructions are I-type instructions? (15.2).Sign-extend the 16-bit immediate of each instruction into a 32-bit number (hexadecimal). *
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16. (2 Points) What is the range of instruction addresses to which conditional branches, such as beq and bne, can branch in a 32-bit MIPS system? (write your name and ID a!er the answer). *
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17. (2 Points) Conve# the following high- level code to MIPS instructions (assumes the integer variables g and h are in registers S0 and S1 respectively): if (g > h) g = g + h else g = g − h; *
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18. (2 Points) Consider the following MIPS instruction (where S0 and S1 are two 32-bit general-purpose integer registers): SW S1, 0x10(S0). Assume that the registers S0 and S1 are initialized with values of 0 and 0x56A78BC1 respectively. Show the contents of the following memory locations of the MIPS’s data memory a!er the store word operation: (18.1). 0x00000011 (18.2). 0x00000012. *
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