Computer Architecture LAB 2
By Jahangir Ikram
Experiment: To study the basic instruction processing in MIPS, basics of pipelining and problems in pipelining.
NOTES: 1. In today’s lab we will concentrate on instructions other than Branch instructions. 2. Please follow the handout exactly as you are guided to do so.
EXPERIMENT 1: Basic Instruction Processing the ADD instruction:
Step 1. Run the visual MIPS simulator by downloading it from my website from the following link. http://suraj.lums.edu.pk/~jikram.
Run the simulator. In the Architecture menu select MIPS 5-STAGE INTEGER PIPELINE. You will see the following screen. Now go to File Menu and select write
program. You will be asked to Enter a Starting Value of
Program Memory Address where you want to write you
program. Enter any value in Decimal, eg, 67676 or
23424324, or something small and simple like 2000 and
press OK. MIPS Integer Program Writer screen will appear.
Here you can write a maximum of 25 instruction program
which is more than enough for this course. By default all
instruction are set to NOP which is translated as SLL
R0,R0,R0. Fill exercise 1 at the end of this handout.
Step 2. Write a single instruction program ADD R5, R4, R3. Now press Assemble. The program appears on the side of the simulator. Save this program as SingleADD, just in case.
Step 3. The Instruction Fetch STEP.
Press Clock it to step through this program. As described in
the class yesterday, the Program Counter (PC) output goes
to instruction memory (IM) and Instruction appears at the output of IM. Click on the instruction, an info bar appears. Fill exercise 2 at the end using the handout. Note that PC+4 is also calculated as next address.
Step 4: The Instruction Decode and Register Fetch Stage.
Press clock it again to go to the next step. For time being just ignore what changes have happened back in the IF stage. As you remember from the class, at this stage R4 as Rs and R3 as Rt go to the Register File (Regs). BUT WHAT VALUES REGISTER FILE WILL RETURN? In a real program some useful info is suppose to be in Regs. The simulator asks you to initialize these two register with some initial values. Give R4 as 100 and R3 as 200. The inputs are done in Decimal. Note that these value appear somewhere on the top also. Also you can see register file contents anytime by clock Register Menu at the top. Another thing to be noted is that Opcode goes to Control Unit and it generates a lot of controls for rest of the instruction steps. The simulator does NOT draw these lines to final destination for sake of simplicity, but you can assume that all the RED lines in the diagram are controls. Some of these control are required for EXE step, other in MEM step and lastly very few are required for WB step. Also note that the Immediate field is sign extended although it not required for ADD instruction but it still does not hurt. Note that only these values are displayed in HEX and all other values on the diagram appear in decimal.
Step 5: The Instruction goes Execution
Press clock it. In Exe step, the importance of each field of the instruction becomes quite clear.
Note 1: B input of the ALU is selected to be R3 register (whose value we initialized to 200) and 32-bit Sign extended Immediate field is rejected.
Note 2: The small control under ALU can still pick the right fields from immediate date and decodes this instruction to be ADD from the function code.
Note 3: At the top Branch target Address Adder assumes immediate field to be Branch Offset, multiplies it by 4 (by shifting left 2 times) and adds NPC. Verify that this is the answer that you got in the exercise 2.
Note 4. The main ALU adds R4 and R3 and AluOUT0 sets out to be 300.
Note 5: The bottom small multiplexer selects Rd from Rt and Rd as Rd is destination for this instruction. Hold your comments on this until you have seen the next instruction.
Step 6: The MEM stage.
This instruction has nothing to do with memory, so it bypasses the Data Memory in MEM stage. So simply Clock it through.
Note 1. AluOUT goes to memory but for non LW and SW instructions, memory simply returns 999 which, as you will see, is rejected in the WB stage. So there is nothing further for this instruction in this stage.
Step 7: The WB stage.
In the Write Back stage, first notice RegisterWrite is 1 for this instruction as this instruction is going to write in the Register File. Second notice that very last multiplexer selects AluOUT from AluOUT and Loaded Memory Data (LMD). Which in return is written to the register file at Rdest.
EXPERIMENT 2: Basic Instruction Processing the LW instruction:
STEP 1: Write single instruction program LW R7, ⎯ 200(R8), using the Integer Program Writer (IPW). You can use CLEAR to clear the program memory. Press Assemble and save it as singleLW just in case.
STEP2. The IF stage.
Press clock it and bring the instruction from Instruction memory. As before fill the table in exercise three.
STEP3. Now are before step through the instruction and fill the table.
Note 1. We read Rt from register file but it is not used as you will see when you step through the instruction. When asked for R8, enter 100010 and when asked for R7 just give a value of 7777.
Note 2: In EXE stage Rt is selected as destination. As there is no Rd for this instruction.
Note 3: In EXE stage note what value is selected to be B input.
Note 4. In MEM stage, since this is memory related instruction, we are trying to load a value at address given by AluOUT, enter an initial value of this memory location when asked, say 525252.
Note 5. Note what is selected in WB stage.
EXPERIMENT 3: Basic Instruction Processing the SW instruction:
STEP 1: Write single instruction program SW R7, ⎯ 200(R8), using the Integer Program Writer (IPW). You can use CLEAR to clear the program memory. Press Assemble and save it as singleSW just in case.
STEP2. The IF stage.
Press clock it and bring the instruction from Instruction memory. As before fill the table in exercise 5.
STEP3. Now are before step through the instruction and fill the table.
Note 1. We read Rt from register file but it is not used as you will see when you step through the instruction. When asked for R8, enter 100010 and when asked for R7 just give a value of 7777.
Note 2: In EXE stage Rt is selected as destination. As there is no Rd for this instruction.
Note 3: In EXE stage note what value is selected to be B input.
Note 4. In MEM stage, since this is memory related instruction, we are trying to store a value at address given by AluOUT, see the value that is stored in the memory pressing Memory Menu at the top. Note what is MEMWrite for this instruction.
Note 5. Note what is selected in WB stage. What is register write and why. Fill exercise 6.
EXPERIMENT 4: Basic Instruction Processing the ADDI instruction:
Write a single ADDI R5, R6, 1000 and run it through. Now you must be able to see the expected behavior this instruction in the Pipeline.
EXPERIMENT 5: The Pipelined processor:
Using the IPW, write the following program: ADD R4, R5, R6
LW R7, 100(R8)
SLTI R9, R10, -1000
SW R1, 200(R2) SUB R11, R12, R13
Assemble and save it as MyFirst.
R3 give 33333, R4 Give 44444 and so on. For R10 and after give 10000, 11000, 12000 etc. For memory load give 77777 as initial value. Now clock this program and see how nicely each instruction is dealt on its merit in each stage of the pipeline. Fill the Exercise 7 when ADD instruction is in WB stage. . Notice that an
Clock it when asked for register value give related value, for example, for
instruction becomes blue when it has completed. Make all of the above instructions blue and now fill final values of registers
EXPERIMENT 5: The Problems with Pipelined processor:
Using the IPW, write the following program:
ADD R1, R2, R3 SUB R5, R6, R1 ADD R4, R1, R5 SW R1, 200(R4) LW R4, 100(R1)
Assemble and save it as MySecond.
example, for R3 give 33333, R4 Give 44444 and so on. Notice that an instruction becomes blue when it has completed. Make all of the above instructions blue and now fill exercise 8. What problems do you see?
EXPERIMENT 6: Inserting NOPs:
Clock it when asked for register value again give related value, for
Using the IPW, verify Example 1. ADD SUB
Example 2. ADD NOP SUB
Example 3. ADD NOP NOP
SUB
Example 4. ADD NOP NOP NOP
SUB
which of the following program works properly. Notice that an R1, R2, R3
R5, R6, R1
R1, R2, R3 R5, R6, R1 R1, R2, R3
R5, R6, R1 R1, R2, R3
R5, R6, R1
Now fill the table 9 for this exercise. As you see example 3 above works fine. Inserting these NOPs between data dependent instructions was done by hand in earlier computers and even today for processors with floating point unis built-in.
EXPERIMENT 7: Automatic NOPs — STALL Dectection:
Before we get to a much better solution, let us bring Stall detection Hardware. This Hardware is not shown in the diagram but it is there and can be activated by selecting Stall Detection in Options menu. This compares Rs and Rt field in ID stage with Rdest in EXE, MEM, and stalls the pipeline if they are equal. By stalling it means, one copy of the instruction stays in the ID stage, but other copy goes through the pipeline as normal. Its RegWrite and MemWrite, however, are made to 0, so it does not changes the state of the processor.
Reload MySecond, reset the processor and RUN the same program with Stall Detection ON and Fill Table 10. Note that it adds many ID stage stalls, solution next time.
Student ID ____________________________, Section _____M/E. Date:51-12-2005. Computer Archtecture LAB 2
Exercise 1:What is hex code for NOP or SLL R0, R0, R0 ____________________?
Exercise 2: By looking at the binary code of the instruction, discover the following fields:
Rs:_______, Rt_______, Rd____________, 16-bit Imm (Imm16)________, Shift amount ________, Function Code ________, Write MemWrite _________ and RegWrite______ for this instruction. What is use of
16-bit Immediate field in this instruction? __________________
If the same instruction were a Branch instruction, the immediate field would have represented a Branch Offset. What is the potential Target Address ______________?
Exercise 3: LW Instruction
Rs:_______, Rt_______, Rd____________, 16-bit Imm (Imm16)________, Shift amount ________, Function Code ________, Write MemWrite _________ and RegWrite______ for this instruction. What is use of Function filed and Shift Amount in this instruction? __________________
If the same instruction were a Branch instruction, the immediate field would have represented a Branch Offset. What is the potential Target Address ______________?
Exercise 4: Branch Target Found Adress____________, Is It same as EX.3___? B input to ALU________, Why? ________________________, ALUOut___________, ALUOP = __________, Why ________.
LMD__________, Rdest________ why this? _________________
RegWrite _____________, MemWrite _________________, What are two values at the input of very last MUX in the WB stage ________, ___________, Which value is selected _________, why _________. Final Register File Values._______, ____,____, ________
Exercise 5: SW instruction
Rs:_______, Rt_______, Rd____________, 16-bit Imm (Imm16)________, Shift amount ________, Function Code ________, Write MemWrite _________ and RegWrite______ for this instruction. What is use of Function filed and Shift Amount in this instruction? __________________
If the same instruction were a Branch instruction, the immediate field would have represented a Branch Offset. What is the potential Target Address ______________?
Exercise 6: Branch Target Found Adress____________, Is It same as EX.3___? B input to ALU________, Why? ________________________, ALUOut___________, ALUOP = __________, Why ________.
LMD__________, Rdest________ why this? _________________
RegWrite _____________, MemWrite _________________, Why__________________, What are two values at the input of very last
MUX in the WB stage ________, ___________, What is selected _________, why _________. Final Register File Values._______, ____,____, ________
Exercise 7:
Signal Name
Value
Why
ID.A
ID.B
ALUOUT in EXE
ALUOUT in MEM
ALUOUT IN EXE
RDEST in ID RDEST in EXE RDEST in MEM RDEST in WB
LMD in MEM LMD in WB
Final Values of Register File
Exercise 8:
Expected Values of Register File
Actual Values of Register File
Reason on difference
Exercise 9:
Instruction\Clock Cycle
1
2
3
4
5
6
7
8
9
10
11
12
ADD R1, R2, R3
IF
ID
NOP
NOP
SUB R5, R6, R1
Exercise 10:
Instruction\Clock Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADD R1, R2, R3
IF
ID
SUB R5, R6, R1
ADD R4, R1, R5
SW R1, 200(R4)
LW R4, 100(R1)