MIPS® Architecture for Programmers Volume II-A: The MIPS32® Instruction Set Manual
Document Number: MD00086 Revision 6.06 December 15, 2016
Public. This publication contains proprietary information which is subject to change without notice and is supplied ‘as is’, without any warranty of any kind.
The MIPS32® Instruction Set Manual, Revision 6.06
Table of Contents
Chapter 1: About This Book …………………………………………………………………………………………………… 2
1.1: Typographical Conventions …………………………………………………………………………………………………………. 3 1.1.1: Italic Text………………………………………………………………………………………………………………………….. 3 1.1.2: Bold Text………………………………………………………………………………………………………………………….. 3 1.1.3: Courier Text ……………………………………………………………………………………………………………………… 3
1.2: UNPREDICTABLE and UNDEFINED …………………………………………………………………………………………… 3 1.2.1: UNPREDICTABLE…………………………………………………………………………………………………………….. 3 1.2.2: UNDEFINED …………………………………………………………………………………………………………………….. 4 1.2.3: UNSTABLE ………………………………………………………………………………………………………………………. 4
1.3: Special Symbols in Pseudocode Notation……………………………………………………………………………………… 4 1.4: Notation for Register Field Accessibility ………………………………………………………………………………………… 7 1.5: For More Information ………………………………………………………………………………………………………………….. 9
Chapter 2: Guide to the Instruction Set …………………………………………………………………………………. 10
2.1: Understanding the Instruction Fields …………………………………………………………………………………………… 10 2.1.1: Instruction Fields ……………………………………………………………………………………………………………… 12 2.1.2: Instruction Descriptive Name and Mnemonic……………………………………………………………………….. 12 2.1.3: Format Field ……………………………………………………………………………………………………………………. 12 2.1.4: Purpose Field ………………………………………………………………………………………………………………….. 13 2.1.5: Description Field ……………………………………………………………………………………………………………… 13 2.1.6: Restrictions Field……………………………………………………………………………………………………………… 13 2.1.7: Availability and Compatibility Fields ……………………………………………………………………………………. 14 2.1.8: Operation Field………………………………………………………………………………………………………………… 15 2.1.9: Exceptions Field………………………………………………………………………………………………………………. 15 2.1.10: Programming Notes and Implementation Notes Fields………………………………………………………… 15
2.2: Operation Section Notation and Functions…………………………………………………………………………………… 16 2.2.1: Instruction Execution Ordering…………………………………………………………………………………………… 16 2.2.2: Pseudocode Functions……………………………………………………………………………………………………… 16
2.3: Op and Function Subfield Notation……………………………………………………………………………………………… 27 2.4: FPU Instructions ………………………………………………………………………………………………………………………. 27
Chapter 3: The MIPS32® Instruction Set ……………………………………………………………………………….. 29
3.1: Compliance and Subsetting……………………………………………………………………………………………………….. 29 3.1.1: Subsetting of Non-Privileged Architecture …………………………………………………………………………… 29 3.2: Alphabetical List of Instructions ………………………………………………………………………………………………….. 31 ABS.fmt ……………………………………………………………………………………………………………………………………… 32 ADD…………………………………………………………………………………………………………………………………………… 33 ADD.fmt……………………………………………………………………………………………………………………………………… 34 ADDI………………………………………………………………………………………………………………………………………….. 35 ADDIU ……………………………………………………………………………………………………………………………………….. 36 ADDIUPC …………………………………………………………………………………………………………………………………… 37 ADDU ………………………………………………………………………………………………………………………………………… 38 ALIGN………………………………………………………………………………………………………………………………………… 39 ALNV.PS ……………………………………………………………………………………………………………………………………. 41 ALUIPC ……………………………………………………………………………………………………………………………………… 43 AND…………………………………………………………………………………………………………………………………………… 44 ANDI………………………………………………………………………………………………………………………………………….. 45
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AUI ……………………………………………………………………………………………………………………………………………. 47 AUIPC ……………………………………………………………………………………………………………………………………….. 48 B ……………………………………………………………………………………………………………………………………………….. 49 BAL……………………………………………………………………………………………………………………………………………. 50 BALC …………………………………………………………………………………………………………………………………………. 52 BC …………………………………………………………………………………………………………………………………………….. 53 BC1EQZ BC1NEZ……………………………………………………………………………………………………………………….. 54 BC1F …………………………………………………………………………………………………………………………………………. 56 BC1FL ……………………………………………………………………………………………………………………………………….. 58 BC1T …………………………………………………………………………………………………………………………………………. 60 BC1TL ……………………………………………………………………………………………………………………………………….. 62 BC2EQZ BC2NEZ……………………………………………………………………………………………………………………….. 64 BC2F …………………………………………………………………………………………………………………………………………. 66 BC2FL ……………………………………………………………………………………………………………………………………….. 67 BC2T …………………………………………………………………………………………………………………………………………. 69 BC2TL ……………………………………………………………………………………………………………………………………….. 70 BEQ…………………………………………………………………………………………………………………………………………… 72 BEQL…………………………………………………………………………………………………………………………………………. 73 BGEZ…………………………………………………………………………………………………………………………………………. 75 BGEZAL …………………………………………………………………………………………………………………………………….. 76 B{LE,GE,GT,LT,EQ,NE}ZALC ………………………………………………………………………………………………………. 77 BGEZALL …………………………………………………………………………………………………………………………………… 80 B
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CVT.D.fmt…………………………………………………………………………………………………………………………………. 153 CVT.L.fmt …………………………………………………………………………………………………………………………………. 154 CVT.PS.S…………………………………………………………………………………………………………………………………. 155 CVT.S.PL …………………………………………………………………………………………………………………………………. 157 CVT.S.PU…………………………………………………………………………………………………………………………………. 158 CVT.S.fmt…………………………………………………………………………………………………………………………………. 159 CVT.W.fmt………………………………………………………………………………………………………………………………… 160 DDIV ………………………………………………………………………………………………………………………………………… 161 DDIVU ……………………………………………………………………………………………………………………………………… 162 DERET …………………………………………………………………………………………………………………………………….. 163 DI…………………………………………………………………………………………………………………………………………….. 164 DIV ………………………………………………………………………………………………………………………………………….. 165 DIV MOD DIVU MODU ………………………………………………………………………………………………………………. 168 DIV.fmt …………………………………………………………………………………………………………………………………….. 170 DIVU………………………………………………………………………………………………………………………………………… 171 DVP …………………………………………………………………………………………………………………………………………. 172 EHB …………………………………………………………………………………………………………………………………………. 175 EI …………………………………………………………………………………………………………………………………………….. 176 ERET ……………………………………………………………………………………………………………………………………….. 177 ERETNC…………………………………………………………………………………………………………………………………… 179 EVP …………………………………………………………………………………………………………………………………………. 181 EXT …………………………………………………………………………………………………………………………………………. 183 FLOOR.L.fmt …………………………………………………………………………………………………………………………….. 185 FLOOR.W.fmt……………………………………………………………………………………………………………………………. 186 GINVI……………………………………………………………………………………………………………………………………….. 187 GINVT ……………………………………………………………………………………………………………………………………… 189 INS ………………………………………………………………………………………………………………………………………….. 192 J………………………………………………………………………………………………………………………………………………. 194 JAL ………………………………………………………………………………………………………………………………………….. 195 JALR………………………………………………………………………………………………………………………………………… 196 JALR.HB…………………………………………………………………………………………………………………………………… 198 JALX………………………………………………………………………………………………………………………………………… 201 JIALC……………………………………………………………………………………………………………………………………….. 203 JIC …………………………………………………………………………………………………………………………………………… 205 JR ……………………………………………………………………………………………………………………………………………. 206 JR.HB ………………………………………………………………………………………………………………………………………. 208 LB ……………………………………………………………………………………………………………………………………………. 211 LBE………………………………………………………………………………………………………………………………………….. 212 LBU …………………………………………………………………………………………………………………………………………. 213 LBUE ……………………………………………………………………………………………………………………………………….. 214 LDC1 ……………………………………………………………………………………………………………………………………….. 215 LDC2 ……………………………………………………………………………………………………………………………………….. 216 LDXC1……………………………………………………………………………………………………………………………………… 218 LH……………………………………………………………………………………………………………………………………………. 219 LHE …………………………………………………………………………………………………………………………………………. 220 LHU …………………………………………………………………………………………………………………………………………. 221 LHUE……………………………………………………………………………………………………………………………………….. 222 LL ……………………………………………………………………………………………………………………………………………. 223 LLE ………………………………………………………………………………………………………………………………………….. 225 LLWP……………………………………………………………………………………………………………………………………….. 228 LLWPE …………………………………………………………………………………………………………………………………….. 230 LSA …………………………………………………………………………………………………………………………………………. 232 LUI…………………………………………………………………………………………………………………………………………… 233
LUXC1……………………………………………………………………………………………………………………………………… 234 LW …………………………………………………………………………………………………………………………………………… 235 LWC1 ………………………………………………………………………………………………………………………………………. 236 LWC2 ………………………………………………………………………………………………………………………………………. 237 LWE…………………………………………………………………………………………………………………………………………. 239 LWL …………………………………………………………………………………………………………………………………………. 240 LWLE……………………………………………………………………………………………………………………………………….. 242 LWPC ………………………………………………………………………………………………………………………………………. 246 LWR ………………………………………………………………………………………………………………………………………… 247 LWRE ………………………………………………………………………………………………………………………………………. 251 LWXC1 …………………………………………………………………………………………………………………………………….. 254 MADD………………………………………………………………………………………………………………………………………. 255 MADD.fmt…………………………………………………………………………………………………………………………………. 256 MADDF.fmt MSUBF.fmt ……………………………………………………………………………………………………………… 259 MADDU ……………………………………………………………………………………………………………………………………. 261 MAX.fmt MIN.fmt MAXA.fmt MINA.fmt………………………………………………………………………………………….. 262 MFC0……………………………………………………………………………………………………………………………………….. 266 MFC1……………………………………………………………………………………………………………………………………….. 267 MFC2……………………………………………………………………………………………………………………………………….. 268 MFHC0 …………………………………………………………………………………………………………………………………….. 270 MFHC1 …………………………………………………………………………………………………………………………………….. 271 MFHC2 …………………………………………………………………………………………………………………………………….. 272 MFHI………………………………………………………………………………………………………………………………………… 273 MFLO ………………………………………………………………………………………………………………………………………. 274 MOV.fmt …………………………………………………………………………………………………………………………………… 275 MOVF ………………………………………………………………………………………………………………………………………. 276 MOVF.fmt …………………………………………………………………………………………………………………………………. 277 MOVN………………………………………………………………………………………………………………………………………. 279 MOVN.fmt…………………………………………………………………………………………………………………………………. 280 MOVT ………………………………………………………………………………………………………………………………………. 281 MOVT.fmt…………………………………………………………………………………………………………………………………. 282 MOVZ ………………………………………………………………………………………………………………………………………. 284 MOVZ.fmt …………………………………………………………………………………………………………………………………. 285 MSUB ………………………………………………………………………………………………………………………………………. 286 MSUB.fmt …………………………………………………………………………………………………………………………………. 287 MSUBU ……………………………………………………………………………………………………………………………………. 289 MTC0……………………………………………………………………………………………………………………………………….. 290 MTC1……………………………………………………………………………………………………………………………………….. 292 MTC2……………………………………………………………………………………………………………………………………….. 293 MTHC0 …………………………………………………………………………………………………………………………………….. 294 MTHC1 …………………………………………………………………………………………………………………………………….. 295 MTHC2 …………………………………………………………………………………………………………………………………….. 296 MTHI………………………………………………………………………………………………………………………………………… 297 MTLO ………………………………………………………………………………………………………………………………………. 298 MUL…………………………………………………………………………………………………………………………………………. 299 MUL MUH MULU MUHU ……………………………………………………………………………………………………………. 300 MUL.fmt……………………………………………………………………………………………………………………………………. 302 MULT……………………………………………………………………………………………………………………………………….. 303 MULTU…………………………………………………………………………………………………………………………………….. 304 NAL …………………………………………………………………………………………………………………………………………. 306 NEG.fmt……………………………………………………………………………………………………………………………………. 307 NMADD.fmt ………………………………………………………………………………………………………………………………. 308 NMSUB.fmt ………………………………………………………………………………………………………………………………. 310
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NOP…………………………………………………………………………………………………………………………………………. 312 NOR ………………………………………………………………………………………………………………………………………… 313 OR …………………………………………………………………………………………………………………………………………… 314 ORI ………………………………………………………………………………………………………………………………………….. 315 PAUSE …………………………………………………………………………………………………………………………………….. 317 PLL.PS …………………………………………………………………………………………………………………………………….. 319 PLU.PS…………………………………………………………………………………………………………………………………….. 320 PREF ……………………………………………………………………………………………………………………………………….. 321 PREFE …………………………………………………………………………………………………………………………………….. 325 PREFX …………………………………………………………………………………………………………………………………….. 329 PUL.PS…………………………………………………………………………………………………………………………………….. 330 PUU.PS ……………………………………………………………………………………………………………………………………. 331 RDHWR……………………………………………………………………………………………………………………………………. 332 RDPGPR ………………………………………………………………………………………………………………………………….. 335 RECIP.fmt ………………………………………………………………………………………………………………………………… 336 RINT.fmt …………………………………………………………………………………………………………………………………… 337 ROTR ………………………………………………………………………………………………………………………………………. 339 ROTRV …………………………………………………………………………………………………………………………………….. 340 ROUND.L.fmt ……………………………………………………………………………………………………………………………. 341 ROUND.W.fmt…………………………………………………………………………………………………………………………… 342 RSQRT.fmt……………………………………………………………………………………………………………………………….. 343 SB……………………………………………………………………………………………………………………………………………. 344 SBE …………………………………………………………………………………………………………………………………………. 346 SC …………………………………………………………………………………………………………………………………………… 347 SCE …………………………………………………………………………………………………………………………………………. 351 SCWP………………………………………………………………………………………………………………………………………. 354 SCWPE ……………………………………………………………………………………………………………………………………. 358 SDBBP …………………………………………………………………………………………………………………………………….. 361 SDC1……………………………………………………………………………………………………………………………………….. 362 SDC2……………………………………………………………………………………………………………………………………….. 363 SDXC1 …………………………………………………………………………………………………………………………………….. 364 SEB …………………………………………………………………………………………………………………………………………. 365 SEH …………………………………………………………………………………………………………………………………………. 366 SEL.fmt…………………………………………………………………………………………………………………………………….. 368 SELEQZ SELNEZ ……………………………………………………………………………………………………………………… 369 SELEQZ.fmt SELNEQZ.fmt ………………………………………………………………………………………………………… 371 SH …………………………………………………………………………………………………………………………………………… 373 SHE …………………………………………………………………………………………………………………………………………. 374 SIGRIE …………………………………………………………………………………………………………………………………….. 375 SLL ………………………………………………………………………………………………………………………………………….. 376 SLLV………………………………………………………………………………………………………………………………………… 377 SLT………………………………………………………………………………………………………………………………………….. 378 SLTI…………………………………………………………………………………………………………………………………………. 379 SLTIU ………………………………………………………………………………………………………………………………………. 380 SLTU ……………………………………………………………………………………………………………………………………….. 381 SQRT.fmt …………………………………………………………………………………………………………………………………. 382 SRA …………………………………………………………………………………………………………………………………………. 383 SRAV……………………………………………………………………………………………………………………………………….. 384 SRL …………………………………………………………………………………………………………………………………………. 385 SRLV ……………………………………………………………………………………………………………………………………….. 386 SSNOP …………………………………………………………………………………………………………………………………….. 387 SUB …………………………………………………………………………………………………………………………………………. 388 SUB.fmt ……………………………………………………………………………………………………………………………………. 389
SUBU ………………………………………………………………………………………………………………………………………. 390 SUXC1 …………………………………………………………………………………………………………………………………….. 391 SW…………………………………………………………………………………………………………………………………………… 392 SWC1 ………………………………………………………………………………………………………………………………………. 393 SWC2 ………………………………………………………………………………………………………………………………………. 394 SWE ………………………………………………………………………………………………………………………………………… 396 SWL…………………………………………………………………………………………………………………………………………. 397 SWLE ………………………………………………………………………………………………………………………………………. 399 SWR ………………………………………………………………………………………………………………………………………… 401 SWRE………………………………………………………………………………………………………………………………………. 404 SWXC1…………………………………………………………………………………………………………………………………….. 406 SYNC ………………………………………………………………………………………………………………………………………. 407 SYNCI ……………………………………………………………………………………………………………………………………… 412 SYSCALL …………………………………………………………………………………………………………………………………. 415 TEQ …………………………………………………………………………………………………………………………………………. 416 TEQI ………………………………………………………………………………………………………………………………………… 417 TGE …………………………………………………………………………………………………………………………………………. 418 TGEI ………………………………………………………………………………………………………………………………………… 419 TGEIU ……………………………………………………………………………………………………………………………………… 420 TGEU ………………………………………………………………………………………………………………………………………. 421 TLBINV …………………………………………………………………………………………………………………………………….. 422 TLBINVF…………………………………………………………………………………………………………………………………… 425 TLBP ……………………………………………………………………………………………………………………………………….. 427 TLBR ……………………………………………………………………………………………………………………………………….. 428 TLBWI ……………………………………………………………………………………………………………………………………… 430 TLBWR…………………………………………………………………………………………………………………………………….. 432 TLT ………………………………………………………………………………………………………………………………………….. 434 TLTI…………………………………………………………………………………………………………………………………………. 435 TLTIU ………………………………………………………………………………………………………………………………………. 436 TLTU ……………………………………………………………………………………………………………………………………….. 437 TNE …………………………………………………………………………………………………………………………………………. 438 TNEI ………………………………………………………………………………………………………………………………………… 439 TRUNC.L.fmt…………………………………………………………………………………………………………………………….. 440 TRUNC.W.fmt …………………………………………………………………………………………………………………………… 441 WAIT ……………………………………………………………………………………………………………………………………….. 442 WRPGPR …………………………………………………………………………………………………………………………………. 444 WSBH………………………………………………………………………………………………………………………………………. 445 XOR…………………………………………………………………………………………………………………………………………. 446 XORI………………………………………………………………………………………………………………………………………… 447
Appendix A: Instruction Bit Encodings ……………………………………………………………………………….. 448
A.1: Instruction Encodings and Instruction Classes …………………………………………………………………………… 448 A.2: Instruction Bit Encoding Tables………………………………………………………………………………………………… 448 A.3: Floating Point Unit Instruction Format Encodings ……………………………………………………………………….. 459 A.4: Release 6 Instruction Encodings………………………………………………………………………………………………. 461
Appendix B: Revision History …………………………………………………………………………………………….. 466
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List of Figures
Figure 2.1: Example of Instruction Description …………………………………………………………………………………………. 11 Figure 2.2: Example of Instruction Fields…………………………………………………………………………………………………. 12 Figure 2.3: Example of Instruction Descriptive Name and Mnemonic ………………………………………………………….. 12 Figure 2.4: Example of Instruction Format ……………………………………………………………………………………………….. 12 Figure 2.5: Example of Instruction Purpose ……………………………………………………………………………………………… 13 Figure 2.6: Example of Instruction Description …………………………………………………………………………………………. 13 Figure 2.7: Example of Instruction Restrictions ………………………………………………………………………………………… 14 Figure 2.8: Example of Instruction Operation …………………………………………………………………………………………… 15 Figure 2.9: Example of Instruction Exception …………………………………………………………………………………………… 15 Figure 2.10: Example of Instruction Programming Notes …………………………………………………………………………… 16 Figure 2.11: COP_LW Pseudocode Function …………………………………………………………………………………………… 16 Figure 2.12: COP_LD Pseudocode Function……………………………………………………………………………………………. 17 Figure 2.13: COP_SW Pseudocode Function ………………………………………………………………………………………….. 17 Figure 2.14: COP_SD Pseudocode Function …………………………………………………………………………………………… 17 Figure 2.15: CoprocessorOperation Pseudocode Function ………………………………………………………………………… 18 Figure 2.16: MisalignedSupport Pseudocode Function ……………………………………………………………………………… 18 Figure 2.17: AddressTranslation Pseudocode Function …………………………………………………………………………….. 19 Figure 2.18: LoadMemory Pseudocode Function ……………………………………………………………………………………… 19 Figure 2.19: StoreMemory Pseudocode Function …………………………………………………………………………………….. 20 Figure 2.20: Prefetch Pseudocode Function…………………………………………………………………………………………….. 20 Figure 2.21: SyncOperation Pseudocode Function …………………………………………………………………………………… 21 Figure 2.22: ValueFPR Pseudocode Function………………………………………………………………………………………….. 21 Figure 2.23: StoreFPR Pseudocode Function ………………………………………………………………………………………….. 22 Figure 2.24: CheckFPException Pseudocode Function …………………………………………………………………………….. 23 Figure 2.25: FPConditionCode Pseudocode Function……………………………………………………………………………….. 23 Figure 2.26: SetFPConditionCode Pseudocode Function ………………………………………………………………………….. 24 Figure 2.27: sign_extend Pseudocode Functions ……………………………………………………………………………………… 24 Figure 2.28: memory_address Pseudocode Function ……………………………………………………………………………….. 25 Figure 2.29: Instruction Fetch Implicit memory_address Wrapping ……………………………………………………………… 25 Figure 2.30: AddressTranslation implicit memory_address Wrapping………………………………………………………….. 25 Figure 2.31: SignalException Pseudocode Function …………………………………………………………………………………. 26 Figure 2.32: SignalDebugBreakpointException Pseudocode Function ………………………………………………………… 26 Figure 2.33: SignalDebugModeBreakpointException Pseudocode Function…………………………………………………. 26 Figure 2.34: NullifyCurrentInstruction PseudoCode Function ……………………………………………………………………… 26 Figure 2.35: PolyMult Pseudocode Function ……………………………………………………………………………………………. 27 Figure 3.1: ALIGN operation (32-bit)……………………………………………………………………………………………………….. 39 Figure 3.2: Example of an ALNV.PS Operation………………………………………………………………………………………… 41 Figure 3.3: Usage of Address Fields to Select Index and Way………………………………………………………………….. 115 Figure 3.4: Usage of Address Fields to Select Index and Way………………………………………………………………….. 121 Figure 3.5: Operation of the EXT Instruction ………………………………………………………………………………………….. 183 Figure 3.6: Operation of the INS Instruction …………………………………………………………………………………………… 192 Figure 4.1: Unaligned Word Load Using LWL and LWR…………………………………………………………………………… 240 Figure 4.2: Bytes Loaded by LWL Instruction …………………………………………………………………………………………. 241 Figure 4.3: Unaligned Word Load Using LWLE and LWRE………………………………………………………………………. 242 Figure 4.4: Bytes Loaded by LWLE Instruction……………………………………………………………………………………….. 243 Figure 4.5: Unaligned Word Load Using LWL and LWR…………………………………………………………………………… 247 Figure 4.6: Bytes Loaded by LWR Instruction ………………………………………………………………………………………… 248
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Figure 4.7: Unaligned Word Load Using LWLE and LWRE………………………………………………………………………. 251 Figure 4.8: Bytes Loaded by LWRE Instruction ………………………………………………………………………………………. 252 Figure 5.9: Unaligned Word Store Using SWL and SWR …………………………………………………………………………. 397 Figure 5.10: Bytes Stored by an SWL Instruction ……………………………………………………………………………………. 398 Figure 5.11: Unaligned Word Store Using SWLE and SWRE …………………………………………………………………… 399 Figure 5.12: Bytes Stored by an SWLE Instruction………………………………………………………………………………….. 400 Figure 5.13: Unaligned Word Store Using SWR and SWL ……………………………………………………………………….. 401 Figure 5.14: Bytes Stored by SWR Instruction ……………………………………………………………………………………….. 402 Figure 5.15: Unaligned Word Store Using SWRE and SWLE …………………………………………………………………… 404 Figure 5.16: Bytes Stored by SWRE Instruction ……………………………………………………………………………………… 405 Figure A.1: Sample Bit Encoding Table …………………………………………………………………………………………………. 449
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List of Tables
Table 1.1: Symbols Used in Instruction Operation Statements……………………………………………………………………… 4 Table 1.2: Read/Write Register Field Notation …………………………………………………………………………………………… 7 Table 2.1: AccessLength Specifications for Loads/Stores………………………………………………………………………….. 20 Table 3.1: FPU Comparisons Without Special Operand Exceptions ………………………………………………………….. 111 Table 3.2: FPU Comparisons With Special Operand Exceptions for QNaNs ………………………………………………. 112 Table 3.3: Usage of Effective Address…………………………………………………………………………………………………… 114 Table 3.4: Encoding of Bits[17:16] of CACHE Instruction …………………………………………………………………………. 115 Table 3.5: Encoding of Bits [20:18] of the CACHE Instruction …………………………………………………………………… 116 Table 3.6: Usage of Effective Address…………………………………………………………………………………………………… 121 Table 3.7: Encoding of Bits[17:16] of CACHEE Instruction ………………………………………………………………………. 122 Table 3.8: Encoding of Bits [20:18] of the CACHEE Instruction ………………………………………………………………… 123 Table 3.1: Types of Global TLB Invalidates ……………………………………………………………………………………………. 189 Table 4.1: Special Cases for FP MAX, MIN, MAXA, MINA……………………………………………………………………….. 264 Table 5.2: Values of hint Field for PREF Instruction ………………………………………………………………………………… 322 Table 5.3: Values of hint Field for PREFE Instruction………………………………………………………………………………. 326 Table 5.4: RDHWR Register Numbers ………………………………………………………………………………………………….. 332 Table 5.5: Encodings of the Bits[10:6] of the SYNC instruction; the SType Field…………………………………………. 409 Table A.1: Symbols Used in the Instruction Encoding Tables …………………………………………………………………… 449 Table A.2: MIPS32 Encoding of the Opcode Field ………………………………………………………………………………….. 451 Table A.3: MIPS32 SPECIAL Opcode Encoding of Function Field ……………………………………………………………. 452 Table A.4: MIPS32 REGIMM Encoding of rt Field …………………………………………………………………………………… 452 Table A.5: MIPS32 SPECIAL2 Encoding of Function Field ………………………………………………………………………. 453 Table A.6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture………………………… 453 Table A.7: MIPS32 MOVCI6R Encoding of tf Bit …………………………………………………………………………………….. 453 Table A.8: MIPS32 SRL Encoding of Shift/Rotate …………………………………………………………………………………… 454 Table A.9: MIPS32 SRLV Encoding of Shift/Rotate…………………………………………………………………………………. 454 Table A.10: MIPS32 BSHFL Encoding of sa Field…………………………………………………………………………………… 454 Table A.11: MIPS32 COP0 Encoding of rs Field …………………………………………………………………………………….. 455 Table A.12: MIPS32 COP0 Encoding of Function Field When rs=CO………………………………………………………… 455 Table A.13: PCREL Encoding of Minor Opcode Field ……………………………………………………………………………… 455 Table A.14: MIPS32 Encoding of rs Field ………………………………………………………………………………………………. 456 Table A.15: MIPS32 COP1 Encoding of Function Field When rs=S…………………………………………………………… 456 Table A.16: MIPS32 COP1 Encoding of Function Field When rs=D ………………………………………………………….. 457 Table A.17: MIPS32 COP1 Encoding of Function Field When rs=W or L ………………………………………………….. 457 Table A.18: MIPS32 COP1 Encoding of Function Field When rs=PS ……………………………………………………….. 458 Table A.19: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS6R, Function=MOVCF6R ………………………. 458 Table A.20: MIPS32 COP2 Encoding of rs Field …………………………………………………………………………………….. 458 Table A.21: MIPS32 COP1X6R Encoding of Function Field …………………………………………………………………….. 459 Table A.22: Floating Point Unit Instruction Format Encodings…………………………………………………………………… 459 Table A.23: Release 6 MUL/DIV encodings …………………………………………………………………………………………… 462 Table A.24: Release 6 PC-relative family encoding…………………………………………………………………………………. 462 Table A.25: Release 6 PC-relative family encoding bitstrings …………………………………………………………………… 463 Table A.26: B*C compact branch encodings ………………………………………………………………………………………….. 464
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Chapter 1
About This Book
The MIPS32® Instruction Set Manual comes as part of a multi-volume set.
• Volume I-A describes conventions used throughout the document set, and provides an introduction to the MIPS32® Architecture
• Volume I-B describes conventions used throughout the document set, and provides an introduction to the micro- MIPSTM Architecture
• Volume II-A provides detailed descriptions of each instruction in the MIPS32® instruction set
• Volume II-B provides detailed descriptions of each instruction in the microMIPS32TM instruction set
• Volume III describes the MIPS32® and microMIPS32TM Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS® processor implementation
• Volume IV-a describes the MIPS16eTM Application-Specific Extension to the MIPS32® Architecture. Beginning with Release 3 of the Architecture, microMIPS is the preferred solution for smaller code size. Release 6 removes MIPS16e: MIPS16e cannot be implemented with Release 6.
• Volume IV-b describes the MDMXTM Application-Specific Extension to the MIPS64® Architecture and microMIPS64TM. It is not applicable to the MIPS32® document set nor the microMIPS32TM document set. With Release 5 of the Architecture, MDMX is deprecated. MDMX and MSA can not be implemented at the same time. Release 6 removes MDMX: MDMX cannot be implemented with Release 6.
• Volume IV-c describes the MIPS-3D® Application-Specific Extension to the MIPS® Architecture. Release 6 removes MIPS-3D: MIPS-3D cannot be implemented with Release 6.
• Volume IV-d describes the SmartMIPS®Application-Specific Extension to the MIPS32® Architecture and the microMIPS32TM Architecture . Release 6 removes SmartMIPS: SmartMIPS cannot be implemented with Release 6, neither MIPS32 Release 6 nor MIPS64 Release 6.
• Volume IV-e describes the MIPS® DSP Module to the MIPS® Architecture.
• Volume IV-f describes the MIPS® MT Module to the MIPS® Architecture
• Volume IV-h describes the MIPS® MCU Application-Specific Extension to the MIPS® Architecture
• Volume IV-i describes the MIPS® Virtualization Module to the MIPS® Architecture
• Volume IV-j describes the MIPS® SIMD Architecture Module to the MIPS® Architecture
The MIPS32® Instruction Set Manual, Revision 6.06 2
About This Book
1.1 Typographical Conventions
This section describes the use of italic, bold and courier fonts in this book. 1.1.1 Italic Text
• is used for emphasis
• is used for bits, fields, and registers that are important from a software perspective (for instance, address bits used by software, and programmable fields and registers), and various floating point instruction formats, such as S and D
• is used for the memory access types, such as cached and uncached 1.1.2 Bold Text
• represents a term that is being defined
• is used for bits and fields that are important from a hardware perspective (for instance, register bits, which are
not programmable but accessible only to hardware)
• is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through 1
• is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below. 1.1.3 Courier Text
Courier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.
1.2 UNPREDICTABLE and UNDEFINED
The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the pro- cessor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unpriv- ileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations.
1.2.1 UNPREDICTABLE
UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is gener- ated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.
UNPREDICTABLE results or operations have several implementation restrictions:
• Implementations of operations generating UNPREDICTABLE results must not depend on any data source
(memory or internal state) which is inaccessible in the current processor mode
3
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• UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process
• UNPREDICTABLE operations must not halt or hang the processor 1.2.2 UNDEFINED
UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED opera- tions or behavior may cause data loss.
UNDEFINED operations or behavior has one implementation restriction:
• UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which there is no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state
1.2.3 UNSTABLE
UNSTABLE results or values may vary as a function of time on the same implementation or instruction. Unlike UNPREDICTABLE values, software may depend on the fact that a sampling of an UNSTABLE value results in a legal transient value that was correct at some point in time prior to the sampling.
UNSTABLE values have one implementation restriction:
• Implementations of operations generating UNSTABLE results must not depend on any data source (memory or
internal state) which is inaccessible in the current processor mode
1.3 Special Symbols in Pseudocode Notation
In this book, algorithmic descriptions of an operation are described using a high-level language pseudocode resem- bling Pascal. Special symbols used in the pseudocode notation are listed in Table 1.1.
Table 1.1 Symbols Used in Instruction Operation Statements
1.3 Special Symbols in Pseudocode Notation
Symbol
Meaning
Assignment
, ≠
Tests for equality and inequality
Bit string concatenation
xy
A y-bit string formed by y copies of the single-bit value x
b#n
A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the “b#” prefix is omitted, the default base is 10.
0bn
A constant value n in base 2. For instance 0b100 represents the binary value 100 (decimal 4).
0xn
A constant value n in base 16. For instance 0x100 represents the hexadecimal value 100 (decimal 256).
The MIPS32® Instruction Set Manual, Revision 6.06 4
About This Book
Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
Symbol
Meaning
xy z
Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is less than z, this expression is an empty (zero length) bit string.
x.bit[y]
Bit y of bitstring x. Alternative to the traditional MIPS notation xy.
x.bits[y..z]
Selection of bits y through z of bit string x. Alternative to the traditional MIPS notation xy z.
x.byte[y]
Byte y of bitstring x. Equivalent to the traditional MIPS notation x8*y+7 8*y.
x.bytes[y..z]
Selection of bytes y through z of bit string x. Alternative to the traditional MIPS notation x8*y+7 8*z
x halfword[y] x.word[i] x.doubleword[i]
Similar extraction of particular bitfields (used in e.g., MSA packed SIMD vectors).
x.bit31, x.byte0, etc.
Examples of abbreviated form of x.bit[y], etc. notation, when y is a constant.
x fieldy
Selection of a named subfield of bitstring x, typically a register or instruction encoding.
More formally described as “Field y of register x”.
For example, FIR.D = “the D bit of the Coprocessor 1 Floating-point Implementation Register (FIR)”.
,
2’s complement or floating point arithmetic: addition, subtraction
*,
2’s complement or floating point multiplication (both used for either)
div
2’s complement integer division
mod
2’s complement modulo
Floating point division
2’s complement less-than comparison
2’s complement greater-than comparison
2’s complement less-than or equal comparison
≥
2’s complement greater-than or equal comparison
nor
Bitwise logical NOR
xor
Bitwise logical XOR
and
Bitwise logical AND
or
Bitwise logical OR
not
Bitwise inversion
&&
Logical (non-Bitwise) AND
<<
Logical Shift left (shift in zeros at right-hand-side)
>>
Logical Shift right (shift in zeros at left-hand-side)
GPRLEN
The length in bits (32 or 64) of the CPU general-purpose registers
GPR[x]
CPU general-purpose register x. The content of GPR[0] is always zero. In Release 2 of the Architecture, GPR[x] is a short-hand notation for SGPR[ SRSCtlCSS, x].
SGPR[s,x]
In Release 2 of the Architecture and subsequent releases, multiple copies of the CPU general-purpose regis- ters may be implemented. SGPR[s,x] refers to GPR set s, register x.
FPR[x]
Floating Point operand register x
FCC[CC]
Floating Point condition code CC. FCC[0] has the same value as COC[1]. Release 6 removes the floating point condition codes.
FPR[x]
Floating Point (Coprocessor unit 1), general register x
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1.3 Special Symbols in Pseudocode Notation Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
Symbol
Meaning
CPR[z,x,s]
Coprocessor unit z, general register x, select s
CP2CPR[x]
Coprocessor unit 2, general register x
CCR[z,x]
Coprocessor unit z, control register x
CP2CCR[x]
Coprocessor unit 2, control register x
COC[z]
Coprocessor unit z condition signal
Xlat[x]
Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number
BigEndianMem
Endian mode as configured at chip reset (0 Little-Endian, 1 Big-Endian). Specifies the endianness of the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions) and the endi- anness of Kernel and Supervisor mode execution.
BigEndianCPU
The endianness for load and store instructions (0 Little-Endian, 1 Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com- puted as (BigEndianMem XOR ReverseEndian).
ReverseEndian
Signal to reverse the endianness of load and store instructions. This feature is available in User mode only, and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as (SRRE and User mode).
LLbit
Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation, when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc- tions.
I:, I+n:, I-n:
This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the instruction time of another instruction. When this happens, the instruction operation is written in sections labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode appears to occur. For example, an instruction may have a result that is not available until after the next instruction. Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I+1.
The effect of pseudocode statements for the current instruction labeled I+1 appears to occur “at the same time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode sequence, the effects of the statements take place in order. However, between sequences of statements for different instructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.
PC
The Program Counter value. During the instruction time of an instruction, this is the address of the instruc- tion word. The address of the instruction that occurs during the next instruction time is determined by assign- ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc- tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.
In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the restart address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an exception. Release 6 adds PC-relative address computation and load instructions. The PC value contains a full 32-bit address, all of which are significant during a memory reference.
The MIPS32® Instruction Set Manual, Revision 6.06 6
About This Book
Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
Symbol
Meaning
ISA Mode
In processors that implement the MIPS16e Application Specific Extension or the microMIPS base architec- tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol- lows:
In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an exception.
Encoding
Meaning
0
The processor is executing 32-bit MIPS instructions
1
The processor is executing MIIPS16e or microMIPS instructions
PABITS
The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 phys- ical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.
FP32RegistersMode
Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). In MIPS32 Release 1, the FPU has 32, 32-bit FPRs, in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and optionally in MIPS32 Release2 and Release 3) the FPU has 32 64-bit FPRs in which 64-bit data types are stored in any FPR.
In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro- cessor operates as if it had 32, 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.
The value of FP32RegistersMode is computed from the FR bit in the Status register.
InstructionInBranchDe- laySlot
Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.
SignalException(excep- tion, argument)
Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function—the exception is signaled at the point of the call.
1.4 Notation for Register Field Accessibility
In this document, the read/write properties of register fields use the notations shown in Table 1.1.
Table 1.2 Read/Write Register Field Notation
Read/Write Notation
Hardware Interpretation
Software Interpretation
R/W
A field in which all bits are readable and writable by software and, potentially, by hardware.
Hardware updates of this field are visible by software read. Software updates of this field are visible by hardware read.
If the Reset State of this field is ‘‘Undefined’’, either software or hardware must initialize the value before the first read will return a predictable value. This should not be confused with the formal definition of UNDEFINED behavior.
7 The MIPS32® Instruction Set Manual, Revision 6.06
1.4 Notation for Register Field Accessibility Table 1.2 Read/Write Register Field Notation (Continued)
Read/Write Notation
Hardware Interpretation
Software Interpretation
R
A field which is either static or is updated only by hardware.
If the Reset State of this field is either ‘‘0’’, ‘‘Pre- set’’, or ‘‘Externally Set’’, hardware initializes this field to zero or to the appropriate state, respectively, on powerup. The term ‘‘Preset’’ is used to suggest that the processor establishes the appropriate state, whereas the term ‘‘Externally Set’’ is used to sug- gest that the state is established via an external source (e.g., personality pins or initialization bit stream). These terms are suggestions only, and are not intended to act as a requirement on the imple- mentation.
If the Reset State of this field is ‘‘Undefined’’, hard- ware updates this field only under those conditions specified in the description of the field.
A field to which the value written by software is ignored by hardware. Software may write any value to this field without affecting hardware behavior. Software reads of this field return the last value updated by hardware.
If the Reset State of this field is ‘‘Undefined’’, soft- ware reads of this field result in an UNPREDICT- ABLE value except after a hardware update done under the conditions specified in the description of the field.
R0
R0 = reserved, read as zero, ignore writes by soft- ware.
Hardware ignores software writes to an R0 field. Neither the occurrence of such writes, nor the val- ues written, affects hardware behavior.
Hardware always returns 0 to software reads of R0 fields.
The Reset State of an R0 field must always be 0.
If software performs an mtc0 instruction which writes a non-zero value to an R0 field, the write to the R0 field will be ignored, but permitted writes to other fields in the register will not be affected.
Architectural Compatibility: R0 fields are reserved, and may be used for not-yet-defined purposes in future revisions of the architecture.
When writing an R0 field, current software should only write either all 0s, or, preferably, write back the same value that was read from the field.
Current software should not assume that the value read from R0 fields is zero, because this may not be true on future hardware.
Future revisions of the architecture may redefine an R0 field, but must do so in such a way that software which is unaware of the new definition and either writes zeros or writes back the value it has read from the field will continue to work correctly.
Writing back the same value that was read is guaran- teed to have no unexpected effects on current or future hardware behavior. (Except for non-atomicity of such read-writes.)
Writing zeros to an R0 field may not be preferred because in the future this may interfere with the oper- ation of other software which has been updated for the new field definition.
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About This Book
Table 1.2 Read/Write Register Field Notation (Continued)
Read/Write Notation
Hardware Interpretation
Software Interpretation
0
Release 6
Release 6 legacy “0” behaves like R0 – read as zero, nonzero writes ignored.
Legacy “0” should not be defined for any new control register fields; R0 should be used instead.
HW returns 0 when read. Only zero should be written, or, value read from reg- HW ignores writes. ister.
pre-Release 6
pre-Release 6 legacy “0” – read as zero, nonzero writes UNDEFINED
A field which hardware does not update, and for which hardware can assume a zero value.
A field to which the value written by software must be zero. Software writes of non-zero values to this field may result in UNDEFINED behavior of the hardware. Software reads of this field return zero as long as all previous software writes are zero.
If the Reset State of this field is ‘‘Undefined’’, soft- ware must write this field with zero before it is guar- anteed to read as zero.
R/W0
Like R/W, except that writes of non-zero to a R/W0 field are ignored. E.g. Status.NMI
Hardware may set or clear an R/W0 bit.
Hardware ignores software writes of nonzero to an R/W0 field. Neither the occurrence of such writes, nor the values written, affects hardware behavior.
Software writes of 0 to an R/W0 field may have an effect.
Hardware may return 0 or nonzero to software reads of an R/W0 bit.
If software performs an mtc0 instruction which writes a non-zero value to an R/W0 field, the write to the R/W0 field will be ignored, but permitted writes to other fields in the register will not be affected.
Software can only clear an R/W0 bit.
Software writes 0 to an R/W0 field to clear the field.
Software writes nonzero to an R/W0 bit in order to guarantee that the bit is not affected by the write.
1.5 For More Information
MIPS processor manuals and additional information about MIPS products can be found at http://www.mips.com.
. .
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Chapter 2
Guide to the Instruction Set
This chapter provides a detailed guide to understanding the instruction descriptions, which are listed in alphabetical order in the tables at the beginning of the next chapter.
2.1 Understanding the Instruction Fields
Figure 2.1 shows an example instruction. Following the figure are descriptions of the fields listed below:
• “Instruction Fields” on page 12
• “Instruction Descriptive Name and Mnemonic” on page 12
• “Format Field” on page 12
• “Purpose Field” on page 13
• “Description Field” on page 13
• “Restrictions Field” on page 13
• “Operation Field” on page 15
• “Exceptions Field” on page 15
• “Programming Notes and Implementation Notes Fields” on page 15
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2.1.1 Instruction Fields
Fields encoding the instruction word are shown in register form at the top of the instruction description. The follow- ing rules are followed:
• The values of constant fields and the opcode names are listed in uppercase (SPECIAL and ADD in Figure 2.2). Constant values in a field are shown in binary below the symbolic or hexadecimal value.
• All variable fields are listed with the lowercase names used in the instruction description (rs, rt, and rd in Figure 2.2).
• Fields that contain zeros but are not named are unused fields that are required to be zero (bits 10:6 in Figure 2.2). If such fields are set to non-zero values, the operation of the processor is UNPREDICTABLE.
Figure 2.2 Example of Instruction Fields
2.1.2 Instruction Descriptive Name and Mnemonic
The instruction descriptive name and mnemonic are printed as page headings for each instruction, as shown in Figure 2.3.
Figure 2.3 Example of Instruction Descriptive Name and Mnemonic
2.1.3 Format Field
The assembler formats for the instruction and the architecture level at which the instruction was originally defined are given in the Format field. If the instruction definition was later extended, the architecture levels at which it was extended and the assembler formats for the extended definition are shown in their order of extension (for an example, see C.cond fmt). The MIPS architecture levels are inclusive; higher architecture levels include all instructions in pre- vious levels. Extensions to instructions are backwards compatible. The original assembler formats are valid for the extended architecture.
Figure 2.4 Example of Instruction Format
The assembler format is shown with literal parts of the assembler instruction printed in uppercase characters. The variable parts, the operands, are shown as the lowercase names of the appropriate fields.
The architectural level at which the instruction was first defined, for example “MIPS32” is shown at the right side of the page. Instructions introduced at different times by different ISA family members, are indicated by markings such
2.1 Understanding the Instruction Fields
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL 000000
rs
rt
rd
0 00000
ADD 100000
655556
Add Word ADD
Format: ADD fd,rs,rt MIPS32
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Guide to the Instruction Set
as “MIPS64, MIPS32 Release 2”. Instructions removed by particular architecture release are indicated in the Avail- ability section.
There can be more than one assembler format for each architecture level. Floating point operations on formatted data show an assembly format with the actual assembler mnemonic for each valid value of the fmt field. For example, the ADD fmt instruction lists both ADD.S and ADD.D.
The assembler format lines sometimes include parenthetical comments to help explain variations in the formats (once again, see C.cond.fmt). These comments are not a part of the assembler format.
2.1.4 Purpose Field
The Purpose field gives a short description of the use of the instruction. Figure 2.5 Example of Instruction Purpose
2.1.5 Description Field
If a one-line symbolic description of the instruction is feasible, it appears immediately to the right of the Description heading. The main purpose is to show how fields in the instruction are used in the arithmetic or logical operation.
Figure 2.6 Example of Instruction Description
Purpose: Add Word
To add 32-bit integers. If an overflow occurs, then trap.
Description: GPR[rd] GPR[rs] + GPR[rt]
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit
result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rd.
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The body of the section is a description of the operation of the instruction in text, tables, and figures. This description complements the high-level language description in the Operation section.
This section uses acronyms for register descriptions. “GPR rt” is CPU general-purpose register specified by the instruction field rt. “FPR fs” is the floating point operand register specified by the instruction field fs. “CP1 register fd” is the coprocessor 1 general register specified by the instruction field fd. “FCSR” is the floating point Control / Status register.
2.1.6 Restrictions Field
The Restrictions field documents any possible restrictions that may affect the instruction. Most restrictions fall into one of the following six categories:
• Valid values for instruction fields (for example, see floating point ADD.fmt)
• ALIGNMENT requirements for memory addresses (for example, see LW)
• Valid values of operands (for example, see ALNV.PS)
• Valid operand formats (for example, see floating point ADD.fmt)
• Order of instructions necessary to guarantee correct execution. These ordering constraints avoid pipeline hazards for which some processors do not have hardware interlocks (for example, see MUL).
• Valid memory access types (for example, see LL/SC)
Figure 2.7 Example of Instruction Restrictions
2.1.7 Availability and Compatibility Fields
The Availability and Compatibility sections are not provided for all instructions. These sections list considerations relevant to whether and how an implementation may implement some instructions, when software may use such instructions, and how software can determine if an instruction or feature is present. Such considerations include:
• Some instructions are not present on all architecture releases. Sometimes the implementation is required to signal a Reserved Instruction exception, but sometimes executing such an instruction encoding is architec- turally defined to give UNPREDICTABLE results.
• Some instructions are available for implementations of a particular architecture release, but may be provided only if an optional feature is implemented. Control register bits typically allow software to determine if the feature is present.
• Some instructions may not behave the same way on all implementations. Typically this involves behavior that was UNPREDICTABLE in some implementations, but which is made architectural and guaranteed con- sistent so that software can rely on it in subsequent architecture releases.
• Some instructions are prohibited for certain architecture releases and/or optional feature combinations.
• Some instructions may be removed for certain architecture releases. Implementations may then be required to signal a Reserved Instruction exception for the removed instruction encoding; but sometimes the instruc- tion encoding is reused for other instructions.
All of these considerations may apply to the same instruction. If such considerations applicable to an instruction are simple, the architecture level in which an instruction was defined or redefined in the Format field, and/or the Restric- tions section, may be sufficient; but if the set of such considerations applicable to an instruction is complicated, the Availability and Compatibility sections may be provided.
2.1 Understanding the Instruction Fields
Restrictions:
None
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Guide to the Instruction Set 2.1.8 Operation Field
The Operation field describes the operation of the instruction as pseudocode in a high-level language notation resem- bling Pascal. This formal description complements the Description section; it is not complete in itself because many of the restrictions are either difficult to include in the pseudocode or are omitted for legibility.
Figure 2.8 Example of Instruction Operation
Operation:
temp (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] temp endif
15
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See 2.2 “Operation Section Notation and Functions” on page 16 for more information on the formal notation used here.
2.1.9 Exceptions Field
The Exceptions field lists the exceptions that can be caused by Operation of the instruction. It omits exceptions that can be caused by the instruction fetch, for instance, TLB Refill, and also omits exceptions that can be caused by asyn- chronous external events such as an Interrupt. Although a Bus Error exception may be caused by the operation of a load or store instruction, this section does not list Bus Error for load and store instructions because the relationship between load and store instructions and external error indications, like Bus Error, are dependent upon the implemen- tation.
Figure 2.9 Example of Instruction Exception
An instruction may cause implementation-dependent exceptions that are not present in the Exceptions section. 2.1.10 Programming Notes and Implementation Notes Fields
The Notes sections contain material that is useful for programmers and implementors, respectively, but that is not necessary to describe the instruction and does not belong in the description sections.
Exceptions:
Integer Overflow
2.2 Operation Section Notation and Functions Figure 2.10 Example of Instruction Programming Notes
2.2 Operation Section Notation and Functions
In an instruction description, the Operation section uses a high-level language notation to describe the operation per- formed by each instruction. Special symbols used in the pseudocode are described in the previous chapter. Specific pseudocode functions are described below.
This section presents information about the following topics:
• “Instruction Execution Ordering” on page 16
• “Pseudocode Functions” on page 16
2.2.1 Instruction Execution Ordering
Each of the high-level language statements in the Operations section are executed sequentially (except as constrained by conditional and loop constructs).
2.2.2 Pseudocode Functions
There are several functions used in the pseudocode descriptions. These are used either to make the pseudocode more readable, to abstract implementation-specific behavior, or both. These functions are defined in this section, and include the following:
• “Coprocessor General Register Access Functions” on page 16
• “Memory Operation Functions” on page 18
• “Floating Point Functions” on page 21
• “Miscellaneous Functions” on page 25
2.2.2.1 Coprocessor General Register Access Functions
Defined coprocessors, except for CP0, have instructions to exchange words and doublewords between coprocessor general registers and the rest of the system. What a coprocessor does with a word or doubleword supplied to it and how a coprocessor supplies a word or doubleword is defined by the coprocessor itself. This behavior is abstracted into the functions described in this section.
2.2.2.1.1 COP_LW
The COP_LW function defines the action taken by coprocessor z when supplied with a word from memory during a load word operation. The action is coprocessor-specific. The typical action would be to store the contents of mem- word in coprocessor general register rt.
Figure 2.11 COP_LW Pseudocode Function
COP_LW (z, rt, memword)
Programming Notes:
ADDU performs the same arithmetic operation but does not trap on overflow.
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z: The coprocessor unit number
rt: Coprocessor general register specifier
memword: A 32-bit word value supplied to the coprocessor
/* Coprocessor-dependent action */
endfunction COP_LW
2.2.2.1.2 COP_LD
The COP_LD function defines the action taken by coprocessor z when supplied with a doubleword from memory during a load doubleword operation. The action is coprocessor-specific. The typical action would be to store the con- tents of memdouble in coprocessor general register rt.
Figure 2.12 COP_LD Pseudocode Function
COP_LD (z, rt, memdouble)
z: The coprocessor unit number
rt: Coprocessor general register specifier
memdouble: 64-bit doubleword value supplied to the coprocessor.
/* Coprocessor-dependent action */
endfunction COP_LD
2.2.2.1.3 COP_SW
The COP_SW function defines the action taken by coprocessor z to supply a word of data during a store word opera- tion. The action is coprocessor-specific. The typical action would be to supply the contents of the low-order word in coprocessor general register rt.
Figure 2.13 COP_SW Pseudocode Function
dataword COP_SW (z, rt)
z: The coprocessor unit number
rt: Coprocessor general register specifier dataword: 32-bit word value
/* Coprocessor-dependent action */
endfunction COP_SW
2.2.2.1.4 COP_SD
The COP_SD function defines the action taken by coprocessor z to supply a doubleword of data during a store dou- bleword operation. The action is coprocessor-specific. The typical action would be to supply the contents of the low- order doubleword in coprocessor general register rt.
Figure 2.14 COP_SD Pseudocode Function
datadouble COP_SD (z, rt)
z: The coprocessor unit number
rt: Coprocessor general register specifier datadouble: 64-bit doubleword value
/* Coprocessor-dependent action */
endfunction COP_SD
2.2.2.1.5 CoprocessorOperation
The CoprocessorOperation function performs the specified Coprocessor operation.
Figure 2.15 CoprocessorOperation Pseudocode Function
CoprocessorOperation (z, cop_fun)
/* z: Coprocessor unit number */
/* cop_fun: Coprocessor function from function field of instruction */
/* Transmit the cop_fun value to coprocessor z */ endfunction CoprocessorOperation
2.2.2.2 Memory Operation Functions
Regardless of byte ordering (big- or little-endian), the address of a halfword, word, or doubleword is the smallest byte address of the bytes that form the object. For big-endian ordering this is the most-significant byte; for a little-endian ordering this is the least-significant byte.
In the Operation pseudocode for load and store operations, the following functions summarize the handling of virtual addresses and the access of physical memory. The size of the data item to be loaded or stored is passed in the Access- Length field. The valid constant names and values are shown in Table 2.1. The bytes within the addressed unit of memory (word for 32-bit processors or doubleword for 64-bit processors) that are used can be determined directly from the AccessLength and the two or three low-order bits of the address.
2.2.2.2.1 Misaligned Support
MIPS processors originally required all memory accesses to be naturally aligned. MSA (the MIPS SIMD Architec- ture) supported misaligned memory accesses for its 128 bit packed SIMD vector loads and stores, from its introduc- tion in MIPS Release 5. Release 6 requires systems to provide support for misaligned memory accesses for all ordinary memory reference instructions: the system must provide a mechanism to complete a misaligned memory ref- erence for this instruction, ranging from full execution in hardware to trap-and-emulate.
The pseudocode function MisalignedSupport encapsulates the version number check to determine if misalignment is supported for an ordinary memory access.
Figure 2.16 MisalignedSupport Pseudocode Function
predicate MisalignedSupport ()
return Config.AR ≥ 2 // Architecture Revision 2 corresponds to MIPS Release 6.
end function
See Appendix B, “Misaligned Memory Accesses” on page 511 for a more detailed discussion of misalignment, including pseudocode functions for the actual misaligned memory access.
2.2.2.2.2 AddressTranslation
The AddressTranslation function translates a virtual address to a physical address and its cacheability and coherency attribute, describing the mechanism used to resolve the memory reference.
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Given the virtual address vAddr, and whether the reference is to Instructions or Data (IorD), find the corresponding physical address (pAddr) and the cacheability and coherency attribute (CCA) used to resolve the reference. If the vir- tual address is in one of the unmapped address spaces, the physical address and CCA are determined directly by the virtual address. If the virtual address is in one of the mapped address spaces then the TLB or fixed mapping MMU determines the physical address and access type; if the required translation is not present in the TLB or the desired access is not permitted, the function fails and an exception is taken.
Figure 2.17 AddressTranslation Pseudocode Function
(pAddr, CCA) AddressTranslation (vAddr, IorD, LorS)
/* pAddr: physical address */
/* CCA: Cacheability&Coherency Attribute,the method used to access caches*/ /* and memory and resolve the reference */
/* vAddr: virtual address */
/* IorD: Indicates whether access is for INSTRUCTION or DATA */ /* LorS: Indicates whether access is for LOAD or STORE */
/* See the address translation description for the appropriate MMU */
/* type in Volume III of this book for the exact translation mechanism */
endfunction AddressTranslation
2.2.2.2.3 LoadMemory
The LoadMemory function loads a value from memory.
This action uses cache and main memory as specified in both the Cacheability and Coherency Attribute (CCA) and the access (IorD) to find the contents of AccessLength memory bytes, starting at physical location pAddr. The data is returned in a fixed-width naturally aligned memory element (MemElem). The low-order 2 (or 3) bits of the address and the AccessLength indicate which of the bytes within MemElem need to be passed to the processor. If the memory access type of the reference is uncached, only the referenced bytes are read from memory and marked as valid within the memory element. If the access type is cached but the data is not present in cache, an implementation-specific size and alignment block of memory is read and loaded into the cache to satisfy a load reference. At a minimum, this block is the entire memory element.
Figure 2.18 LoadMemory Pseudocode Function
MemElem LoadMemory (CCA, AccessLength, pAddr, vAddr, IorD)
/* MemElem: /*
/*
/*
/* CCA: /*
Data is returned in a fixed width with a natural alignment. The */
width is the same size as the CPU general-purpose register, */
32 or 64 bits, aligned on a 32- or 64-bit boundary, */
respectively. */
Cacheability&CoherencyAttribute=method used to access caches */
and memory and resolve the reference */
/* AccessLength: Length, in bytes, of access */
/* pAddr:
/* vAddr:
/* IorD:
physical address */
virtual address */
Indicates whether access is for Instructions or Data */
endfunction LoadMemory
2.2.2.2.4 StoreMemory
The StoreMemory function stores a value to memory.
The specified data is stored into the physical location pAddr using the memory hierarchy (data caches and main mem- ory) as specified by the Cacheability and Coherency Attribute (CCA). The MemElem contains the data for an aligned, fixed-width memory element (a word for 32-bit processors, a doubleword for 64-bit processors), though only the bytes that are actually stored to memory need be valid. The low-order two (or three) bits of pAddr and the AccessLen- gth field indicate which of the bytes within the MemElem data should be stored; only these bytes in memory will actually be changed.
Figure 2.19 StoreMemory Pseudocode Function
StoreMemory (CCA, AccessLength, MemElem, pAddr, vAddr)
/* CCA: Cacheability&Coherency Attribute, the method used to access */ /* caches and memory and resolve the reference. */
/* AccessLength: Length, in bytes, of access */
/* MemElem: /*
/*
/*
/* /*
/* pAddr:
/* vAddr:
Data in the width and alignment of a memory element. */
The width is the same size as the CPU general */
purpose register, either 4 or 8 bytes, */
aligned on a 4- or 8-byte boundary. For a */
partial-memory-element store, only the bytes that will be*/
stored must be valid.*/
physical address */
virtual address */
endfunction StoreMemory
2.2.2.2.5 Prefetch
The Prefetch function prefetches data from memory.
Prefetch is an advisory instruction for which an implementation-specific action is taken. The action taken may increase performance but must not change the meaning of the program or alter architecturally visible state.
Figure 2.20 Prefetch Pseudocode Function
Prefetch (CCA, pAddr, vAddr, DATA, hint)
/* CCA: Cacheability&Coherency Attribute, the method used to access */ /* caches and memory and resolve the reference. */
/* pAddr: physical address */
/* vAddr: virtual address */
/* DATA: Indicates that access is for DATA */
/* hint: hint that indicates the possible use of the data */
endfunction Prefetch
Table 2.1 lists the data access lengths and their labels for loads and stores.
Table 2.1 AccessLength Specifications for Loads/Stores
2.2 Operation Section Notation and Functions
AccessLength Name
Value
Meaning
DOUBLEWORD
7
8 bytes (64 bits)
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Table 2.1 AccessLength Specifications for Loads/Stores
AccessLength Name
Value
Meaning
SEPTIBYTE
6
7 bytes (56 bits)
SEXTIBYTE
5
6 bytes (48 bits)
QUINTIBYTE
4
5 bytes (40 bits)
WORD
3
4 bytes (32 bits)
TRIPLEBYTE
2
3 bytes (24 bits)
HALFWORD
1
2 bytes (16 bits)
BYTE
0
1 byte (8 bits)
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2.2.2.2.6 SyncOperation
The SyncOperation function orders loads and stores to synchronize shared memory.
This action makes the effects of the synchronizable loads and stores indicated by stype occur in the same order for all processors.
Figure 2.21 SyncOperation Pseudocode Function
SyncOperation(stype)
/* stype: Type of load/store ordering to perform. */
/* Perform implementation-dependent operation to complete the */
/* required synchronization operation */
endfunction SyncOperation
2.2.2.3 Floating Point Functions
The pseudocode shown in below specifies how the unformatted contents loaded or moved to CP1 registers are inter- preted to form a formatted value. If an FPR contains a value in some format, rather than unformatted contents from a load (uninterpreted), it is valid to interpret the value in that format (but not to interpret it in a different format).
2.2.2.3.1 ValueFPR
The ValueFPR function returns a formatted value from the floating point registers.
Figure 2.22 ValueFPR Pseudocode Function
value ValueFPR(fpr, fmt)
/* value: The formattted value from the FPR */
/* fpr:
/* fmt:
/*
/*
The FPR number */
The format of the data, one of: */
S, D, W, L, PS, */
OB, QH, */
UNINTERPRETED_WORD, */
UNINTERPRETED_DOUBLEWORD */
/*
/*
/* The UNINTERPRETED values are used to indicate that the datatype */
/* is not known as, for example, in SWC1 and SDC1 */
case fmt of
S, W, UNINTERPRETED_WORD:
valueFPR FPR[fpr]
D, UNINTERPRETED_DOUBLEWORD: if (FP32RegistersMode 0)
if (fpr0 0) then
valueFPR UNPREDICTABLE
else
valueFPR FPR[fpr1]31..0 FPR[fpr]31..0
endif else
valueFPR FPR[fpr] endif
L:
if (FP32RegistersMode 0) then
valueFPR UNPREDICTABLE else
valueFPR FPR[fpr] endif
DEFAULT:
valueFPR UNPREDICTABLE
endcase
endfunction ValueFPR
The pseudocode shown below specifies the way a binary encoding representing a formatted value is stored into CP1 registers by a computational or move operation. This binary representation is visible to store or move-from instruc- tions. Once an FPR receives a value from the StoreFPR(), it is not valid to interpret the value with ValueFPR() in a different format.
2.2.2.3.2 StoreFPR
Figure 2.23 StoreFPR Pseudocode Function
StoreFPR (fpr, fmt, value)
/* fpr:
/* fmt:
/*
/*
The FPR number */
The format of the data, one of: */
S, D, W, L, PS, */
OB, QH, */
UNINTERPRETED_WORD, */
UNINTERPRETED_DOUBLEWORD */
/*
/*
/* value: The formattted value to be stored into the FPR */
/* The UNINTERPRETED values are used to indicate that the datatype */
/* is not known as, for example, in LWC1 and LDC1 */
case fmt of
S, W, UNINTERPRETED_WORD:
FPR[fpr] value
D, UNINTERPRETED_DOUBLEWORD:
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if (FP32RegistersMode 0) if (fpr0 0) then
UNPREDICTABLE
else
FPR[fpr] UNPREDICTABLE32 value FPR[fpr1] UNPREDICTABLE32 value
endif else
FPR[fpr] value endif
L:
if (FP32RegistersMode 0) then
UNPREDICTABLE
else
FPR[fpr] value
endif
endcase
endfunction StoreFPR
2.2.2.3.3 CheckFPException
The pseudocode shown below checks for an enabled floating point exception and conditionally signals the exception.
Figure 2.24 CheckFPException Pseudocode Function
CheckFPException()
/* A floating point exception is signaled if the E bit of the Cause field is a 1 */ /* (Unimplemented Operations have no enable) or if any bit in the Cause field */ /* and the corresponding bit in the Enable field are both 1 */
if ( (FCSR17 1) or
((FCSR16..12 and FCSR11..7) 0)) ) then
SignalException(FloatingPointException)
endif
endfunction CheckFPException
2.2.2.3.4 FPConditionCode
The FPConditionCode function returns the value of a specific floating point condition code.
Figure 2.25 FPConditionCode Pseudocode Function
tf FPConditionCode(cc)
/* tf: The value of the specified condition code */ /* cc: The Condition code number in the range 0..7 */
if cc = 0 then FPConditionCode FCSR23
else
FPConditionCode FCSR24+cc
31..0 63..32
endif
endfunction FPConditionCode
2.2.2.3.5 SetFPConditionCode
The SetFPConditionCode function writes a new value to a specific floating point condition code.
Figure 2.26 SetFPConditionCode Pseudocode Function
SetFPConditionCode(cc, tf)
if cc = 0 then
FCSR FCSR31..24 || tf || FCSR22..0 else
FCSR FCSR31..25+cc || tf || FCSR23+cc..0 endfunction SetFPConditionCode
2.2.2.4 Pseudocode Functions Related to Sign and Zero Extension 2.2.2.4.1 Sign extension and zero extension in pseudocode
Much pseudocode uses a generic function sign_extend without specifying from what bit position the extension is done, when the intention is obvious. E.g. sign_extend(immediate16) or sign_extend(disp9).
However, sometimes it is necessary to specify the bit position. For example, sign_extend(temp31..0) or the more complicated (offset15)GPRLEN-(16+2) || offset || 02.
The explicit notation sign_extend.nbits(val) or sign_extend(val,nbits) is suggested as a simpli- fication. They say to sign extend as if an nbits-sized signed integer. The width to be sign extended to is usually appar- ent by context, and is usually GPRLEN, 32 or 64 bits. The previous examples then become.
sign_extend(temp31..0)
= sign_extend.32(temp)
and
Note that sign_extend.N(value) extends from bit position N-1, if the bits are numbered 0..N-1 as is typical.
The explicit notations sign_extend.nbits(val) or sign_extend(val,nbits) is used as a simplifica- tion. These notations say to sign extend as if an nbits-sized signed integer. The width to be sign extended to is usually apparent by context, and is usually GPRLEN, 32 or 64 bits.
Figure 2.27 sign_extend Pseudocode Functions
sign_extend.nbits(val) = sign_extend(val,nbits) /* syntactic equivalents */
function sign_extend(val,nbits)
return (valnbits-1)GPRLEN-nbits || valnbits-1..0
end function
The earlier examples can be expressed as
endif
(offset15)GPRLEN-(16+2) || offset || 02 = sign_extend.16(offset)<<2
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(offset15)GPRLEN-(16+2) || offset || 02 = sign_extend.16(offset) << 2)
and
Similarly for zero_extension, although zero extension is less common than sign extension in the MIPS ISA. Floating point may use notations such as zero_extend.fmt corresponding to the format of the FPU instruction.
E.g. zero_extend.S and zero_extend.D are equivalent to zero_extend.32 and zero_extend.64.
Existing pseudocode may use any of these, or other, notations.
2.2.2.4.2 memory_address
The pseudocode function memory_address performs mode-dependent address space wrapping for compatibility between MIPS32 and MIPS64. It is applied to all memory references. It may be specified explicitly in some places, particularly for new memory reference instructions, but it is also declared to apply implicitly to all memory refer- ences as defined below. In addition, certain instructions that are used to calculate effective memory addresses but which are not themselves memory accesses specify memory_address explicitly in their pseudocode.
Figure 2.28 memory_address Pseudocode Function
function memory_address(ea)
return ea
end function
On a 32-bit CPU, memory_address returns its 32-bit effective address argument unaffected.
In addition to the use of memory_address for all memory references (including load and store instructions, LL/ SC), Release 6 extends this behavior to control transfers (branch and call instructions), and to the PC-relative address calculation instructions (ADDIUPC, AUIPC, ALUIPC). In newer instructions the function is explicit in the pseudo- code.
Implicit address space wrapping for all instruction fetches is described by the following pseudocode fragment which should be considered part of instruction fetch:
Figure 2.29 Instruction Fetch Implicit memory_address Wrapping
PC memory_address( PC )
( instruction_data, length ) instruction_fetch( PC ) /* decode and execute instruction */
Implicit address space wrapping for all data memory accesses is described by the following pseudocode, which is inserted at the top of the AddressTranslation pseudocode function:
Figure 2.30 AddressTranslation implicit memory_address Wrapping
(pAddr, CCA) AddressTranslation (vAddr, IorD, LorS) vAddr memory_address(vAddr)
In addition to its use in instruction pseudocode,
2.2.2.5 Miscellaneous Functions
This section lists miscellaneous functions not covered in previous sections.
sign_extend(temp31..0) = sign_extend.32(temp)
2.2.2.5.1 SignalException
The SignalException function signals an exception condition.
This action results in an exception that aborts the instruction. The instruction operation pseudocode never sees a return from this function call.
Figure 2.31 SignalException Pseudocode Function
SignalException(Exception, argument)
/* Exception: The exception condition that exists. */ /* argument: A exception-dependent argument, if any */
endfunction SignalException
2.2.2.5.2 SignalDebugBreakpointException
The SignalDebugBreakpointException function signals a condition that causes entry into Debug Mode from non- Debug Mode.
This action results in an exception that aborts the instruction. The instruction operation pseudocode never sees a return from this function call.
Figure 2.32 SignalDebugBreakpointException Pseudocode Function
SignalDebugBreakpointException()
endfunction SignalDebugBreakpointException
2.2.2.5.3 SignalDebugModeBreakpointException
The SignalDebugModeBreakpointException function signals a condition that causes entry into Debug Mode from Debug Mode (i.e., an exception generated while already running in Debug Mode).
This action results in an exception that aborts the instruction. The instruction operation pseudocode never sees a return from this function call.
Figure 2.33 SignalDebugModeBreakpointException Pseudocode Function
SignalDebugModeBreakpointException()
endfunction SignalDebugModeBreakpointException
2.2.2.5.4 NullifyCurrentInstruction
The NullifyCurrentInstruction function nullifies the current instruction.
The instruction is aborted, inhibiting not only the functional effect of the instruction, but also inhibiting all exceptions detected during fetch, decode, or execution of the instruction in question. For branch-likely instructions, nullification kills the instruction in the delay slot of the branch likely instruction.
Figure 2.34 NullifyCurrentInstruction PseudoCode Function
NullifyCurrentInstruction()
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endfunction NullifyCurrentInstruction
2.2.2.5.5 PolyMult
The PolyMult function multiplies two binary polynomial coefficients.
Figure 2.35 PolyMult Pseudocode Function
PolyMult(x, y) temp 0
for i in 0 .. 31 if xi = 1 then
temp temp xor (y (31-i)..0
endif endfor
PolyMult temp endfunction PolyMult
|| 0i)
2.3 Op and Function Subfield Notation
In some instructions, the instruction subfields op and function can have constant 5- or 6-bit values. When reference is made to these instructions, uppercase mnemonics are used. For instance, in the floating point ADD instruction, op=COP1 and function=ADD. In other cases, a single field has both fixed and variable subfields, so the name con- tains both upper- and lowercase characters.
2.4 FPU Instructions
In the detailed description of each FPU instruction, all variable subfields in an instruction format (such as fs, ft, imme- diate, and so on) are shown in lowercase. The instruction name (such as ADD, SUB, and so on) is shown in upper- case.
For the sake of clarity, an alias is sometimes used for a variable subfield in the formats of specific instructions. For example, rs=base in the format for load and store instructions. Such an alias is always lowercase since it refers to a variable subfield.
Bit encodings for mnemonics are given in Volume I, in the chapters describing the CPU, FPU, MDMX, and MIPS16e instructions.
See “Op and Function Subfield Notation” on page 27 for a description of the op and function subfields.
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Chapter 3
The MIPS32® Instruction Set
3.1 Compliance and Subsetting
To be compliant with the MIPS32 Architecture, designs must implement a set of required features, as described in this document set. To allow implementation flexibility, the MIPS32 Architecture provides subsetting rules. An imple- mentation that follows these rules is compliant with the MIPS32 Architecture as long as it adheres strictly to the rules, and fully implements the remaining instructions. Supersetting of the MIPS32 Architecture is only allowed by adding functions to the SPECIAL2, COP2, or both major opcodes, by adding control for co-processors via the COP2, LWC2, SWC2, LDC2, and/or SDC2, or via the addition of approved Application Specific Extensions.
Release 6 removes all instructions under the SPECIAL2 major opcode, either by removing them or moving them to the COP2 major opcode. All coprocessor 2 support instructions (for example, LWC2) have been moved to the COP2 major opcode. Supersetting of the Release 6 architecture is only allowed in the COP2 major opcode, or via the addi- tion of approved Application Specific Extensions. SPECIAL2 is reserved for MIPS.
Note: The use of COP3 as a customizable coprocessor has been removed in the Release 2 of the MIPS32 architecture. The COP3 is reserved for the future extension of the architecture. Implementations using Release1 of the MIPS32 architecture are strongly discouraged from using the COP3 opcode for a user-available coprocessor as doing so will limit the potential for an upgrade path to a 64-bit floating point unit.
The instruction set subsetting rules are described in the subsections below, and also the following rule:
• Co-dependence of Architecture Features: MIPSr5TM (also called Release 5) and subsequent releases (such as Release 6) include a number of features. Some are optional; some are required. Features provided by a release, such as MIPSr5 or later, whether optional or required, must be consistent. If any feature that is introduced by a particular release is implemented (such as a feature described as part of Release 5 and not any earlier release) then all other features must be implemented in a manner consistent with that release. For example: the VZ and MSA features are introduced by Release 5 but are optional. The FR=1 64-bit FPU register model was optional when introduced earlier, but is now required by Release 5 if any FPU is implemented. If any or all of VZ or MSA are implemented, then Release 5 is implied, and then if an FPU is implemented, it must implement the FR=1 64- bit FPU register model.
3.1.1 Subsetting of Non-Privileged Architecture
• All non-privileged (do not need access to Coprocessor 0) CPU (non-FPU) instructions must be implemented — no subsetting of these are allowed — per the MIPS Instruction Set Architecture release supported.
• If any instruction is subsetted out based on the rules below, an attempt to execute that instruction must cause the appropriate exception (typically Reserved Instruction or Coprocessor Unusable).
• The FPU and related support instructions, such as CPU conditional branches on FPU conditions (pre-Release 6 BC1T/BC1F, Release 6 BC1NEQZ) and CPU conditional moves on FPU conditions (pre-Release 6 MOVT/ MOVF), may be omitted. Software may determine if an FPU is implemented by checking the state of the FP bit in the Config1 CP0 register. Software may determine which FPU data types are implemented by checking the
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appropriate bits in the FIR CP1 register. The following allowable FPU subsets are compliant with the MIPS32 architecture:
• No FPU Config1.FP=0
• FPU with S, and W formats and all supporting instructions.
This 32-bit subset is permitted by Release 6, but prohibited by pre-Release 6 releases. Config1.FP=1, Status.FR=0, FIR.S=FIR.L=1, FIR.D=FIR.L=FIR.PS=0.
• FPU with S, D, W, and L formats and all supporting instructions
Config1.FP=1, Status.FR=(see below), FIR.S=FIR.L=FIR.D=FIR.L=1, FIR.PS=0.
pre-MIPSr5 permits this 64-bit configuration, and allows both FPU register modes. Status.FR=0 support is required but Status.FR=1 support is optional.
MIPSr5 permits this 64-bit configuration, and requires both FPU register modes, i.e. both Status.FR=0 and Status.FR=1 support are required.
Release 6 permits this 64-bit configuration, but requires Status.FR=1 and FIR.F64=1. Release 6 prohibits Status.FR=0 if FIR.D=1 or FIR.L=1.
• FPU with S, D, PS, W, and L formats and all supporting instructions Config1.FP=1, Status.FR=0/1, FIR.S=FIR.L=FIR.D=FIR.L=FIR.PS=1.
Release 6 prohibits this mode, and any mode with FIR.PS=1 paired single support.
• In Release 5 of the Architecture, if floating point is implemented then FR=1 is required. I.e. the 64-bit FPU, with the FR=1 64-bit FPU register model, is required. The FR=0 32-bit FPU register model continues to be required.
• Coprocessor 2 is optional and may be omitted. Software may determine if Coprocessor 2 is implemented by checking the state of the C2 bit in the Config1 CP0 register. If Coprocessor 2 is implemented, the Coprocessor 2 interface instructions (BC2, CFC2, COP2, CTC2, LDC2, LWC2, MFC2, MTC2, SDC2, and SWC2) may be omitted on an instruction-by-instruction basis.
• The caches are optional. The Config1DL and Config1IL fields denote whether the first level caches are present or not.
• Instruction, CP0 Register, and CP1 Control Register fields that are marked “Reserved” or shown as “0” in the description of that field are reserved for future use by the architecture and are not available to implementations. Implementations may only use those fields that are explicitly reserved for implementation dependent use.
• Supported Modules/ASEs are optional and may be subsetted out. In most cases, software may determine if a sup- ported Module/ASE is implemented by checking the appropriate bit in the Config1 or Config3 or Config4 CP0 register. If they are implemented, they must implement the entire ISA applicable to the component, or implement subsets that are approved by the Module/ASE specifications.
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3.1 Compliance and Subsetting
The MIPS32® Instruction Set
• EJTAG is optional and may be subsetted out. If it is implemented, it must implement only those subsets that are approved by the EJTAG specification. If EJTAG is not implemented, the EJTAG instructions (SDBBP and DERET) can be subsetted out.
• In MIPS Release 3, there are two architecture branches (MIPS32/64 and microMIPS32/64). A single device is allowed to implement both architecture branches. The Privileged Resource Architecture (COP0) registers do not mode-switch in width (32-bit vs. 64-bit). For this reason, if a device implements both architecture branches, the address/data widths must be consistent. If a device implements MIPS64 and also implements microMIPS, it must implement microMIPS64 not just microMIPS32. Simiarly, If a device implements microMIPS64 and also imple- ments MIPS32/64, it must implement MIPS64 not just MIPS32.
• Prior to Release 6, the JALX instruction is required if and only if ISA mode-switching is possible. If both of the architecture branches are implemented (MIPS32/64 and microMIPS32/64) or if MIPS16e is implemented then the JALX instructions are required. If only one branch of the architecture family and MIPS16e is not imple- mented then the JALX instruction is not implemented. The JALX instruction was removed in Release 6.
3.2 Alphabetical List of Instructions
The following pages present detailed descriptions of instructions, arranged alphabetical order of opcode mnemonic (except where several similar instructions are described together.)
31 The MIPS32® Instruction Set Manual, Revision 6.06
ABS.fmt IFloating Point Absolute Value
31
26 25 21 20 16 15 11 10 6 5
655556
COP1 010001
fmt
0 00000
fs
fd
ABS 000101
Format: ABS.fmt ABS.S fd, fs
ABS.D fd, fs
ABS.PS fd, fs
Purpose: Floating Point Absolute Value Description: FPR[fd] abs(FPR[fs])
0
MIPS32
MIPS32 MIPS64,MIPS32 Release 2, removed in Release 6
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. ABS.PS takes the absolute value of the two values in FPR fs independently, and ORs together any generated excep- tions.
The Cause bits are ORed into the Flag bits if no exception is taken.
If FIRHas2008=0 or FCSRABS2008=0 then this operation is arithmetic. For this case, any NaN operand signals invalid
operation.
If FCSRABS2008=1 then this operation is non-arithmetic. For this case, both regular floating point numbers and NAN values are treated alike, only the sign bit is affected by this instruction. No IEEE exception can be generated for this case, and the FCSRCause and FCSRFlags fields are not modified.
Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPRE-
DICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
The result of ABS.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model.
ABS.PS is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU. Availability and Compatibility:
ABS.PS has been removed in Release 6.
Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation
The MIPS32® Instruction Set Manual, Revision 6.06 32
ADD
Add Word
31
26 25 21 20 16 15 11 10 6 5
655556
Format: ADD rd, rs, rt Purpose: Add Word
To add 32-bit integers. If an overflow occurs, then trap.
Description: GPR[rd] GPR[rs] + GPR[rt]
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
0
MIPS32
SPECIAL 000000
rs
rt
rd
0 00000
ADD 100000
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rd. Restrictions:
None
Operation:
temp (GPR[rs]31||GPR[rs]31..0) + (GPR[rt]31||GPR[rt]31..0) if temp32 temp31 then
SignalException(IntegerOverflow)
else
GPR[rd] temp endif
Exceptions:
Integer Overflow
Programming Notes:
ADDU performs the same arithmetic operation but does not trap on overflow.
The MIPS32® Instruction Set Manual, Revision 6.06 33
ADD.fmt Floating Point Add
31
26 25 21 20 16 15 11 10 6 5
655556
COP1 010001
fmt
ft
fs
fd
ADD 000000
34
The MIPS32® Instruction Set Manual, Revision 6.06
Format: ADD.fmt
ADD.S fd, fs, ft
ADD.D fd, fs, ft
ADD.PS fd, fs, ft
Purpose: Floating Point Add To add floating point values.
0
MIPS32
MIPS32 MIPS64,MIPS32 Release 2, removed in Release 6
Description: FPR[fd] FPR[fs] + FPR[ft]
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to
the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. ADD.PS adds the upper and lower halves of FPR fs and FPR ft independently, and ORs together any generated excep-
tions.
The Cause bits are ORed into the Flag bits if no exception is taken.
Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPREDICTABLE.
The operands must be values in format fmt. If the fields are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
The result of ADD.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. ADD.PS is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
Availability and Compatibility:
ADD.PS has been removed in Release 6.
Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) fmt ValueFPR(ft, fmt)) Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow
ADDI
Add Immediate Word
31
26 25 21 20 16 15
655 16
Format: ADDI rt, rs, immediate Purpose: Add Immediate Word
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description: GPR[rt] GPR[rs] + immediate
0
MIPS32, removed in Release 6
ADDI 001000
rs
rt
immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
Availability and Compatibility:
This instruction has been removed in Release 6. The encoding has been reused for other instructions introduced by Release 6.
Operation:
temp (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 temp31 then
SignalException(IntegerOverflow)
else
GPR[rt] temp endif
Exceptions:
Integer Overflow
Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.
The MIPS32® Instruction Set Manual, Revision 6.06 35
ADDIU Add Immediate Unsigned Word
31
26 25 21 20 16 15 0
ADDIU 001001
rs
rt
immediate
655 16
Format: ADDIU rt, rs, immediate Purpose: Add Immediate Unsigned Word
To add a constant to a 32-bit integer.
MIPS32
Description: GPR[rt] GPR[rs] + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rt.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp GPR[rs] + sign_extend(immediate) GPR[rt] temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith- metic environments that ignore overflow, such as C language arithmetic.
The MIPS32® Instruction Set Manual, Revision 6.06 36
ADDIUPC Add Immediate to PC (unsigned - non-trapping) 31 2625 21201918 0
652 19
Format: ADDIUPC rs,immediate MIPS32 Release 6 Purpose: Add Immediate to PC (unsigned - non-trapping)
Description: GPR[rs] ( PC + sign_extend( immediate << 2 ) )
This instruction performs a PC-relative address calculation. The 19-bit immediate is shifted left by 2 bits, sign-
extended, and added to the address of the ADDIUPC instruction. The result is placed in GPR rs. Restrictions:
None
Availability and Compatibility:
This instruction is introduced by and required as of Release 6.
Operation:
GPR[rs] ( PC + sign_extend( immediate << 2 ) ) Exceptions:
None
Programming Notes:
The term “unsigned” in this instruction mnemonic is a misnomer. “Unsigned” here means “non-trapping”. It does not trap on a signed 32-bit overflow. ADDIUPC corresponds to unsigned ADDIU, which does not trap on overflow, as opposed to ADDI, which does trap on overflow.
PCREL 111011
rs
ADDIUPC 00
immediate
The MIPS32® Instruction Set Manual, Revision 6.06 37
ADDU Add Unsigned Word
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: ADDU rd, rs, rt MIPS32 Purpose: Add Unsigned Word
To add 32-bit integers.
Description: GPR[rd] GPR[rs] + GPR[rt]
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into
GPR rd.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None
Operation:
temp GPR[rs] + GPR[rt] GPR[rd] temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith- metic environments that ignore overflow, such as C language arithmetic.
SPECIAL 000000
rs
rt
rd
0 00000
ADDU 100001
38
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40
The MIPS32® Instruction Set Manual, Revision 6.06
ALIGN Concatenate two GPRs, and extract a contiguous subset at a byte position
Exceptions:
None
ALNV.PS
IFloating Point Align Variable
StoreFPR(fd, PS,ValueFPR(fs,PS)) else if GPR[rs]2..0 4 then
UNPREDICTABLE
else if BigEndianCPU then
StoreFPR(fd, PS, ValueFPR(fs, PS)31..0 || ValueFPR(ft,PS)63..32)
else
StoreFPR(fd, PS, ValueFPR(ft, PS)31..0 || ValueFPR(fs,PS)63..32)
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
ALNV.PS is designed to be used with LUXC1 to load 8 bytes of data from any 4-byte boundary. For example:
/* Copy T2 bytes (a multiple of 16) of data T0 to T1, T0 unaligned, T1 aligned.
Reads one dw beyond the end of T0. */
LUXC1 F0, 0(T0) /* set up by reading 1st src dw */
LI T3, 0 /* index into src and dst arrays */
ADDIU T4, T0, 8 /* base for odd dw loads */
ADDIU T5, T1, -8/* base for odd dw stores */
LOOP:
LUXC1 F1, T3(T4)
ALNV.PS F2, F0, F1, T0/* switch F0, F1 for little-endian */ SDC1 F2, T3(T1)
ADDIU T3, T3, 16
LUXC1 F0, T3(T0)
ALNV.PS F2, F1, F0, T0/* switch F1, F0 for little-endian */ BNE T3, T2, LOOP
SDC1 F2,T3(T5)
DONE:
ALNV.PS is also useful with SUXC1 to store paired-single results in a vector loop to a possibly misaligned address:
/* T1[i] = T0[i] + F8, T0 aligned, T1 unaligned. */
CVT.PS.S F8, F8, F8/* make addend paired-single */
/* Loop header computes 1st pair into F0, stores high half if T1 */
/* misaligned */
LOOP:
LDC1 F2, T3(T4)/* get T0[i+2]/T0[i+3] */
ADD.PS F1, F2, F8/* compute T1[i+2]/T1[i+3] */
ALNV.PS F3, F0, F1, T1/* align to dst memory */
SUXC1 F3, T3(T1)/* store to T1[i+0]/T1[i+1] */
ADDIU T3, 16 /* i = i + 4 */
LDC1 F2, T3(T0)/* get T0[i+0]/T0[i+1] */
ADD.PS F0, F2, F8/* compute T1[i+0]/T1[i+1] */
ALNV.PS F3, F1, F0, T1/* align to dst memory */
BNE T3, T2, LOOP
SUXC1 F3, T3(T5)/* store to T1[i+2]/T1[i+3] */
/* Loop trailer stores all or half of F0, depending on T1 alignment */
The MIPS32® Instruction Set Manual, Revision 6.06 42
ALUIPC Aligned Add Upper Immediate to PC
31
26 25 21 20 16 15 0
655 16
Format: ALUIPC rs,immediate MIPS32 Release 6 Purpose: Aligned Add Upper Immediate to PC
Description: GPR[rs] ~0x0FFFF & ( PC + sign_extend( immediate << 16 ) )
This instruction performs a PC-relative address calculation. The 16-bit immediate is shifted left by 16 bits, sign- extended, and added to the address of the ALUIPC instruction. The low 16 bits of the result are cleared, that is the result is aligned on a 64K boundary. The result is placed in GPR rs.
Restrictions:
None
Availability and Compatibility:
This instruction is introduced by and required as of Release 6.
Operation:
GPR[rs] ~0x0FFFF & ( PC + sign_extend( immediate << 16 ) ) Exceptions:
None
PCREL 111011
rs
ALUIPC 11111
immediate
The MIPS32® Instruction Set Manual, Revision 6.06 43
AND
and
31
26 25 21 20 16 15 11 10 6 5
655556
Format: AND rd, rs, rt Purpose: and
To do a bitwise logical AND.
0
MIPS32
SPECIAL 000000
rs
rt
rd
0 00000
AND 100100
44
The MIPS32® Instruction Set Manual, Revision 6.06
Description: GPR[rd] GPR[rs] and GPR[rt]
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is
placed into GPR rd. Restrictions:
None
Operation:
GPR[rd] GPR[rs] and GPR[rt]
Exceptions:
None
ANDI
31
26 25 21 20 16 15
655 16
Format: ANDI rt, rs, immediate Purpose: and immediate
To do a bitwise logical AND with a constant
Iand immediate 0
MIPS32
ANDI 001100
rs
rt
immediate
Description: GPR[rt] GPR[rs] and zero_extend(immediate)
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND
operation. The result is placed into GPR rt. Restrictions:
None
Operation:
GPR[rt] GPR[rs] and zero_extend(immediate) Exceptions:
None
The MIPS32® Instruction Set Manual, Revision 6.06 45
ANDI and immediate
46 The MIPS32® Instruction Set Manual, Revision 6.06
AUI
Add Immediate to Upper Bits
31
26 25 21 20 16 15
655 16
Format: AUI rt, rs immediate Purpose: Add Immediate to Upper Bits Add Upper Immediate
Description:
0
MIPS32 Release 6
AUI 001111
rs
rt
immediate
GPR[rt] GPR[rs] + sign_extend(immediate << 16)
The 16 bit immediate is shifted left 16 bits, sign-extended, and added to the register rs, storing the result in rt. In Release 6, LUI is an assembly idiom for AUI with rs=0.
Restrictions:
Availability and Compatibility:
AUI is introduced by and required as of Release 6.
Operation:
GPR[rt] GPR[rs] + sign_extend(immediate << 16) Exceptions:
None.
Programming Notes:
AUI can be used to synthesize large constants in situations where it is not convenient to load a large constant from memory. To simplify hardware that may recognize sequences of instructions as generating large constants, AUI should be used in a stylized manner.
To create an integer:
LUI rd, imm_low(rtmp)
ORI rd, rd, imm_upper
To create a large offset for a memory access whose address is of the form rbase+large_offset: AUI rtmp, rbase, imm_upper
LW rd, (rtmp)imm_low
To create a large constant operand for an instruction of the form rd:=rs+large_immediate or rd:=rs-large_immediate:
AUI rtmp,rs, imm_upper ADDIU rd, rtmp, imm_low
The MIPS32® Instruction Set Manual, Revision 6.06 47
AUIPC Add Upper Immediate to PC
31
26 25 21 20 16 15 0
655 16
Format: AUIPC rs, immediate MIPS32 Release 6 Purpose: Add Upper Immediate to PC
Description: GPR[rs] ( PC + ( immediate << 16 ) )
This instruction performs a PC-relative address calculation. The 16-bit immediate is shifted left by 16 bits, sign-
extended, and added to the address of the AUIPC instruction. The result is placed in GPR rs. Restrictions:
None
Availability and Compatibility:
This instruction is introduced by and required as of Release 6.
PCREL 111011
rs
AUIPC 11110
immediate
48
The MIPS32® Instruction Set Manual, Revision 6.06
Operation:
GPR[rs]
Exceptions:
None
( PC + ( immediate << 16 ) )
B
31
26 25 21 20 16 15
655 16
Format: B offset
Purpose: Unconditional Branch
To do an unconditional branch.
Description: branch
IUnconditional Branch 0
Assembly Idiom
BEQ 000100
0 00000
0 00000
offset
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BEQ r0, r0, offset.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) I+1: PC PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 Kbytes. Use jump (J) or jump register (JR) or the Release 6 branch compact (BC) instructions to branch to addresses outside this range.
The MIPS32® Instruction Set Manual, Revision 6.06 49
BAL
IBranch and Link
pre-Release 6:
31 26 25 21 20 16 15
0
0
REGIMM 000001
00000
BGEZAL 10001
offset
Release 6:
31
26 25 21 20 16 15
655 16
655 16
REGIMM 000001
0 00000
BAL 10001
offset
Format: BALoffset AssemblyIdiomMIPS32,MIPS32Release6 Purpose: Branch and Link
To do an unconditional PC-relative procedure call.
Description: procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2-bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Availability and Compatibility:
Pre-Release 6: BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BGEZAL r0, offset.
Release 6 keeps the BAL special case of BGEZAL, but removes all other instances of BGEZAL. BGEZAL with rs any register other than GPR[0] is required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) GPR[31] PC + 8
I+1: PC PC + target_offset Exceptions:
None
Programming Notes:
BAL without a corresponding return should NOT be used to read the PC. Doing so is likely to cause a performance loss on processors with a return address predictor.
The MIPS32® Instruction Set Manual, Revision 6.06 50
BAL Branch and Link With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or
jump and link register (JALR) instructions for procedure calls to addresses outside this range.
51 The MIPS32® Instruction Set Manual, Revision 6.06
BALC
31
IBranch and Link, Compact 0
MIPS32 Release 6
26 25
6 26
Format: BALC offset
Purpose: Branch and Link, Compact
To do an unconditional PC-relative procedure call.
BALC 111010
offset
Description: procedure_call (no delay slot)
Place the return address link in GPR 31. The return link is the address of the instruction immediately following the
branch, where execution continues after a procedure call. (Because compact branches have no delay slots, see below.)
A 28-bit signed offset (the 26-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
Compact branches do not have delay slots. The instruction after the branch is NOT executed when the branch is taken.
Restrictions:
This instruction is an unconditional, always taken, compact branch. It does not have a forbidden slot, that is, a Reserved Instruction exception is not caused by a Control Transfer Instruction placed in the slot following the branch.
Availability and Compatibility:
This instruction is introduced by and required as of Release 6.
Release 6 instruction BALC occupies the same encoding as pre-Release 6 instruction SWC2. The SWC2 instruction has been moved to the COP2 major opcode in MIPS Release 6.
Exceptions:
None
Operation:
target_offset sign_extend( offset || 02 ) GPR[31] PC+4
PC PC+4 + sign_extend(target_offset)
The MIPS32® Instruction Set Manual, Revision 6.06 52
BC
Branch, Compact
31
26 25
6 26
Format: BC offset Purpose: Branch, Compact
0
MIPS32 Release 6
BC 110010
offset
53
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Description: PC PC+4 + sign_extend( offset << 2)
A 28-bit signed offset (the 26-bit offset field shifted left 2 bits) is added to the address of the instruction following the
branch (not the branch itself), to form a PC-relative effective target address.
Compact branches have no delay slot: the instruction after the branch is NOT executed when the branch is taken.
Restrictions:
This instruction is an unconditional, always taken, compact branch. It does not have a forbidden slot, that is, a Reserved Instruction exception is not caused by a Control Transfer Instruction placed in the slot following the branch.
Availability and Compatibility:
This instruction is introduced by and required as of Release 6.
Release 6 instruction BC occupies the same encoding as pre-Release 6 instruction LWC2. The LWC2 instruction has been moved to the COP2 major opcode in MIPS Release 6.
Exceptions:
None
Operation:
target_offset sign_extend( offset || 02 ) PC ( PC+4 + sign_extend(target_offset) )
BC1EQZ BC1NEZ IBranch if Coprocessor 1 (FPU) Register Bit 0 Equal/Not Equal to Zero
31
26 25 21 20 16 15
655 16
Format: BC1EQZ BC1NEZ BC1EQZ ft, offset
BC1NEZ ft, offset
Purpose: Branch if Coprocessor 1 (FPU) Register Bit 0 Equal/Not Equal to Zero BC1EQZ: Branch if Coprocessor 1 (FPU) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Coprocessor 1 (FPR) Register Bit 0 is Not Equal to Zero
Description:
BC1EQZ: if FPR[ft] & 1 = 0 then branch BC1NEZ: if FPR[ft] & 1 0 then branch
The condition is evaluated on FPU register ft.
• For BC1EQZ, the condition is true if and only if bit 0 of the FPU register ft is zero.
• For BC1NEZ, the condition is true if and only if bit 0 of the FPU register ft is non-zero.
If the condition is false, the branch is not taken, and execution continues with the next instruction.
0
MIPS32 Release 6 MIPS32 Release 6
COP1 010001
BC1EQZ 01001
ft
offset
COP1 010001
BC1NEZ 01101
ft
offset
1.
A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address. Execute the instruction in the delay slot before the instruction at the target.
Restrictions:
If access to Coprocessor 1 is not enabled, a Coprocessor Unusable Exception is signaled.
Because these instructions BC1EQZ and BC1NEZ do not depend on a particular floating point data type, they operate whenever Coprocessor 1 is enabled.
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 implementations are required to signal a Reserved Instruction exception.
Availability and Compatibility:
These instructions are introduced by and required as of Release 6.
Exceptions:
Coprocessor Unusable1
Operation:
In Release 6, BC1EQZ and BC1NEZ are required, if the FPU is implemented. They must not signal a Reserved Instruction exception. They can signal a Coprocessor Unusable Exception.
The MIPS32® Instruction Set Manual, Revision 6.06 54
55
The MIPS32® Instruction Set Manual, Revision 6.06
BC1EQZ BC1NEZ Branch if Coprocessor 1 (FPU) Register Bit 0 Equal/Not Equal to Zero
tmp ValueFPR(ft, UNINTERPRETED_WORD) BC1EQZ: cond tmp & 1 = 0
BC1NEZ: cond tmp & 1 0
if cond then
I: target_PC ( PC+4 + sign_extend( offset << 2 ) I+1: PC target_PC
Programming Notes:
Release 6: These instructions, BC1EQZ and BC1NEZ, replace the pre-Release 6 instructions BC1F and BC1T. These Release 6 FPU branches depend on bit 0 of the scalar FPU register.
Note: BC1EQZ and BC1NEZ do not have a format or data type width. The same instructions are used for branches based on conditions involving any format, including 32-bit S (single precision) and W (word) format, and 64-bit D (double precision) and L (longword) format, as well as 128-bit MSA. The FPU scalar comparison instructions CMP.condn fmt produce an all ones or all zeros truth mask of their format width with the upper bits (where applica- ble) UNPREDICTABLE. BC1EQZ and BC1NEZ consume only bit 0 of the CMP.condn fmt output value, and there- fore operate correctly independent of fmt.
BC1F
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1F offset (cc = 0 implied) BC1F cc, offset
Purpose: Branch on FP False
To test an FP condition code and do a PC-relative conditional branch.
Description: if FPConditionCode(cc) = 0 then branch
IBranch on FP False 0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP1 010001
BC 01000
cc
nd 0
tf 0
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit cc is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: condition FPConditionCode(cc) = 0
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
This instruction has been removed in Release 6 and has been replaced by the BC1EQZ instruction. Refer to the ‘BC1EQZ’ instruction in this manual for more information.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are
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BC1F
Branch on FP False
valid for MIPS IV and MIPS32.
BC1FL IBranch on FP False Likely
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1FL offset (cc = 0 implied) BC1FL cc, offset
0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP1 010001
BC 01000
cc
nd 1
tf 0
offset
Purpose: Branch on FP False Likely
To test an FP condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only
if the branch is taken.
Description: if FPConditionCode(cc) = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con- dition Code bit cc is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition FPConditionCode(cc) = 0
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
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BC1FL Branch on FP False Likely Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC1F instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
BC1T
31
26 25 21 20 18 17 16 15
65311 16
Format: BC1T offset (cc = 0 implied) BC1T cc, offset
Purpose: Branch on FP True
To test an FP condition code and do a PC-relative conditional branch.
Description: if FPConditionCode(cc) = 1 then branch
IBranch on FP True 0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP1 010001
BC 01000
cc
nd 0
tf 1
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con- dition code bit cc is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: condition FPConditionCode(cc) = 1
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
This instruction has been replaced by the BC1NEZ instruction. Refer to the ‘BC1NEZ’ instruction in this manual for more information.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
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BC1T Branch on FP True
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
BC1TL
31
IBranch on FP True Likely 0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
26 25 21 20 18 17 16 15
65311 16
Format: BC1TL offset (cc = 0 implied) BC1TL cc, offset
COP1 010001
BC 01000
cc
nd 1
tf 1
offset
Purpose: Branch on FP True Likely
To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if
the branch is taken.
Description: if FPConditionCode(cc) = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con- dition Code bit cc is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition FPConditionCode(cc) = 1
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Unimplemented Operation
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
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BC1TL Branch on FP True Likely Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC1T instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
BC2EQZ BC2NEZ IBranch if Coprocessor 2 Condition (Register) Equal/Not Equal to Zero
31
26 25 21 20 16 15
655 16
Format: BC2EQZ BC2NEZ BC2EQZ ct, offset BC2NEZ ct, offset
Purpose: Branch if Coprocessor 2 Condition (Register) Equal/Not Equal to Zero BC2EQZ: Branch if Coprocessor 2 Condition (Register) is Equal to Zero BC2NEZ: Branch if Coprocessor 2 Condition (Register) is Not Equal to Zero
Description:
BC2EQZ: if COP2Condition[ct] = 0 then branch BC2NEZ: if COP2Condition[ct] 0 then branch
The 5-bit field ct specifies a coprocessor 2 condition.
• For BC2EQZ if the coprocessor 2 condition is true the branch is taken.
• For BC2NEZ if the coprocessor 2 condition is false the branch is taken.
0
MIPS32 Release 6 MIPS32 Release 6
COP2 010010
BC2EQZ 01001
ct
offset
COP2 010010
BC2NEZ 01101
ct
offset
A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address. Execute the instruction in the delay slot before the instruction at the target.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 implementations are required to signal a Reserved Instruction exception.
If access to Coprocessor 2 is not enabled, a Coprocessor Unusable Exception is signaled.
Availability and Compatibility:
These instructions are introduced by and required as of Release 6.
Exceptions:
Coprocessor Unusable, Reserved Instruction
Operation:
tmpcond Coprocessor2Condition(ct) if BC2EQZ then
tmpcond not(tmpcond) endif
if tmpcond then
PC PC+4 + sign_extend( immediate << 2 ) )
endif
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BC2EQZ BC2NEZ Branch if Coprocessor 2 Condition (Register) Equal/Not Equal to Zero Implementation Notes:
As of Release 6 these instructions, BC2EQZ and BC2NEZ, replace the pre-Release 6 instructions BC2F and BC2T, which had a 3-bit condition code field (as well as nullify and true/false bits). Release 6 makes all 5 bits of the ct con- dition code available to the coprocessor designer as a condition specifier.
A customer defined coprocessor instruction set can implement any sort of condition it wants. For example, it could implement up to 32 single-bit flags, specified by the 5-bit field ct. It could also implement conditions encoded as values in a coprocessor register (such as testing the least significant bit of a coprocessor register) as done by Release 6 instructions BC1EQZ/BC1NEZ.
BC2F
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2F offset (cc = 0 implied) BC2F cc, offset
Purpose: Branch on COP2 False
To test a COP2 condition code and do a PC-relative conditional branch.
Description: if COP2Condition(cc) = 0 then branch
IBranch on COP2 False 0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP2 010010
BC 01000
cc
nd 0
tf 0
offset
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by cc is false (0), the program branches to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: condition COP2Condition(cc) = 0
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
This instruction has been replaced by the BC2EQZ instruction. Refer to the ‘BC2EQZ’ instruction in this manual for more information.
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BC2FL Branch on COP2 False Likely
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2FL offset (cc = 0 implied) BC2FL cc, offset
0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP2 010010
BC 01000
cc
nd 1
tf 0
offset
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Purpose: Branch on COP2 False Likely
To test a COP2 condition code and make a PC-relative conditional branch; execute the instruction in the delay slot
only if the branch is taken.
Description: if COP2Condition(cc) = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by cc is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: condition COP2Condition(cc) = 0
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions,
15
BC2FL IBranch on COP2 False Likely as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC2F instruction instead.
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BC2T
Branch on COP2 True
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2T offset (cc = 0 implied) BC2T cc, offset
Purpose: Branch on COP2 True
To test a COP2 condition code and do a PC-relative conditional branch.
Description: if COP2Condition(cc) = 1 then branch
0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP2 010010
BC 01000
cc
nd 0
tf 1
offset
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An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by cc is true (1), the program branches to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: condition COP2Condition(cc) = 1
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
This instruction has been replaced by the BC2NEZ instruction. Refer to the ‘BC2NEZ’ instruction in this manual for more information.
15
BC2TL IBranch on COP2 True Likely
31
26 25 21 20 18 17 16 15
65311 16
Format: BC2TL offset (cc = 0 implied) BC2TL cc, offset
0
MIPS32, removed in Release 6 MIPS32, removed in Release 6
COP2 010010
BC 01000
cc
nd 1
tf 1
offset
Purpose: Branch on COP2 True Likely
To test a COP2 condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only
if the branch is taken.
Description: if COP2Condition(cc) = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the COP2 condition specified by cc is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC2F, BC2FL, BC2T, and BC2TL have specific values for tf and nd.
I: condition COP2Condition(cc) = 1
target_offset (offset )GPRLEN-(16+2) || offset || 02
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
Coprocessor Unusable, Reserved Instruction
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions,
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BC2TL Branch on COP2 True Likely as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC2T instruction instead.
BEQ
31
26 25 21 20 16 15
655 16
Format: BEQ rs, rt, offset Purpose: Branch on Equal
To compare GPRs then do a PC-relative conditional branch.
IBranch on Equal 0
MIPS32
BEQ 000100
rs
rt
offset
Description: if GPR[rs] = GPR[rt] then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are equal, branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition (GPR[rs] = GPR[rt])
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
BEQ r0, r0 offset, expressed as B offset, is the assembly idiom used to denote an unconditional branch.
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BEQL
Branch on Equal Likely
31
26 25 21 20 16 15
655 16
Format: BEQL rs, rt, offset Purpose: Branch on Equal Likely
0
MIPS32, removed in Release 6
BEQL 010100
rs
rt
offset
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To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] = GPR[rt] then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are equal, branch to the target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition (GPR[rs] = GPR[rt])
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BEQ instruction instead.
BEQL IBranch on Equal Likely Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
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BGEZ Branch on Greater Than or Equal to Zero
31
26 25 21 20 16 15 0
655 16
Format: BGEZ rs, offset MIPS32 Purpose: Branch on Greater Than or Equal to Zero
To test a GPR then do a PC-relative conditional branch
Description: if GPR[rs] 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
REGIMM 000001
rs
BGEZ 00001
offset
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BGEZAL IBranch on Greater Than or Equal to Zero and Link
31
26 25 21 20 16 15
655 16
Format: BGEZAL rs, offset
Purpose: Branch on Greater Than or Equal to Zero and Link
To test a GPR then do a PC-relative conditional procedure call
0
MIPS32, removed in Release 6
REGIMM 000001
rs
BGEZAL 10001
offset
Description: if GPR[rs] 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed.
Availability and Compatibility
This instruction has been removed in Release 6 with the exception of special case BAL (unconditional Branch and Link) which was an alias for BGEZAL with rs=0.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Branch-and-link Restartability: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot or forbidden slot.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
GPR[31] PC + 8
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
BGEZAL r0, offset, expressed as BAL offset, is the assembly idiom used to denote a PC-relative branch and link. BAL is used in a manner similar to JAL, but provides PC-relative addressing and a more limited target PC range.
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B{LE,GE,GT,LT,EQ,NE}ZALC ICompact Zero-Compare and Branch-and-Link Instructions
31
26 25 21 20 16 15
0
POP06 000110
BLEZALC
00000 rt 00000
offset
POP06 000110
BGEZALC rs = rt 00000
rs
rt
offset
POP07 000111
BGTZALC
00000 rt 00000
offset
POP07 000111
BLTZALC rs = rt 00000
rs
rt
offset
POP10 001000
00000
BEQZALC rs < rt
rt 00000
offset
POP30 011000
00000
BNEZALC rs < rt
rt 00000
offset
Format:
B{LE,GE,GT,LT,EQ,NE}ZALC
BLEZALC rt, offset
BGEZALC rt, offset
BGTZALC rt, offset
BLTZALC rt, offset
BEQZALC rt, offset
BNEZALC rt, offset
655 16
Purpose: Compact Zero-Compare and Branch-and-Link Instructions BLEZALC: Compact branch-and-link if GPR rt is less than or equal to zero BGEZALC: Compact branch-and-link if GPR rt is greater than or equal to zero BGTZALC: Compact branch-and-link if GPR rt is greater than zero BLTZALC: Compact branch-and-link if GPR rt is less than to zero BEQZALC: Compact branch-and-link if GPR rt is equal to zero
BNEZALC: Compact branch-and-link if GPR rt is not equal to zero
Description: if condition(GPR[rt]) then procedure_call branch (no delay slot) The condition is evaluated. If the condition is true, the branch is taken.
Places the return address link in GPR 31. The return link is the address of the instruction immediately following the branch, where execution continues after a procedure call.
The return address link is unconditionally updated.
A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
The MIPS32® Instruction Set Manual, Revision 6.06 77
MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6
78
The MIPS32® Instruction Set Manual, Revision 6.06
B{LE,GE,GT,LT,EQ,NE}ZALC Compact Zero-Compare and Branch-and-Link Instructions
BLEZALC: the condition is true if and only if GPR rt is less than or equal to zero. BGEZALC: the condition is true if and only if GPR rt is greater than or equal to zero. BLTZALC: the condition is true if and only if GPR rt is less than zero.
BGTZALC: the condition is true if and only if GPR rt is greater than zero. BEQZALC: the condition is true if and only if GPR rt is equal to zero.
BNEZALC: the condition is true if and only if GPR rt is not equal to zero.
Compact branches do not have delay slots. The instruction after a compact branch is only executed if the branch is not
taken.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is executed in the forbidden slot of a compact branch, Release 6 implementa- tions are required to signal a Reserved Instruction exception, but only when the branch is not taken.
Branch-and-link Restartability: GPR 31 must not be used for the source registers, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot or forbidden slot.
Availability and Compatibility:
These instructions are introduced by and required as of Release 6.
• BEQZALC reuses the opcode assigned to pre-Release 6 ADDI.
• BNEZALC reuses the opcode assigned to pre-Release 6 MIPS64 DADDI.
These instructions occupy primary opcode spaces originally allocated to other instructions. BLEZALC and BGEZALC have the same primary opcode as BLEZ, and are distinguished by rs and rt register numbers. Similarly, BGTZALC and BLTZALC have the same primary opcode as BGTZ, and are distinguished by register fields. BEQZALC and BNEZALC reuse the primary opcodes ADDI and DADDI.
Exceptions:
None
Operation:
GPR[31] PC+4
target_offset sign_extend( offset || 02 )
BLTZALC: cond GPR[rt] < 0 BLEZALC: cond GPR[rt] 0 BGEZALC: cond GPR[rt] 0 BGTZALC: cond GPR[rt] > 0 BEQZALC: cond GPR[rt] = 0 BNEZALC: cond GPR[rt] 0
if cond then
PC ( PC+4+ sign_extend(
endif
Programming Notes:
target_offset ) )
Software that performs incomplete instruction decode may incorrectly decode these new instructions, because of their
B{LE,GE,GT,LT,EQ,NE}ZALC ICompact Zero-Compare and Branch-and-Link Instructions
very tight encoding. For example, a disassembler might look only at the primary opcode field, instruction bits 31-26, to decode BLEZL without checking that the “rt” field is zero. Such software violated the pre-Release 6 architecture specification.
With the 16-bit offset shifted left 2 bits and sign extended, the conditional branch range is ± 128 KBytes. Other instructions such as pre-Release 6 JAL and JALR, or Release 6 JIALC and BALC have larger ranges. In particular, BALC, with a 26-bit offset shifted by 2 bits, has a 28-bit range, ± 128 MBytes. Code sequences using AUIPC and JIALC allow still greater PC-relative range.
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BGEZALL IBranch on Greater Than or Equal to Zero and Link Likely
31
26 25 21 20 16 15 0
655 16
Format: BGEZALL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Greater Than or Equal to Zero and Link Likely
To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
Description: if GPR[rs] 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Branch-and-link Restartability: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
GPR[31] PC + 8
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
REGIMM 000001
rs
BGEZALL 10011
offset
The MIPS32® Instruction Set Manual, Revision 6.06 80
BGEZALL IBranch on Greater Than or Equal to Zero and Link Likely encouraged to use the BGEZAL instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
The MIPS32® Instruction Set Manual, Revision 6.06 81
B
31
26 25 21 20 16 15
0
POP26 010110
BLEZC
00000
rt 00000
offset
POP26 010110
BGEZC rs = rt
rs 00000 rt 00000
offset
POP26 010110
BGEC (BLEC) rs rt
rs 00000 rt 00000
offset
POP27 010111
BGTZC
00000
rt 00000
offset
POP27 010111
BLTZC rs = rt
rs 00000 rt 00000
offset
POP27 010111
BLTC (BGTC) rs rt
rs 00000 rt 00000
offset
POP06 000110
BGEUC (BLEUC) rs rt
rs 00000 rt 00000
offset
POP07 000111
BLTUC (BGTUC) rs rt
rs 00000 rt 00000
offset
POP10 001000
BEQC rs < rt
rs 00000 rt 00000
offset
POP30 011000
BNEC rs < rt
rs 00000 rt 00000
offset
31
655 16 26 25 21 20
65 21
Format: B
Purpose: Compact Compare-and-Branch Instructions Format Details:
Equal/Not-Equal register-register compare and branch with 16-bit offset:
BEQC rs, rt, offset
BNEC rs, rt, offset
0
MIPS32 Release 6
MIPS32 Release 6 MIPS32 Release 6
POP66 110110
BEQZC rs 00000 rs
offset
POP76 111110
BNEZC rs 00000 rs
offset
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Compact Compare-and-Branch Instructions
Signed register-register compare and branch with 16-bit offset:
BLTC rs, rt, offset
BGEC rs, rt, offset
Unsigned register-register compare and branch with 16-bit offset:
BLTUC rs, rt, offset
BGEUC rs, rt, offset
Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BGTC rt, rs, offset
BLEC rt, rs, offset
BGTUC rt, rs, offset
BLEUC rt, rs, offset
Signed Compare register to Zero and branch with 16-bit offset:
BLTZC rt, offset
BLEZC rt, offset
BGEZC rt, offset
BGTZC rt, offset
Equal/Not-equal Compare register to Zero and branch with 21-bit offset:
BEQZC rs, offset
BNEZC rs, offset
MIPS32 Release 6 MIPS32 Release 6
MIPS32 Release 6 MIPS32 Release 6
Assembly Idiom Assembly Idiom Assembly Idiom Assembly Idiom
MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6 MIPS32 Release 6
MIPS32 Release 6 MIPS32 Release 6
Description: if condition(GPR[rs] and/or GPR[rt]) then compact branch (no delay slot) The condition is evaluated. If the condition is true, the branch is taken.
An 18/23-bit signed offset (the 16/21-bit offset field shifted left 2 bits) is added to the address of the instruction fol- lowing the branch (not the branch itself), to form a PC-relative effective target address.
The offset is 16 bits for most compact branches, including BLTC, BLEC, BGEC, BGTC, BNEQC, BNEC, BLTUC, BLEUC, BGEUC, BGTC, BLTZC, BLEZC, BGEZC, BGTZC. The offset is 21 bits for BEQZC and BNEZC.
Compact branches have no delay slot: the instruction after the branch is NOT executed if the branch is taken. The conditions are as follows:
Equal/Not-equal register-register compare-and-branch with 16-bit offset: BEQC: Compact branch if GPRs are equal
BNEC: Compact branch if GPRs are not equal
Signed register-register compare and branch with 16-bit offset:
BLTC: Compact branch if GPR rs is less than GPR rt
BGEC: Compact branch if GPR rs is greater than or equal to GPR rt
Unsigned register-register compare and branch with 16-bit offset:
BLTUC: Compact branch if GPR rs is less than GPR rt, unsigned
BGEUC: Compact branch if GPR rs is greater than or equal to GPR rt, unsigned
Assembly Idioms with Operands Reversed:
BLEC: Compact branch if GPR rt is less than or equal to GPR rs (alias for BGEC)
BGTC: Compact branch if GPR rt is greater than GPR rs (alias for BLTC)
BLEUC: Compact branch if GPR rt is less than or equal to GPR rt, unsigned (alias for BGEUC) BGTUC: Compact branch if GPR rt is greater than GPR rs, unsigned (alias for BLTUC)
B
Compare register to zero and branch with 16-bit offset:
BLTZC: Compact branch if GPR rt is less than zero
BLEZC: Compact branch if GPR rt is less than or equal to zero BGEZC: Compact branch if GPR rt is greater than or equal to zero BGTZC: Compact branch if GPR rt is greater than zero
Compare register to zero and branch with 21-bit offset:
BEQZC: Compact branch if GPR rs is equal to zero BNEZC: Compact branch if GPR rs is not equal to zero
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is placed in the forbidden slot of a compact branch, Release 6 implementations are required to signal a Reserved Instruction exception, but only when the branch is not taken.
Availability and Compatibility:
These instructions are introduced by and required as of Release 6.
• BEQZC reuses the opcode assigned to pre-Release 6 LDC2.
• BNEZC reuses the opcode assigned to pre-Release 6 SDC2.
• BEQC reuses the opcode assigned to pre-Release 6 ADDI.
• BNEC reuses the opcode assigned to pre-Release 6 MIPD64 DADDI.
Exceptions:
None
Operation:
target_offset sign_extend( offset || 02 )
/* Register-register compare and branch, 16 bit offset: */ /* Equal / Not-Equal */
BEQC: cond GPR[rs] = GPR[rt]
BNEC: cond GPR[rs] GPR[rt]
/* Signed */
BLTC: cond GPR[rs] < GPR[rt]
BGEC: cond GPR[rs] GPR[rt]
/* Unsigned: */
BLTUC: cond unsigned(GPR[rs]) < unsigned(GPR[rt]) BGEUC: cond unsigned(GPR[rs]) unsigned(GPR[rt])
/* Compare register to zero, small offset: */ BLTZC: cond GPR[rt] < 0
BLEZC: cond GPR[rt] 0
BGEZC: cond GPR[rt] 0
BGTZC: cond GPR[rt] > 0
/* Compare register to zero, large offset: */ BEQZC: cond GPR[rs] = 0
BNEZC: cond GPR[rs] 0
if cond then
PC ( PC+4+ sign_extend( offset ) )
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B
Programming Notes:
Legacy software that performs incomplete instruction decode may incorrectly decode these new instructions, because of their very tight encoding. For example, a disassembler that looks only at the primary opcode field (instruction bits 31-26) to decode BLEZL without checking that the “rt” field is zero violates the pre-Release 6 architecture specifica- tion. Complete instruction decode allows reuse of pre-Release 6 BLEZL opcode for Release 6 conditional branches.
BGEZL IBranch on Greater Than or Equal to Zero Likely
31
26 25 21 20 16 15 0
655 16
Format: BGEZL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Greater Than or Equal to Zero Likely
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than or equal to zero (sign bit is 0), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BGEZ instruction instead.
REGIMM 000001
rs
BGEZL 00011
offset
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BGEZL Branch on Greater Than or Equal to Zero Likely Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
87 The MIPS32® Instruction Set Manual, Revision 6.06
BGTZ IBranch on Greater Than Zero
31
26 25 21 20 16 15 0
655 16
Format: BGTZ rs, offset MIPS32 Purpose: Branch on Greater Than Zero
To test a GPR then do a PC-relative conditional branch.
Description: if GPR[rs] > 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] > 0GPRLEN
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
BGTZ 000111
rs
0 00000
offset
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BGTZL Branch on Greater Than Zero Likely
31
26 25 21 20 16 15 0
655 16
Format: BGTZL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Greater Than Zero Likely
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] > 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not exe- cuted.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] > 0GPRLEN
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
BGTZL 010111
rs
0 00000
offset
89
The MIPS32® Instruction Set Manual, Revision 6.06
BGTZL IBranch on Greater Than Zero Likely encouraged to use the BGTZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
The MIPS32® Instruction Set Manual, Revision 6.06 90
BGTZL Branch on Greater Than Zero Likely
91 The MIPS32® Instruction Set Manual, Revision 6.06
BITSWAP ISwaps (reverses) bits in each byte
31
26 25 21 20 16 15 11 10 6 5 0
655556
Format: BITSWAP
BITSWAP rd,rt MIPS32 Release 6
Purpose: Swaps (reverses) bits in each byte
Description: GPR[rd].byte(i) reverse_bits_in_byte(GPR[rt].byte(i)), for all
bytes i
Each byte in input GPR rt is moved to the same byte position in output GPR rd, with bits in each byte reversed. BITSWAP operates on all 4 bytes of a 32-bit GPR on a 32-bit CPU.
Restrictions:
None.
Availability and Compatibility:
The BITSWAP instruction is introduced by and required as of Release 6.
Operation:
BITSWAP:
for i in 0 to 3 do /* for all bytes in 32-bit GPR width */
tmp.byte(i) reverse_bits_in_byte( GPR[rt].byte(i) ) endfor
GPR[rd] tmp where
function reverse_bits_in_byte(inbyte) outbyte7 inbyte0
outbyte6 inbyte1
outbyte5 inbyte2
outbyte4 inbyte3 outbyte3 inbyte4 outbyte2 inbyte5 outbyte1 inbyte6 outbyte0 inbyte7 return outbyte
end function
Exceptions:
None
Programming Notes:
The Release 6 BITSWAP instruction corresponds to the DSP Module BITREV instruction, except that the latter bit- reverses the least-significant 16-bit halfword of the input register, zero extending the rest, while BITSWAP operates on 32-bits.
SPECIAL3 011111
00000
rt
rd
BITSWAP 00000
BSHFL 100000
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BITSWAP Swaps (reverses) bits in each byte
93 The MIPS32® Instruction Set Manual, Revision 6.06
BLEZ
IBranch on Less Than or Equal to Zero
31
26 25 21 20 16 15 0
655 16
Format: BLEZ rs, offset MIPS32 Purpose: Branch on Less Than or Equal to Zero
To test a GPR then do a PC-relative conditional branch.
Description: if GPR[rs] 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
BLEZ 000110
rs
0 00000
offset
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BLEZL Branch on Less Than or Equal to Zero Likely
31
26 25 21 20 16 15 0
655 16
Format: BLEZL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Less Than or Equal to Zero Likely
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] 0GPRLEN
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is
BLEZL 010110
rs
0 00000
offset
95
The MIPS32® Instruction Set Manual, Revision 6.06
BLEZL IBranch on Less Than or Equal to Zero Likely encouraged to use the BLEZ instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
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BLTZ
Branch on Less Than Zero
31
26 25 21 20 16 15 0
655 16
Format: BLTZ rs, offset MIPS32 Purpose: Branch on Less Than Zero
To test a GPR then do a PC-relative conditional branch.
Description: if GPR[rs] < 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] < 0GPRLEN
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
REGIMM 000001
rs
BLTZ 00000
offset
97
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BLTZAL IBranch on Less Than Zero and Link
31
26 25 21 20 16 15
655 16
Format: BLTZAL rs, offset
Purpose: Branch on Less Than Zero and Link
To test a GPR then do a PC-relative conditional procedure call.
0
MIPS32, removed in Release 6
REGIMM 000001
rs
BLTZAL 10000
offset
Description: if GPR[rs] < 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed.
Availability and Compatibility:
This instruction has been removed in Release 6.
The special case BLTZAL r0, offset, has been retained as NAL in Release 6.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Branch-and-link Restartability: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when re-executed. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by re-executing the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] < 0GPRLEN
GPR[31] PC + 8
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
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BLTZALL Branch on Less Than Zero and Link Likely
31
26 25 21 20 16 15 0
655 16
Format: BLTZALL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Less Than Zero and Link Likely
To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
Description: if GPR[rs] < 0 then procedure_call_likely
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a
branch or jump.
Branch-and-link Restartability: GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] < 0GPRLEN
GPR[31] PC + 8
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump and link (JAL) or The MIPS32® Instruction Set Manual, Revision 6.06
REGIMM 000001
rs
BLTZALL 10010
offset
99
BLTZALL IBranch on Less Than Zero and Link Likely jump and link register (JALR) instructions for procedure calls to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLTZAL instruction instead.
Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
The MIPS32® Instruction Set Manual, Revision 6.06 100
BLTZL Branch on Less Than Zero Likely
31
26 25 21 20 16 15 0
655 16
Format: BLTZL rs, offset MIPS32, removed in Release 6 Purpose: Branch on Less Than Zero Likely
To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] < 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition GPR[rs] < 0GPRLEN
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BLTZ instruction instead.
REGIMM 000001
rs
BLTZL 00010
offset
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BLTZL IBranch on Less Than Zero Likely Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
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BNE
Branch on Not Equal
31
26 25 21 20 16 15
655 16
Format: BNE rs, rt, offset Purpose: Branch on Not Equal
To compare GPRs then do a PC-relative conditional branch
0
MIPS32
BNE 000101
rs
rt
offset
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Description: if GPR[rs] GPR[rt] then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI) is placed in the delay slot of a branch or jump.
Release 6: If a control transfer instruction (CTI) is executed in the delay slot of a branch or jump, Release 6 imple- mentations are required to signal a Reserved Instruction exception.
Operation:
I: target_offset sign_extend(offset || 02) condition (GPR[rs] GPR[rt])
I+1: if condition then
PC PC + target_offset
endif
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
BNEL IBranch on Not Equal Likely
31
26 25 21 20 16 15 0
655 16
Format: BNEL rs, rt, offset MIPS32, removed in Release 6 Purpose: Branch on Not Equal Likely
To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] GPR[rt] then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following
the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the
delay slot of a branch or jump.
Availability and Compatibility:
This instruction has been removed in Release 6.
Operation:
I: target_offset sign_extend(offset || 02) condition (GPR[rs] GPR[rt])
I+1: if condition then
PC PC + target_offset
else
NullifyCurrentInstruction()
endif
Exceptions:
None
Implementation Note:
Some implementations always predict that the branch will be taken, and do not use nor do they update the branch internal processor branch prediction tables for this instruction. To maintain performance compatibility, future imple- mentations are encouraged to do the same.
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is 128 KBytes. Use jump (J) or jump register (JR) to branch to addresses outside this range.
In Pre-Release 6 implementations, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BNE instruction instead.
BNEL 010101
rs
rt
offset
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BNEL Branch on Not Equal Likely Historical Information:
In the MIPS I architecture, this instruction signaled a Reserved Instruction exception.
105 The MIPS32® Instruction Set Manual, Revision 6.06
BNEL IBranch on Not Equal Likely
The MIPS32® Instruction Set Manual, Revision 6.06 106
BOVC BNVC Branch on Overflow, Compact; Branch on No Overflow, Compact
31
26 25 21 20 16 15
655 16
Format: BOVC BNVC
BOVC rs,rt,offset
BNVC rs,rt,offset
Purpose: Branch on Overflow, Compact; Branch on No Overflow, Compact BOVC: Detect overflow for add (signed 32 bits) and branch if overflow. BNVC: Detect overflow for add (signed 32 bits) and branch if no overflow.
0
MIPS32 Release 6 MIPS32 Release 6
POP10 001000
BOVC rs >=rt
offset
rs
rt
POP30 011000
BNVC rs>=rt
offset
rs
rt
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Description:branchif/if-not NotWordValue(GPR[rs]+GPR[rt])
• BOVC performs a signed 32-bit addition of rs and rt. BOVC discards the sum, but detects signed 32-bit inte-
ger overflow of the sum, and branches if such overflow is detected.
• BNVC performs a signed 32-bit addition of rs and rt. BNVC discards the sum, but detects signed 32-bit inte- ger overflow of the sum, and branches if such overflow is not detected.
BOVC and BNVC are compact branches—they have no branch delay slots, but do have a forbidden slot.
A 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
The special case with rt=0 (for example, GPR[0]) is allowed. On MIPS32, BOVC rs,r0 offset never branches, while BNVC rs,r0 offset always branches.
The special case of rs=0 and rt=0 is allowed. BOVC never branches, while BNVC always branches.
Restrictions:
Control Transfer Instructions (CTIs) should not be placed in branch delay slots or Release 6 forbidden slots. CTIs include all branches and jumps, NAL, ERET, ERETNC, DERET, WAIT, and PAUSE.
If a control transfer instruction (CTI) is executed in the forbidden slot of a compact branch, Release 6 implementa- tions are required to signal a Reserved Instruction exception, but only when the branch is not taken.
Availability and Compatibility:
These instructions are introduced by and required as of Release 6.
See section A.4 on page 461 in Volume II for a complete overview of Release 6 instruction encodings. Brief notes related to these instructions:
• BOVC uses the primary opcode allocated to MIPS32 pre-Release 6 ADDI. Release 6 reuses the ADDI primary opcode for BOVC and other instructions, distinguished by register numbers.
• BNVC uses the primary opcode allocated to MIPS64 pre-Release 6 DADDI. Release 6 reuses the DADDI pri- mary opcode for BNVC and other instructions, distinguished by register numbers.
Operation:
temp1 GPR[rs] temp2 GPR[rt]
BOVC BNVC IBranch on Overflow, Compact; Branch on No Overflow, Compact tempd temp1 + temp2 // wider than 32-bit precision
sum_overflow (tempd32 tempd31) BOVC: cond sum_overflow
BNVC: cond not( sum_overflow )
if cond then
PC ( PC+4 + sign_extend( offset << 2 ) )
endif
Exceptions:
None
The MIPS32® Instruction Set Manual, Revision 6.06 108
BREAK
Breakpoint
31
26 25 6 5
6 20 6
Format: BREAK Purpose: Breakpoint
To cause a Breakpoint exception
Description:
0
MIPS32
SPECIAL 000000
code
BREAK 001101
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A breakpoint exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
Restrictions:
None
Operation:
SignalException(Breakpoint)
Exceptions:
Breakpoint
C.cond.fmt IFloating Point Compare
31
26 25 21 20 16 15 11 10 8 7 6 5 4 3 0
655531124
COP1 010001
fmt
ft
fs
cc
0
A 0
FC 11
cond
Format:
C.cond.fmt
C.cond.S fs, ft (cc
C.cond.D fs, ft (cc
C.cond.PS fs, ft(cc
C.cond.S cc, fs, ft
C.cond.D cc, fs, ft
C.cond.PS cc, fs, ft
Purpose: Floating Point Compare
To compare FP values and record the Boolean result in a condition code.
= 0 implied)
= 0 implied)
= 0 implied)
MIPS32, removed in Release 6
MIPS32, removed in Release 6 MIPS32 Release 2, removed in Release 6 MIPS32, removed in Release 6 MIPS32, removed in Release 6 MIPS32 Release 2, removed in Release 6
Description: FPConditionCode(cc) FPR[fs] compare_cond FPR[ft]
The value in FPR fs is compared to the value in FPR ft; the values are in format fmt. The comparison is exact and nei-
ther overflows nor underflows.
If the comparison specified by the cond field of the instruction is true for the operand values, the result is true; other-
wise, the result is false. If no exception is taken, the result is written into condition code CC; true is 1 and false is 0.
In the cond field of the instruction: cond2..1 specify the nature of the comparison (equals, less than, and so on). cond0 specifies whether the comparison is ordered or unordered, that is, false or true if any operand is a NaN; cond3 indi- cates whether the instruction should signal an exception on QNaN inputs, or not (see Table 3.2).
C.cond.PS compares the upper and lower halves of FPR fs and FPR ft independently and writes the results into condi- tion codes CC +1 and CC respectively. The CC number must be even. If the number is not even the operation of the instruction is UNPREDICTABLE.
If one of the values is an SNaN, or cond3 is set and at least one of the values is a QNaN, an Invalid Operation condi- tion is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise, the Boolean result is written into condition code CC.
There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0.
The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal, equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Bool- ean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP val- ues in the equation. If the equal relation is true, for example, then all four example predicates above yield a true result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result.
Logical negation of a compare result allows eight distinct comparisons to test for the 16 predicates as shown in Table 3.2. Each mnemonic tests for both a predicate and its logical negation. For each mnemonic, compare tests the truth of the first predicate. When the first predicate is true, the result is true as shown in the “If Predicate Is True” column, and the second predicate must be false, and vice versa. (Note that the False predicate is never true and False/True do not follow the normal pattern.)
The truth of the second predicate is the logical negation of the instruction result. After a compare instruction, test for the truth of the first predicate can be made with the Branch on FP True (BC1T) instruction and the truth of the second
The MIPS32® Instruction Set Manual, Revision 6.06 110
C.cond.fmt Floating Point Compare can be made with Branch on FP False (BC1F).
Table 3.2 shows another set of eight compare operations, distinguished by a cond3 value of 1 and testing the same 16 conditions. For these additional comparisons, if at least one of the operands is a NaN, including Quiet NaN, then an Invalid Operation condition is raised. If the Invalid Operation condition is enabled in the FCSR, an Invalid Operation exception occurs.
Table 3.1 FPU Comparisons Without Special Operand Exceptions
Instruction
Comparison Predicate
Comparison CC Result
Instruction
Cond Mnemonic
Name of Predicate and Logically Negated Predicate (Abbreviation)
Relation Values
If Predicate Is True
Inv Op Excp. if QNaN?
Condition Field
>
<
=
?
3
2..0
F
False [this predicate is always False]
F
F
F
F
F
No
0
0
True (T)
T
T
T
T
UN
Unordered
F
F
F
T
T
1
Ordered (OR)
T
T
T
F
F
EQ
Equal
F
F
T
F
T
2
Not Equal (NEQ)
T
T
F
T
F
UEQ
Unordered or Equal
F
F
T
T
T
3
Ordered or Greater Than or Less Than (OGL)
T
T
F
F
F
OLT
Ordered or Less Than
F
T
F
F
T
4
Unordered or Greater Than or Equal (UGE)
T
F
T
T
F
ULT
Unordered or Less Than
F
T
F
T
T
5
Ordered or Greater Than or Equal (OGE)
T
F
T
F
F
OLE
Ordered or Less Than or Equal
F
T
T
F
T
6
Unordered or Greater Than (UGT)
T
F
F
T
F
ULE
Unordered or Less Than or Equal
F
T
T
T
T
7
Ordered or Greater Than (OGT)
T
F
F
F
F
Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False
111
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C.cond.fmt IFloating Point Compare Table 3.2 FPU Comparisons With Special Operand Exceptions for QNaNs
Instruction
Comparison Predicate
Comparison CC Result
Instruction
Cond Mnemonic
Name of Predicate and Logically Negated Predicate (Abbreviation)
Relation Values
If Predicate Is True
Inv Op Excp If QNaN?
Condition Field
>
<
=
?
3
2..0
SF
Signaling False [this predicate always False]
F
F
F
F
F
Yes
1
0
Signaling True (ST)
T
T
T
T
NGLE
Not Greater Than or Less Than or Equal
F
F
F
T
T
1
Greater Than or Less Than or Equal (GLE)
T
T
T
F
F
SEQ
Signaling Equal
F
F
T
F
T
2
Signaling Not Equal (SNE)
T
T
F
T
F
NGL
Not Greater Than or Less Than
F
F
T
T
T
3
Greater Than or Less Than (GL)
T
T
F
F
F
LT
Less Than
F
T
F
F
T
4
Not Less Than (NLT)
T
F
T
T
F
NGE
Not Greater Than or Equal
F
T
F
T
T
5
Greater Than or Equal (GE)
T
F
T
F
F
LE
Less Than or Equal
F
T
T
F
T
6
Not Less Than or Equal (NLE)
T
F
F
T
F
NGT
Not Greater Than
F
T
T
T
T
7
Greater Than (GT)
T
F
F
F
F
Key: ? = unordered, > = greater than, < = less than, = is equal, T = True, F = False
Restrictions:
The fields fs and ft must specify FPRs valid for operands of type fmt. If the fields are not valid, the result is UNPRE-
DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the
operand FPRs becomes UNPREDICTABLE.
The result of C.cond.PS is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model;
it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU,. The result of C.cond.PS is UNPREDICTABLE if the condition code number is odd.
Availability and Compatibility:
This instruction has been removed in Release 6 and has been replaced by the ‘CMP.cond fmt’ instruction. Refer to the CMP.cond fmt instruction in this manual for more information. Release 6 does not support Paired Single (PS).
Operation:
if SNaN(ValueFPR(fs, fmt)) or SNaN(ValueFPR(ft, fmt)) or QNaN(ValueFPR(fs, fmt)) or QNaN(ValueFPR(ft, fmt)) then less false
equal false
unordered true
if (SNaN(ValueFPR(fs,fmt)) or SNaN(ValueFPR(ft,fmt))) or
(cond3 and (QNaN(ValueFPR(fs,fmt)) or QNaN(ValueFPR(ft,fmt)))) then
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C.cond.fmt
Floating Point Compare
SignalException(InvalidOperation)
endif
else
less ValueFPR(fs, fmt)