Pipelined CPU
During a particular clock cycle, assume that s1=16, s2=8 and that the following five instructions were in the pipeline (the first column is the instruction’s address in decimal):
100 lw t1, 4(s1)
Copyright By PowCoder代写 加微信 powcoder
104 addi t2, s2, -4
108 sw
112 ori
116 sub
t5, s1, s2
During the cycle in question, sub was in the instruction fetch stage and lw was in the write-back stage.
For each of the busses denoted on the previous slide, describe what the bus holds (e.g. the immediate of the lw instruction) and compute its decimal value
Not suitable for online tests so adjustments will be made. e.g. numerical and short answer entries without textual explanations.
Describe the content and compute the value of the A bus.
This is the address of the instruction in the IF stage (the 5th instruction) 116 sub t5, s1, s2
Describe the content and compute the value of the B bus.
This is the ??? ???
Describe the content and compute the value of the C bus.
1 (lw writes to a register)
This is the RegWrite of the instruction in the WB stage (the 1st instruction) 100 lw t1, 4(s1)
Describe the content and compute the value of the D bus.
This is the ??? ???
Describe the content and compute the value of the E bus.
This is the ??? ???
Describe the content and compute the value of the F bus.
This is the data from the source register 1 in the instruction in the EX stage (the 3rd instruction)
108 sw t3, 4(s2)
Describe the content and compute the value of the G bus.
This is the ??? ???
Describe the content and compute the value of the H bus.
4 (imm[4:0] )
These are the imm[4:0] bits of the instruction in the EX stage (the 3rd instruction)
108 sw s1, 4(s2)
Describe the content and compute the value of the I bus.
0 (not a branch instruction)
This is 1 only if a branch is taken but the instruction in the MEM stage (the 2nd instruction) is not a branch instruction
104 addi t2, s2, -4
Describe the content and compute the value of the J bus.
This is the ??? ???
Describe the content and compute the value of the K bus.
0 (addi does not write to RAM)
This is 1 only if the instruction in the MEM stage (the 2nd instruction) writes to RAM
104 addi t2, s2, -4
Describe the content and compute the value of the L bus.
This is the ??? ???
Describe the content and compute the value of the M bus.
1 (reads from RAM)
This is 1 only the instruction in the WB stage (the 1st instruction) reads from
100 lw t1, 4(s1)
Describe the content and compute the value of the N bus.
This is the ??? ???
Describe the content and compute the value of the O bus.
This is the ??? ???
Given a 128KBytes direct-mapped data cache that uses a 32-bit address and 16 bytes per block answer the following questions:
(a) How many bits are used for the byte offset?
4 bits (16 bytes per block)
(b) How many bits are used for the index field?
13 bits (8K blocks)
(c) How many bits are used for the tag?
15 bits (remaining bits = 32 – 17)
The calculations for the above answers are as follows:
128K=128*1024=27*210=217, 16=24, and 217/24=213
We, therefore, have 8K blocks with 16 bytes of data in each block.
For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache:
Tag[31-10] Index[9-4] Offset[3-0]
(a) What is the cache entry size in bytes? Write the value in the space below and explain how you obtained it.
(Offset[3-0]= 4 bits= 24 bytes= ??? bytes)
(b) How many entries does the cache have? Write the value in the space below and explain how you obtained it.
??? entries
(Index[9-4]= 6 bits= 26 entries= ??? entries)
Not suitable for online tests so adjustments will be made. e.g. numerical and short answer entries without textual explanations.
(c) How many bits per entry are required for such a cache implementation? Write the value in the space below and explain how you obtained it.?
Each cache entry contains:
A valid bit= 1 bit;
Tag bits [31-10]= 22 bits
Data bits= 128 bits= 8 bits x 16 bytes
1 Valid bit+ 22 Tag bits+ 128 Data bits = 151 bits
程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com