ICS 51: Introduction to Computer Organization Sample problems #10 on Spring 2020
1. [Arithmetic Logic Unit Design] You may use any logic gates or data path components.
a. Given two 4-bit two’s complement binary numbers A and B, build a circuit that outputs 1 when A=B, otherwise 0.
1-bit Full Adder
XOR
AND
OR
NOT
2. [Register File Design] Build a 4×8-bit register file with one read and one write address, using 8- bit registers, decoders, and or any logic gate. (Ignore the routing for clk)
8-bit register
Tri-state buffer (optional)
3. [MIPS Processor Design/Datapath] Given the datapath/lookup tables in the following for instruction opcodes and ALU controller
Intr. opcode
ALUOp
Instruction operation
Funct field
Desired ALU action
LW
00
load word
XXXXXX
add
SW
00
store word
XXXXXX
add
addi
00
add immediate
XXXXXX
add
BEQ/BNEQ
01
branch equal/not equal
XXXXXX
subtract
R-type
10
add
100000
add
R-type
10
subtract
100010
subtract
R-type
10
AND
100100
AND
R-type
10
OR
100101
OR
J
X
jump
XXXXXX
X
ALUControl
Function
–
ALUControl
Function
0000
AND
–
0010
add
0001
OR
–
0110
subtract
a. According to the given MIPS design, fill in the table below for the following instructions: i. lw $7, offset($8) (i.e. R7 = Mem[R8+offset], assume offset is 32)
Line
Value
Line
Value
Instruction bits[31:26]
RegDst
Instruction bits[25:21]
MemRead
Instruction bits[20:16]
MemWrite
Instruction bits[15:0]
MemtoReg
ALUOp
ALUSrc
ALUControl
RegWrite
ii. addi $3, $4, imm (i.e. $3 = $4 + imm, assume imm is 16)
Line
Value
Line
Value
Instruction bits[31:26]
RegDst
Instruction bits[25:21]
MemRead
Instruction bits[20:16]
MemWrite
Instruction bits[15:0]
MemtoReg
ALUOp
ALUSrc
ALUControl
RegWrite
b. In order to support the bneq instruction (branch not equal), accomplish the missing component in the following MIPS processor. (Note: you may need one output of Control unit, which is not named/connected yet.)
c. [BONUS] In order to support the blez instruction (Branch on less than or equal to zero), accomplish the missing component in the following. (Assume ALUResult is N-bit and you may need it routing to the solution.) (Note: you may need one output of Control unit, not named/connected yet.)
d. i.
ii.
From the above instruction formats, fill in the assembled machine code according to each following assembly code.
sub $11, $13, $15
beq $14, $16, addr_x (assume addr_x is 4)
opcode
rs
rt
rd
shamt
funct
00000
opcode
rs
rt
address
iii. j addr_y (assume addr_y is 64)
opcode
address
4. [Decoder/Multiplexer]
a. Accomplish the truth table of a 2to4 decoder
s
y3
y2
y1
y0
00
01
10
11
b. Implement the function using a 4:1 multiplexer
S1
S0
Y
0
0
1
0
1
0
1
0
0
1
1
1
5. [Register Design] Build a 4x 4-bit register file with the input D[3:0], S[1:0] and the output Q[3:0], using four 4-bit registers below. (Note: when EN is 1, the register updates the value. When EN is 0, the register holds the value.)
6. Suppose the MIPS processor has the following maximum delays for each of the functional units:
Memory unit: 200ps (for one read or one write)
ALUs or Adders: 180ps
Register File: 50ps (for two reads or one write).
Assume all other circuitry (except registers) – i.e. mux’s, wires, etc – has negligible delay.
a) What is the latency of lw instruction?
b) What is the latency of R-type instruction?
c) What is clock period?