PAPER CODE NO.
ELEC 470
EXAMINER: Dr S Khursheed DEPARTMENT: EE&E
Email: S.Khursheed@Liverpool.ac.uk
SEMESTER TWO EXAMINATION REPLACEMENTS 2019/20
ADVANCED EMBEDDED SYSTEMS
INSTRUCTIONS TO CANDIDATES
The numbers in the right hand margin represent an approximate guide to the marks available for that question (or part of a question). Total marks available are 100.
Copying any material from another source, or colluding with any other person in the preparation and production of this work will be considered suspected academic misconduct and will be dealt with according to the University¡¯s Academic Integrity Policy.
This is an open-book test. Answer ALL Questions.
The use of a calculator IS allowed.
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1. a)
An instruction pipeline is an important element in the RISC (reduced 8 instruction set computer) architecture. Briefly describe how an instruction pipeline works and explain why a pipeline with more stages can give an
improved performance.
b) The ARM9 microprocessor has a 5 stage pipeline and reads registers at the 6 end of stage 2 (decode) but writes values to registers in stage 5 (write-back).
i. How does this lead to a ¡®read-after-write¡¯ hazard?
ii. How is this problem eliminated using ¡®data forwarding¡¯?
iii. If the problem cannot be eliminated then an ¡®interlock¡¯ results; what is an ¡®interlock¡¯?
c) In the following ARM9 program, there are two examples of ¡®data 6 forwarding¡¯ and one further example of a ¡®read-after-write¡¯ hazard that
results in an interlock. Identify all three.
Mnemonic
MOV r1, #0x0004A000
MOV r2, #0x00003BC0
MOV r0, r1, LSL #8
SUB r3, r2, r1
ADD r4, r1, r2
RSB r5, r4, r0
MOV r6, #0x000002E4
MOV r7, #0x0002E400
ADD r2, r1, r0
Question continues overleaf.
Comment
;move 0x0004A000 into r1
;move 0x00003BC0 into r2
;left shift r1 by 8 bits
;subtract r1 from r2
;add r1 and r2, sum in r4
;subtract r4 from r0
;move 0x000002E4 into r6
;move 0x0002E400 into r7
;add r1 and r2, sum in r2
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Question continued.
d) Draw a pipeline diagram for the program given above in part c), assuming 10 that it is executed using the ARM9 microprocessor.
What is the performance, as measured in ¡®clocks per instruction¡¯ (CPI)?
(counting clock cycles from the execute stage of the first instruction to the
execute stage of the last instruction)
How can the instructions be reordered so that ¡®read-after-write¡¯ hazards do not occur without changing the function of the programme?
e) What values are held in registers R3, R4, and R5 after the execution of the 3 following instructions, assuming that the value in register R0 is
0x80C6B75F?
i) MOV R3, R0, ROR #12
ii) MOV R4, R0, ASR #16
iii) MOV R5, R0, LSR # 4
Total 33
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2. a)
Define the term dynamic power dissipation. Write down a mathematical 2 relationship for dynamic power dissipation in terms of operating
frequency, switching capacitance and supply voltage.
b) With reference to the equation you gave for part (a) above, describe 5 using appropriate examples, how good circuit design and good software
design can lead to a reduction in dynamic power dissipation.
c) Figure Q2 shows a circuit diagram of a NAND gate which uses 8 multithreshold CMOS technology (MTCMOS) to implement power gating. With reference to the figure, describe its working principle, and explain how power gating leads to a reduction in leakage power dissipation.
Figure Q2
Total 15
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3. a)
b)
In the context of data path synthesis of a digital system, briefly describe 4 the principles of allocation and binding.
Figure Q3 shows a scheduled data flow graph with inputs {a, b, c, d, e, f} and output {y} (see overleaf). Assume that the delay of the adder and the multiplier fits within one clock cycle.
i) Using a figure, show the life-time analysis of all variables, including 5 inputs, outputs and intermediate variables.
ii) Using the Left Edge Algorithm, determine the minimum number of registers required to store all variables. Show the variable to register mapping to minimize the number of registers.
iii) Draw the data-path implementing the scheduled data flow graph with two adders and two multipliers as shown in Figure Q3 and using the variable to register mapping obtained in part ii).
Question continues overleaf.
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6
12
Total 27
Question continued.
Figure Q3: The scheduled sequence graph mentioned in Q3 (part b)
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4. a) Using appropriate examples, describe the main differences between the 4 SystemC modelling processes: SC_METHOD and SC_THREAD.
b) Develop a SystemC model to compute the following logic expression: 6 Y = (A and B) or (C and D),
where the inputs and the output of the basic module should be SC_Logic type. The state of the output variable ¡®Y¡¯ should change whenever any of the input variables (A, B, C, D) change their state.
The model should include the basic module description.
c) i)
Develop a SystemC behavioural model (basic module only) of a 4-bit 6 synchronous counter with enable and reset inputs. The counter counts up when input c=1 and counts down when c=0, where c is the control input.
ii) For the model developed in part (i) above, design a test bench with the 4 following sequence:
set enable = 0 wait for 50ns set enable = 1 wait for 50ns set reset = 1 wait for 50ns set c = 1
wait for 200ns set enable = 0 wait for 30ns
iii) Develop the top-level module of the counter using the results of parts (i) and (ii) above, showing the necessary signal interconnections. Assume the clock period to be 10 nanoseconds.
Total 25
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