The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2
Editors: 1, ́c1,2
1SiFive Inc.,
2CS Division, EECS Department, University of California, Berkeley
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May 7, 2017
Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): ́c, ˇzienis, , . Batten, . Baum, , , , , , , Palmer Dabbelt, , , , , , , , Yunsup Lee, , , ’Rear, , , , , , , , , DeWalker, , , – son, and .
This document is released under a Creative Commons Attribution 4.0 International License.
This document is a derivative of “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1” released under the following license: ⃝c 2010–2017 , Yunsup Lee, , ́c. Creative Commons Attribution 4.0 International License.
Please cite as: “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2”, Editors and ́c, RISC-V Foundation, May 2017.
This is version 2.2 of the document describing the RISC-V user-level architecture. The document contains the following versions of the RISC-V ISA modules:
Base Version
RV32I 2.0 Y
RV32E 1.9 N RV64I 2.0 Y RV128I 1.7 N
Extension Version Frozen? M 2.0 Y
F 2.0 Y D 2.0 Y Q 2.0 Y L 0.0 N C 2.0 Y B 0.0 N J 0.0 N T 0.0 N P 0.1 N V 0.2 N N 1.1 N
To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled “frozen” above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.
The major changes in this version of the document include:
• The previous version of this document was released under a Creative Commons Attribution 4.0 International Licence by the original authors, and this and future versions of this document will be released under the same licence.
• Rearranged chapters to put all extensions first in canonical order.
• Improvements to the description and commentary.
• Modified implicit hinting suggestion on JALR to support more efficient macro-op fusion of
LUI/JALR and AUIPC/JALR pairs.
Volume I: RISC-V User-Level ISA V2.2
Clarification of constraints on load-reserved/store-conditional sequences.
A new table of control and status register (CSR) mappings.
Clarified purpose and behavior of high-order bits of fcsr.
Corrected the description of the FNMADD.fmt and FNMSUB.fmt instructions, which had suggested the incorrect sign of a zero result.
Instructions FMV.S.X and FMV.X.S were renamed to FMV.W.X and FMV.X.W respectively to be more consistent with their semantics, which did not change. The old names will continue to be supported in the tools.
Specified behavior of narrower (
long instruction formats.
• CSR instructions are now described in the base integer format where the counter registers
are introduced, as opposed to only being introduced later in the floating-point section (and
the companion privileged architecture manual).
• The SCALL and SBREAK instructions have been renamed to ECALL and EBREAK, re-
spectively. Their encoding and functionality are unchanged.
• Clarification of floating-point NaN handling, and a new canonical NaN value.
• Clarification of values returned by floating-point to integer conversions that overflow.
• Clarification of LR/SC allowed successes and required failures, including use of compressed
instructions in the sequence.
• A new RV32E base ISA proposal for reduced integer register counts, supports MAC exten-
• A revised calling convention.
• Relaxed stack alignment for soft-float calling convention, and description of the RV32E calling
Volume I: RISC-V User-Level ISA V2.2 iii convention.
• A revised proposal for the C compressed extension, version 1.9.
Preface to Version 2.0
This is the second release of the user ISA specification, and we intend the specification of the base user ISA plus general extensions (i.e., IMAFD) to remain fixed for future development. The following changes have been made since Version 1.0 [35] of this ISA specification.
• The ISA has been divided into an integer base with several standard extensions.
• The instruction formats have been rearranged to make immediate encoding more efficient.
• The base ISA has been defined to have a little-endian memory system, with big-endian or
bi-endian as non-standard variants.
• Load-Reserved/Store-Conditional (LR/SC) instructions have been added in the atomic in-
struction extension.
• AMOs and LR/SC can support the release consistency model.
• The FENCE instruction provides finer-grain memory and I/O orderings.
• An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP
has been changed to make room.
• The AUIPC instruction, which adds a 20-bit upper immediate to the PC, replaces the RDNPC
instruction, which only read the current PC value. This results in significant savings for
position-independent code.
• The JAL instruction has now moved to the U-Type format with an explicit destination
register, and the J instruction has been dropped being replaced by JAL with rd=x0. This removes the only instruction with an implicit destination register and removes the J-Type instruction format from the base ISA. There is an accompanying reduction in JAL reach, but a significant reduction in base ISA complexity.
• The static hints on the JALR instruction have been dropped. The hints are redundant with the rd and rs1 register specifiers for code compliant with the standard calling convention.
• The JALR instruction now clears the lowest bit of the calculated target address, to simplify
hardware and to allow auxiliary information to be stored in function pointers.
• The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and FMV.X.D, respectively. Similarly, MXTF.S and MXTF.D instructions have been renamed to FMV.S.X
and FMV.D.X, respectively.
• The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR, respec-
tively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added to individu-
ally access the rounding mode and exception flags subfields of the fcsr.
• The FMV.X.S and FMV.X.D instructions now source their operands from rs1, instead of rs2.
This change simplifies datapath design.
• FCLASS.S and FCLASS.D floating-point classify instructions have been added.
• A simpler NaN generation and propagation scheme has been adopted.
• ForRV32I,thesystemperformancecountershavebeenextendedto64-bitswide,withseparate
read access to the upper and lower 32 bits.
• Canonical NOP and MV encodings have been defined.
Volume I: RISC-V User-Level ISA V2.2
Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit in- structions.
Description of a 128-bit address space variant, RV128, has been added.
Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions.
A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.
1 Introduction 1
1.1 RISC-VISAOverview…………………………….. 3 1.2 InstructionLengthEncoding …………………………. 5 1.3 Exceptions,Traps,andInterrupts……………………….. 7
2 RV32I Base Integer Instruction Set, Version 2.0 9
2.1 Programmers’ModelforBaseIntegerSubset …………………. 9 2.2 BaseInstructionFormats …………………………… 11 2.3 ImmediateEncodingVariants…………………………. 11 2.4 IntegerComputationalInstructions………………………. 13 2.5 ControlTransferInstructions …………………………. 15 2.6 LoadandStoreInstructions………………………….. 18 2.7 MemoryModel………………………………… 20 2.8 ControlandStatusRegisterInstructions……………………. 21 2.9 EnvironmentCallandBreakpoints ………………………. 24
3 RV32E Base Integer Instruction Set, Version 1.9 27
3.1 RV32EProgrammers’Model …………………………. 27 3.2 RV32EInstructionSet…………………………….. 27 3.3 RV32EExtensions ………………………………. 28
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4 RV64I Base Integer Instruction Set, Version 2.0 29
4.1 RegisterState…………………………………. 29 4.2 IntegerComputationalInstructions………………………. 29 4.3 LoadandStoreInstructions………………………….. 31 4.4 SystemInstructions ……………………………… 32
5 RV128I Base Integer Instruction Set, Version 1.7 33
6 “M” Standard Extension for Integer Multiplication and Division, Version 2.0 35
6.1 MultiplicationOperations …………………………… 35 6.2 DivisionOperations ……………………………… 36
7 “A” Standard Extension for Atomic Instructions, Version 2.0 39
7.1 SpecifyingOrderingofAtomicInstructions ………………….. 39 7.2 Load-Reserved/Store-ConditionalInstructions…………………. 40 7.3 AtomicMemoryOperations………………………….. 43
8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0 45
8.1 FRegisterState ……………………………….. 45 8.2 Floating-PointControlandStatusRegister ………………….. 47 8.3 NaNGenerationandPropagation……………………….. 48 8.4 SubnormalArithmetic …………………………….. 49 8.5 Single-PrecisionLoadandStoreInstructions………………….. 49 8.6 Single-Precision Floating-Point Computational Instructions . . . . . . . . . . . . . . 49 8.7 Single-Precision Floating-Point Conversion and Move Instructions . . . . . . . . . . 51 8.8 Single-Precision Floating-Point Compare Instructions . . . . . . . . . . . . . . . . . . 52 8.9 Single-PrecisionFloating-PointClassifyInstruction . . . . . . . . . . . . . . . . . . . 53
9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0 55
9.1 DRegisterState ……………………………….. 55
Volume I: RISC-V User-Level ISA V2.2 vii
9.2 NaNBoxingofNarrowerValues………………………… 55 9.3 Double-PrecisionLoadandStoreInstructions…………………. 56
9.4 Double-Precision Floating-Point Computational Instructions . . . . . . . . . . 9.5 Double-Precision Floating-Point Conversion and Move Instructions . . . . . . 9.6 Double-Precision Floating-Point Compare Instructions . . . . . . . . . . . . . 9.7 Double-Precision Floating-Point Classify Instruction . . . . . . . . . . . . . .
10 “Q” Standard Extension for Quad-Precision Floating-Point, Version 2.0
. . . . 57 . . . . 57 . . . . 59 . . . . 59
10.1Quad-PrecisionLoadandStoreInstructions………………….. 61 10.2Quad-PrecisionComputationalInstructions ………………….. 62 10.3Quad-PrecisionConvertandMoveInstructions ………………… 62
10.4 Quad-Precision Floating-Point Compare Instructions . . . . . . . . . 10.5 Quad-PrecisionFloating-PointClassifyInstruction . . . . . . . . . .
11 “L” Standard Extension for Decimal Floating-Point, Version 0.0
. . . . . . . . . 63 . . . . . . . . . 63
11.1DecimalFloating-PointRegisters……………………….. 65
12 “C” Standard Extension for Compressed Instructions, Version 2.0 67
12.1Overview …………………………………… 67 12.2CompressedInstructionFormats ……………………….. 69 12.3LoadandStoreInstructions………………………….. 71 12.4ControlTransferInstructions …………………………. 74 12.5IntegerComputationalInstructions………………………. 76 12.6UsageofCInstructionsinLR/SCSequences …………………. 80 12.7RVCInstructionSetListings …………………………. 81
13 “B” Standard Extension for Bit Manipulation, Version 0.0 85
14 “J” Standard Extension for Dynamically Translated Languages, Version 0.0 87
15 “T” Standard Extension for Transactional Memory, Version 0.0 89
viii Volume I: RISC-V User-Level ISA V2.2
16 “P” Standard Extension for Packed-SIMD Instructions, Version 0.1 91
17 “V” Standard Extension for Vector Operations, Version 0.2 93
17.1VectorUnitState……………………………….. 93 17.2ElementDatatypesandWidth ………………………… 93 17.3 VectorConfigurationRegisters(vcmaxw,vctype,vcp) . . . . . . . . . . . . . . . . . 95 17.4VectorLength…………………………………. 97 17.5RapidConfigurationInstructions……………………….. 97
18 “N” Standard Extension for User-Level Interrupts, Version 1.1 101
18.1AdditionalCSRs ………………………………..101
18.2 User Status Register (ustatus) . . 18.3 Other CSRs . . . . . . . . . . . . . 18.4 N Extension Instructions . . . . . . 18.5ReducingContext-SwapOverhead
19 RV32/64G Instruction Set Listings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ……………………….102
20 RISC-V Assembly Programmer’s Handbook 109
21 Extending RISC-V 113
21.1 Extension Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 21.2RISC-VExtensionDesignPhilosophy ……………………..116 21.3 Extensions within fixed-width 32-bit instruction format . . . . . . . . . . . . . . . . 116 21.4 Adding aligned 64-bit instruction extensions . . . . . . . . . . . . . . . . . . . . . . . 118 21.5SupportingVLIWencodings ………………………….118
22 ISA Subset Naming Conventions 121
22.1 Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.2BaseIntegerISA ………………………………..121 22.3 Instruction Extensions Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Volume I: RISC-V User-Level ISA V2.2 ix
22.4VersionNumbers ………………………………..122 22.5 Non-Standard Extension Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 22.6Supervisor-levelInstructionSubsets ………………………122 22.7Supervisor-levelExtensions …………………………..122 22.8SubsetNamingConvention …………………………..123
23 History and Acknowledgments 125
23.1 History from Revision 1.0 of ISA manual . . . . . . . . . . . . . . . . . . . . . . . . . 125 23.2 History from Revision 2.0 of ISA manual . . . . . . . . . . . . . . . . . . . . . . . . . 126 23.3HistoryforRevision2.1 …………………………….128 23.4HistoryforRevision2.2 …………………………….128 23.5 Funding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
x Volume I: RISC-V User-Level ISA V2.2
Chapter 1 Introduction
RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry implementations. Our goals in defining RISC-V include:
• A completely open ISA that is freely available to academia and industry.
• A real ISA suitable for direct native hardware implementation, not just simulation or binary
translation.
• An ISA that avoids “over-architecting” for a particular microarchitecture style (e.g., mi-
crocoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom,
ASIC, FPGA), but which allows efficient implementation in any of these.
• An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-
purpose software development.
• Support for the revised 2008 IEEE-754 floating-point standard [14].
• An ISA supporting extensive user-level ISA extensions and specialized variants.
• Both 32-bit and 64-bit address space variants for applications, operating system kernels, and
hardware implementations.
• An ISA with support for highly-parallel multicore or manycore implementations, including
heterogeneous multiprocessors.
• Optional variable-length instructions to both expand available instruction encoding space and
to support an optional dense instruction encoding for improved performance, static code size,
and energy efficiency.
• A fully virtualizable ISA to ease hypervisor development.
• An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA de-
Commentary on our design decisions is formatted as in this paragraph, and can be skipped if the reader is only interested in the specification itself.
The name RISC-V was chosen to represent the fifth major RISC ISA design from UC Berkeley (RISC-I [23], RISC-II [15], SOAR [32], and SPUR [18] were the first four). We also pun on the
Volume I: RISC-V User-Level ISA V2.2
use of the Roman numeral “V” to signify “variations” and “vectors”, as support for a range of architecture research, including various data-parallel accelerators, is an explicit goal of the ISA design.
We developed RISC-V to support our own needs in research and education, where our group is particularly interested in actual hardware implementations of research ideas (we have completed eleven different silicon fabrications of RISC-V since the first edition of this specification), and in providing real implementations for students to explore in classes (RISC-V processor RTL de- signs have been used in multiple undergraduate and graduate classes at Berkeley). In our current research, we are especially interested in the move towards specialized and heterogeneous accel- erators, driven by the power constraints imposed by the end of conventional transistor scaling. We wanted a highly flexible and extensible base ISA around which to build our research effort.
A question we have been repeatedly asked is “Why develop a new ISA?” The biggest obvious benefit of using an existing commercial ISA is the large and widely supported software ecosystem, both development tools and ported applications, which can be leveraged in research and teaching. Other benefits include the existence of large amounts of documentation and tutorial examples. However, our experience of using commercial instruction sets for research and teaching is that these benefits are smaller in practice, and do not outweigh the disadvantages:
• Commercial IS
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