程序代写代做代考 assembler graph C cache x86 assembly go compiler clock Carnegie Mellon

程序代写 CS代考 / compiler, C语言代写, x86汇编代写代考

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Machine-Level Programming I: Basics
15-213/18-213/15-513: Introduction to Computer Systems 5th Lecture, May 27, 2020
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Logistics
 Course ombudsmen
▪ Ishita Sinha
▪ If you’re having any issues with a TA, and are uncomfortable discussing this with the instructor, go to her
 TA office hours on course website
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Today: Machine Programming I: Basics
 History of Intel processors and architectures  Assembly Basics: Registers, operands, move  Arithmetic & logical operations
 C, assembly, machine code
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Intel x86 Processors
 Dominate laptop/desktop/server market
 Evolutionary design
▪ Backwards compatible up until 8086, introduced in 1978 ▪ Added more features as time goes on
 x86 is a Complex Instruction Set Computer (CISC) ▪ Many different instructions with many different formats
▪ But, only small subset encountered with Linux programs
 Compare: Reduced Instruction Set Computer (RISC)
▪ RISC: *very few* instructions, with *very few* modes for each
▪ RISC can be quite fast (but Intel still wins on speed!)
▪ Current RISC renaissance (e.g., ARM, RISC V), especially for low-power
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Intel x86 Evolution: Milestones
Name Date Transistors MHz
 8086 1978 29K 5-10 ▪ First 16-bit Intel processor. Basis for IBM PC & DOS
▪ 1MB address space
 386 1985 275K 16-33 ▪ First 32 bit Intel processor , referred to as IA32
▪ Added “flat addressing”, capable of running Unix
 Pentium 4E 2004 125M 2800-3800 ▪ First 64-bit Intel x86 processor, referred to as x86-64
 Core 2 2006 291M ▪ First multi-core Intel processor
 Core i7 2008 731M
▪ Four cores (our shark machines) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Intel x86 Processors, cont.
 Machine Evolution
▪ 386 1985 0.3M ▪ Pentium 1993 3.1M ▪ Pentium/MMX 1997 4.5M ▪ PentiumPro 1995 6.5M ▪ Pentium III 1999 8.2M ▪ Pentium 4 2000 42M ▪ Core 2 Duo 2006 291M ▪ Core i7 2008 731M ▪ Core i7 Skylake 2015 1.9B
 Added Features
▪ Instructions to support multimedia operations
▪ Instructions to enable more efficient conditional operations
▪ Transition from 32 bits to 64 bits
▪ More cores
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Intel x86 Processors, cont.
 Past Generations ▪1stPentiumPro 1995 ▪ 1st Pentium III 1999 ▪ 1st Pentium 4 2000 ▪ 1st Core 2 Duo 2006
Process technology
600nm 250 nm 180 nm
65 nm
Process technology dimension = width of narrowest wires (10 nm ≈ 100 atoms wide)
 Recent & Upcoming Generations
1. Nehalem 2008
2. Sandy Bridge 2011
3. Ivy Bridge 2012
4. Haswell 2013
5. Broadwell 2014
6. Skylake 2015
7. Kaby Lake 2016
8. Coffee Lake 2017
9. Cannon Lake 2018
10. Ice Lake 2019
11. Tiger Lake 2020?
45 nm 32 nm 22 nm 22 nm 14 nm 14 nm 14 nm 14 nm 10 nm 10 nm 10 nm
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2018 State of the Art: Coffee Lake
 Mobile Model: Core i7 ▪ 2.2-3.2 GHz
 Server Model: Xeon E ▪ Integrated graphics
▪ 45 W
 Desktop Model: Core i7 ▪ Integrated graphics
▪ 2.4-4.0 GHz
▪ Multi-socket enabled ▪ 3.3-3.8 GHz
▪ 80-95 W
▪ 35-95 W Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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x86 Clones: Advanced Micro Devices (AMD)
 Historically
▪AMD has followed just behind Intel ▪A little bit slower, a lot cheaper
 Then
▪Recruited top circuit designers from Digital Equipment Corp. and
other downward trending companies
▪Built Opteron: tough competitor to Pentium 4 ▪Developed x86-64, their own extension to 64 bits
 Recent Years
▪Intel got its act together
▪ 1995-2011: Lead semiconductor “fab” in world ▪ 2018: #2 largest by $$ (#1 is Samsung)
▪ 2019: reclaimed #1
▪AMD fell behind
▪ Relies on external semiconductor manufacturer GlobalFoundaries ▪ ca. 2019 CPUs (e.g., Ryzen) are competitive again
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Intel’s 64-Bit History
 2001: Intel Attempts Radical Shift from IA32 to IA64 ▪ Totally different architecture (Itanium, AKA “Itanic”)
▪ Executes IA32 code only as legacy ▪ Performance disappointing
 2003: AMD Steps in with Evolutionary Solution ▪ x86-64 (now called “AMD64”)
 Intel Felt Obligated to Focus on IA64
▪ Hard to admit mistake or that AMD is better
 2004: Intel Announces EM64T extension to IA32 ▪ Extended Memory 64-bit Technology
▪ Almost identical to x86-64!
 Virtually all modern x86 processors support x86-64 ▪ But, lots of code still runs in 32-bit mode
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Our Coverage
 IA32
▪ The traditional x86
▪ For 15/18-213: RIP, Summer 2015
 x86-64
▪ The standard
▪ shark> gcc hello.c
▪ shark> gcc –m64 hello.c
 Presentation
▪ Book covers x86-64
▪ Web aside on IA32
▪ We will only cover x86-64
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Today: Machine Programming I: Basics
 History of Intel processors and architectures  Assembly Basics: Registers, operands, move  Arithmetic & logical operations
 C, assembly, machine code
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Levels of Abstraction
C programmer
#include
int main(){
int i, n = 10, t1 = 0, t2 = 1, nxt; for (i = 1; i <= n; ++i){ printf("%d, ", t1); nxt = t1 + t2; t1 = t2; t2 = nxt; } return 0; } Assembly programmer Nice clean layers, but beware... Computer designer Gates, clocks, circuit layout, ... Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 13 Carnegie Mellon Definitions  Architecture: (also ISA: instruction set architecture) The parts of a processor design that one needs to understand for writing correct machine/assembly code ▪ Examples: instruction set specification, registers ▪ Machine Code: The byte-level programs that a processor executes ▪ Assembly Code: A text representation of machine code  Microarchitecture: Implementation of the architecture ▪ Examples: cache sizes and core frequency  Example ISAs: ▪ Intel: x86, IA32, Itanium, x86-64 ▪ ARM: Used in almost all mobile phones ▪ RISC V: New open-source ISA Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 14 Carnegie Mellon Assembly/Machine Code View CPU PC Registers Addresses Data Instructions Memory Code Data Stack Condition Codes Programmer-Visible State ▪ PC: Program counter ▪ Address of next instruction ▪ Called “RIP” (x86-64) ▪ Register file ▪ Heavily used program data ▪ Condition codes ▪ Store status information about most recent arithmetic or logical operation ▪ Used for conditional branching Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition ▪ Memory ▪ Byte addressable array ▪ Code and user data ▪ Stack to support procedures 15 Carnegie Mellon Assembly Characteristics: Data Types  “Integer” data of 1, 2, 4, or 8 bytes ▪ Data values ▪ Addresses (untyped pointers)  Floating point data of 4, 8, or 10 bytes  (SIMD vector data types of 8, 16, 32 or 64 bytes)  Code: Byte sequences encoding series of instructions  No aggregate types such as arrays or structures ▪ Just contiguously allocated bytes in memory Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 16 Carnegie Mellon x86-64 Integer Registers %rax %eax %rbx %ebx %rcx %ecx %rdx %edx %rsi %esi %rdi %edi %rsp %esp %rbp %ebp %r8 %r8d %r9 %r9d %r10 %r10d %r11 %r11d %r12 %r12d %r13 %r13d %r14 %r14d %r15 %r15d ▪ Can reference low-order 4 bytes (also low-order 1 & 2 bytes) ▪ Not part of memory (or cache) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 17 Carnegie Mellon Some History: IA32 Registers Origin (mostly obsolete) accumulate counter data base source index destination index stack pointer base pointer %eax %ax %ah %al %ecx %cx %ch %cl %edx %dx %dh %dl %ebx %bx %bh %bl %esi %si %edi %di %esp %sp %ebp %bp Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 16-bit virtual registers (backwards compatibility) 18 general purpose Carnegie Mellon Assembly Characteristics: Operations  Transfer data between memory and register ▪ Load data from memory into register ▪ Store register data into memory  Perform arithmetic function on register or memory data  Transfer control ▪ Unconditional jumps to/from procedures ▪ Conditional branches ▪ Indirect branches Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 19 Carnegie Mellon Moving Data  Moving Data movq Source, Dest  Operand Types ▪ Immediate: Constant integer data ▪ Example: $0x400, $-533 ▪ Like C constant, but prefixed with ‘$’ ▪ Encoded with 1, 2, or 4 bytes ▪ Register: One of 16 integer registers ▪ Example: %rax, %r13 ▪ But %rsp reserved for special use ▪ Others have special uses for particular instructions ▪ Memory: 8 consecutive bytes of memory at address given by register ▪ Simplest example: (%rax) ▪ Various other “addressing modes” %rax %rcx %rdx %rbx %rsi %rdi %rsp %rbp %rN Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 20 Warning: Intel docs use mov Dest, Source Carnegie Mellon movq Operand Combinations Source Dest Src,Dest movq $0x4,%rax movq$-147,(%rax) movq %rax,%rdx movq %rax,(%rdx) movq (%rax),%rdx C Analog temp = 0x4; *p=-147; temp2 = temp1; *p = temp; temp = *p; Imm Reg Mem movq Reg Mem Reg Mem Reg Cannot do memory-memory transfer with a single instruction Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 21 Carnegie Mellon Simple Memory Addressing Modes  Normal (R) Mem[Reg[R]] ▪Register R specifies memory address ▪Aha! Pointer dereferencing in C movq (%rcx),%rax  Displacement D(R) Mem[Reg[R]+D] ▪Register R specifies start of memory region ▪Constant displacement D specifies offset movq 8(%rbp),%rdx Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 22 Carnegie Mellon Simple Memory Addressing Modes  Normal (R) Mem[Reg[R]] ▪Register R specifies memory address ▪Aha! Pointer dereferencing in C movq (%rcx),%rax  Displacement D(R) Mem[Reg[R]+D] ▪Register R specifies start of memory region ▪Constant displacement D specifies offset movq 8(%rbp),%rdx Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 31 Carnegie Mellon Complete Memory Addressing Modes  Most General Form ▪ D: ▪ Rb: ▪ Ri: ▪ S: D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] Constant “displacement” 1, 2, or 4 bytes Base register: Any of 16 integer registers Index register: Any, except for %rsp Scale: 1, 2, 4, or 8 (why these numbers?)  Special Cases (Rb,Ri) D(Rb,Ri) (Rb,Ri,S) Mem[Reg[Rb]+Reg[Ri]] Mem[Reg[Rb]+Reg[Ri]+D] Mem[Reg[Rb]+S*Reg[Ri]] Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 32 Carnegie Mellon Today: Machine Programming I: Basics  History of Intel processors and architectures  Assembly Basics: Registers, operands, move  Arithmetic & logical operations  C, assembly, machine code Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 35 Carnegie Mellon Address Computation Instruction  leaq Src, Dst ▪ Src is address mode expression ▪ Set Dst to address denoted by expression  Uses ▪ Computing addresses without a memory reference ▪ E.g., translation of p = &x[i]; ▪ Computing arithmetic expressions of the form x + k*y ▪ k = 1, 2, 4, or 8  Example Converted to ASM by compiler: long m12(long x) { return x*12; } Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 36 leaq (%rdi,%rdi,2), %rax # t = x+2*x salq $2, %rax # return t<<2 Carnegie Mellon Some Arithmetic Operations  Two Operand Instructions: Format Computation addq Src,Dest subq Src,Dest imulq Src,Dest shlq Src,Dest sarq Src,Dest shrq Src,Dest xorq Src,Dest andq Src,Dest orq Src,Dest Dest = Dest + Src Dest = Dest − Src Dest = Dest * Src Dest = Dest << Src Dest = Dest >> Src Dest = Dest >> Src Dest = Dest ^ Src Dest = Dest & Src Dest = Dest | Src
Synonym: salq Arithmetic Logical
 Watch out for argument order! Src,Dest (Warning: Intel docs use “op Dest,Src”)
 No distinction between signed and unsigned int (why?) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Some Arithmetic Operations  One Operand Instructions
incq Dest decq Dest negq Dest notq Dest
Dest = Dest + 1 Dest=Dest−1 Dest = − Dest Dest = ~Dest
 See book for more instructions
▪ Depending how you count, there are 2,034 total x86 instructions ▪ (If you count all addr modes, op widths, flags, it’s actually 3,683)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Activity
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Carnegie Mellon
Today: Machine Programming I: Basics
 History of Intel processors and architectures  Assembly Basics: Registers, operands, move  Arithmetic & logical operations
 C, assembly, machine code
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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Carnegie Mellon
Turning C into Object Code
▪ Code in files p1.c p2.c
▪ Compile with command: gcc –Og p1.c p2.c -o p
▪ Use basic optimizations (-Og) [New to recent versions of GCC] ▪ Put resulting binary in file p
text
text binary
C program (p1.c p2.c)
Compiler (gcc –Og -S)
Asm program (p1.s p2.s)
Assembler (gcc or as)
Object program (p1.o p2.o)
Linker (gcc or ld)
Executable program (p) Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
binary
Static libraries (.a)
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Compiling Into Assembly
C Code (sum.c)
Generated x86-64 Assembly
long plus(long x, long y);
void sumstore(long x, long y, long *dest)
{
long t = plus(x, y);
*dest = t;
}
Obtain (on shark machine) with command
gcc –Og –S sum.c Produces file sum.s
Warning: Will get very different results on non-Shark machines (Andrew Linux, Mac OS-X, …) due to different versions of gcc and different compiler settings.
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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sumstore:
pushq %rbx
movq %rdx, %rbx call plus
movq %rax, (%rbx) popq %rbx
ret

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What it really looks like
.globl sumstore
.type sumstore, @function sumstore:
.LFB35:
.cfi_startproc
pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdx, %rbx call plus
movq %rax, (%rbx) popq %rbx .cfi_def_cfa_offset 8 ret
.cfi_endproc
.LFE35:
.size sumstore, .-sumstore
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What it really looks like
.globl sumstore
.type sumstore, @function
sumstore:
.LFB35:
.cfi_startproc
pushq %rbx
.cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdx, %rbx call plus
movq %rax, (%rbx) popq %rbx .cfi_def_cfa_offset 8 ret
.cfi_endproc
.LFE35:
.size sumstore, .-sumstore
Things that look weird and are preceded by a ‘.’ are generally directives.
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
46
sumstore:
pushq %rbx
movq %rdx, %rbx
call plus
movq %rax, (%rbx)
popq %rbx
ret

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Assembly Characteristics: Data Types
 “Integer” data of 1, 2, 4, or 8 bytes ▪ Data values
▪ Addresses (untyped pointers)
 Floating point data of 4, 8, or 10 bytes
 (SIMD vector data types of 8, 16, 32 or 64 bytes)
 Code: Byte sequences encoding series of instructions
 No aggregate types such as arrays or structures ▪ Just contiguously allocated bytes in memory
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Assembly Characteristics: Operations
 Transfer data between memory and register ▪ Load data from memory into register
▪ Store register data into memory
 Perform arithmetic function on register or memory data
 Transfer control
▪ Unconditional jumps to/from procedures ▪ Conditional branches
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Object Code
Code for sumstore
 Assembler
▪ Translates .s into .o
▪ Binary encoding of each instruction
▪ Nearly-complete image of executable code
▪ Missing linkages between code in different files
 Linker
▪ Resolves references between files
▪ Combines with static run-time libraries
▪ e.g., code for malloc, printf ▪ Some libraries are dynamically linked
▪ Linking occurs when program begins execution
0x0400595: 0x53 0x48 0x89 0xd3 0xe8 0xf2 0xff 0xff 0xff 0x48 0x89 0x03 0x5b 0xc3
• •
•
Total of 14 bytes
Each instruction 1, 3, or 5 bytes
Starts at address
0x0400595
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Machine Instruction Example
*dest = t;
movq %rax, (%rbx)
 C Code
▪ Store value t where designated by
dest
 Assembly
▪ Move 8-byte value to memory
▪ Quad words in x86-64 parlance ▪ Operands:
t: Register %rax dest: Register %rbx *dest: MemoryM[%rbx]
 Object Code
▪ 3-byte instruction
▪ Stored at address 0x40059e
0x40059e: 48 89 03
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Disassembling Object Code Disassembled
0000000000400595 :
400595: 53
400596: 48 89 d3 400599: e8 f2 ff ff ff 40059e: 48 89 03 4005a1: 5b
4005a2: c3
push %rbx
mov %rdx,%rbx callq 400590 mov %rax,(%rbx) pop %rbx
retq
 Disassembler
objdump –d sum
▪ Useful tool for examining object code
▪ Analyzes bit pattern of series of instructions
▪ Produces approximate rendition of assembly code
▪ Can be run on either a.out (complete executable) or .o file
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Alternate Disassembly Disassembled
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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 Within gdb Debugger
▪ Disassemble procedure gdb sum
disassemble sumstore
Dump of assembler code for function sumstore:
0x0000000000400595 <+0>: push 0x0000000000400596 <+1>: mov 0x0000000000400599 <+4>: callq 0x000000000040059e <+9>: mov 0x00000000004005a1 <+12>:pop 0x00000000004005a2 <+13>:retq
%rbx
%rdx,%rbx 0x400590 %rax,(%rbx) %rbx

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Alternate Disassembly
Object Code
Disassembled
0x0400595: 0x53 0x48 0x89 0xd3 0xe8 0xf2 0xff 0xff 0xff 0x48 0x89 0x03 0x5b 0xc3
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
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 Within gdb Debugger
▪ Disassemble procedure
gdb sum
disassemble sumstore
▪ Examine the 14 bytes starting at sumstore x/14xb sumstore
Dump of assembler code for function sumstore:
0x0000000000400595 <+0>: push 0x0000000000400596 <+1>: mov 0x0000000000400599 <+4>: callq 0x000000000040059e <+9>: mov 0x00000000004005a1 <+12>:pop 0x00000000004005a2 <+13>:retq
%rbx
%rdx,%rbx 0x400590 %rax,(%rbx) %rbx

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What Can be Disassembled?
% objdump -d WINWORD.EXE WINWORD.EXE: file format pei-i386
No symbols in “WINWORD.EXE”.
Disassembly of section .text:
30001000 <.text>: 30001000: 30001001: 30001003: 30001005: 3000100a:
55 push %ebp
8b ec mov %esp,%ebp
Reverse engineering forbidden by
6a ff push $0xffffffff
Microsoft End User License Agreement
68 90 10 00 30 push $0x30001090 68 91 dc 4c 30 push $0x304cdc91
 Anything that can be interpreted as executable code
 Disassembler examines bytes and reconstructs assembly source
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Machine Programming I: Summary  History of Intel processors and architectures
▪ Evolutionary design leads to many quirks and artifacts
 C, assembly, machine code
▪ New forms of visible state: program counter, registers, …
▪ Compiler must transform statements, expressions, procedures into low-level instruction sequences
 Assembly Basics: Registers, operands, move
▪ The x86-64 move instructions cover wide range of data movement
forms
 Arithmetic
▪ C compiler will figure out different instruction combinations to
carry out computation
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