1007ICT / 1807ICT / 7611ICT Computer Systems & Networks
4A: The Processor
Last Section: Digital Logic and Digital Circuits
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Topics Covered:
⚫ Digital logic, Basic logic gates, Boolean algebra
⚫ Combinatoriallogicgates
⚫ Logicunit,Selectionlogic,Decoderlogic
⚫ Multiplexinganddemultiplexing
⚫ Arithmetic logic unit
⚫ Binarymultiplicationanddivision
⚫ Shifting
⚫ SequentialLogic
⚫ Data latches, S-R Latch
⚫ Clocksandsynchronisation
⚫ Registers,Buses,Computermemory
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Lecture Content
⚫ Learningobjectives
⚫ Centralprocessingunit(CPU)
⚫ Arithmetic Logic Unit (ALU)
⚫ RegistersandControlunit
⚫ Data, instructions and instruction sets
⚫ Microprograms
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Learning Objectives
In this lecture you will have:
⚫ Gained an appreciation of the Central processing unit
⚫ Gained an understanding of the Arithmetic Logic Unit
⚫ Gained an understanding of Registers
⚫ Gained an understanding of the Control unit
⚫ Gained an understanding of data, instructions and instruction sets
⚫ Learnt the basics of writing Micro programs
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Central Processing Unit (Chapter 7)
⚫ The CPU is the heart of a computer and its function is to execute programs which are stored in main memory.
⚫ Instructions are fetched, examined and executed sequentially.
⚫ A processor is composed of several distinct parts: ⚫ Acontrolunit
Arithmetic logic unit (ALU) May include some memory
Called the Datapath Called on-chip cache
⚫ Special purpose registers (Section 3.6)
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Central Processing Unit (Section 3.5 and Chapter 7)
Processors have 3 main buses for transferring information
⚫ Data bus
⚫ Control bus
⚫ Address bus
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Sub-units in a simple processor (Section 7.2)
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Arithmetic and Logic Unit (ALU) (Section 7.2)
⚫ The ALU is the component that performs data transformations on the data stored in memory.
⚫ Performs the following functions:
⚫ Mathematical:Add,Subtract
⚫ Logical:AND,OR,XOR,Shifts
⚫ Compound: Multiply and Divide (with register support)
⚫ It accepts 2 data words (A and B) as inputs and outputs a single data word (X)
⚫ Functions are selected via multi- bit control input (Select)
AB Select ALU
XA LShift
XA RShift
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Registers (Sections 3.6 and 7.2)
The registers are used to store short-term results.
⚫ Accumulator (ACC) refers to a general purpose register that holds the last computed result. This register is referred to in the textbook as Register X
⚫ Program counter or PC holds the memory address of the next instruction to be executed
⚫ Instruction register or IR holds the actual instruction being executed
⚫ Memory Address register or MAR holds the address of a memory location to read/write from.
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Registers (Sections 3.6 and 7.2)
⚫ Memory Buffer register or MBR holds the data value that is being stored or retrieved from the memory location currently specified by MAR.
⚫ Condition Code register holds the current status of the machine after completing the previous operation
⚫ Stack Pointer holds the memory address of the most recently saved register data
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Control Unit (Section 7.2)
⚫ The control unit generates control signals for all parts of the processor to coordinate its operation.
⚫ Keeps track of what sequence of steps the processor must perform to accomplish a processing operation.
⚫ For each step of a processor’s operation it
⚫ Selects ALU function to perform
⚫ Tells registers when to load new input values ⚫ Selectsmultiplexorinputs
⚫ Tells memory when to read / write data
Execute Instruction Code
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Data and Instruction Codes (Section 3.7)
⚫ Data – information to be processed during the
execution of a program. (integer, float, char, etc).
⚫ Instruction Code – tells the processor what to do
⚫ Instruction codewords are normally organised into groups of bits;
⚫ Opcode: Actual operation to be performed (Opcode may be split into instruction and addressing mode. Addressing mode discussed later)
⚫ Operand: The data or memory address to read/write
⚫ Example: assume we have a codeword that has a 4
bit opcode & a 12 bit Operand
0x 200➔Load (1) content of memory location 200 into processor 0x 304➔Start executing (2) from code at memory location 304 0x 010➔Store (3) the processor output to memory address 10
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Opcode and operand example
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Instruction Sets (Section 3.7)
⚫ The set of instruction codes used to control a processor is called an instruction set.
⚫ Instruction sets vary and are tied to a specific processor
⚫ Each opcode in an instruction set is interpreted by a processor’s control unit to perform a different function. EG
⚫ 0000 = ADD operation
⚫ 0010 = JMP goto operation
⚫ 0100 = LST shift data left
⚫ 0110 = AND operation
0001 = LOD read from memory 0011 = STO save to memory 0101 = RST shift data right 0111 = XOR operation
⚫ Instruction set sizes can vary from 20 to 300 operations.
⚫ Machines with many instructions are called CISC (Complex
Instruction Set Computers)
⚫ Machines with few instructions are called RISC (Reduced Instruction Set Computers)
⚫ Compilers can generate many instructions from one high-level language statement.
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Addressing Modes
Processors interpret the operand field in an instruction in different ways to obtain the data to be used in an operation.
The way they are interpreted is called the addressing mode The addressing mode may be part of the opcode
Addressing Mode
Effective Address (Interpretation of operand)
the data is part of the instruction
the address of the data is given in the instruction
the address of the address of the data is in the instruction
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Addressing Modes Example
⚫ Given the operand value 800, what value is loaded into the accumulator for each
addressing mode?
800 … 900 … 1000 … 1100 … 1600
Value Loaded into ACC
Immediate (use operand as is)
(use operand as address)
(use operand as address of address)
Note: Indirect addressing mode allows us to manipulate the address of an operand dynamically (ie. during runtime) which is useful for working with some types of more advanced data structures.
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Von Model (Section 1.3)
⚫ NamedafterJohnVonNeumann.Alsocalledthestored program model (textbook)
⚫ Bothdataandinstructioncodesarestoredinmainmemory but often in separate locations
⚫ Instructions are ‘fetched’ from the memory location that is addressed by the Program Counter (PC) register.
⚫ Instructionsarejustword-sizedbinarycodesthatare interpreted to be instructions and decoded as such.
⚫ If instead, actual data is accidentally fetched then it will be also decoded and erroneously interpreted as an instruction.
⚫ In most computing models this is avoided since memory is typically split into distinct data and code segments.
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Instruction Execution (Section 3.4)
A processor executes each instruction as a
sequence of small steps called a micro-program
1. Fetch the next instruction from memory into an Instruction
Register (IR).
2. Increment the Program Counter (PC) register to point to the next instruction.
3. Determine the type of the instruction just fetched.
4. If the instruction uses data stored in memory, fetch the data,
into internal CPU registers.
5. Execute the instruction.
6. Store the result in the appropriate place.
7. GOTO step 1.
be broken down further into
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This is called the
Each small step in the Fetch-Execute-Cycle can
instructions.
Micro-programs (Section 7.3)
⚫ Micro programs are written using micro-instructions
⚫ We can use a Register Transfer Language notation to unambiguously specify our micro-instructions
⚫ Let R1R2 denote a transfer of data from register R2 to register R1
⚫ Let M[MAR] denote the data stored in memory at location MAR
⚫ Higher level instructions are performed as a sequence of microinstructions for example
⚫ Fetch next instruction
1. MARPC // setup to read instruction
2. MBR M[MAR] // get instruction from memory
3. IR MBR opcode part // load it into instruction reg
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Micro-program Examples
Jump to specified address
1. PC MBR
Store Accumulator value to memory
Add value in memory to accumulator
1. MAR MBR
2. MBR ACC
3. M[MAR] MBR
Clear Accumulator
// set address to write to // set data to write
// write data to memory
1. MAR MBR
2. MBR M[MAR]
3. ACC MBR + ACC
// set address to read from // read value from memory // write data to memory
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A Simple program
⚫ In this example the instruction format is
⚫ 4 bit opcodes
⚫ 12 bits operands
⚫ 1➔Load 3➔Add ⚫ 4➔Store 7➔Halt
Instruction Trace: Load 104
Program Code
Instruction
Initial value
MBR M[MAR]
IR MBR.opcode
Get Operand
MAR MBR.oper
MBR M[MAR]
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Program Code
Instruction
⚫ In this example the instruction format is
⚫ 4 bit opcodes
⚫ 12 bits operands
⚫ 1➔Load 3➔Add ⚫ 4➔Store 7➔Halt
Instruction Trace: Add 105
Initial value
MBR M[MAR]
IR MBR.opcode
Get Operand
MAR MBR.oper
MBR M[MAR]
ACCACC+MBR
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Have studied:
⚫ Central processing unit ⚫ Instruction sets
⚫ Micro programs
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⚫ Simple processor datapath
⚫ Fetch / decode / execute cycle ⚫ General purpose registers
⚫ Stack based processors
⚫ Input / Output models
⚫ Interrupts
© . Revised and updated by , , and Wee Lum 24
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