代写代考 1007ICT / 1807ICT / 7611ICT Computer Systems & Networks

1007ICT / 1807ICT / 7611ICT Computer Systems & Networks
3C. Digital Logic and Digital Circuits

Last Lecture:

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Topics Covered:
• Logic unit, Selection logic, Decoder logic
• Multiplexing and Demultiplexing
• Half and Full adders

Lecture Content
 Learningobjectives
 Arithmeticlogicunit
 Binarymultiplicationanddivision
 Shifting
 SequentialLogic
 Datalatches,S-RLatch
 Clocksandsynchronisation
 Registers,Buses,Computermemory
© . Revised and updated by , , and Wee Lum 3

Learning Objectives
At the end of this lecture you will have gained an understanding of:
 Arithmetic logic unit
 Binary multiplication and division
 Shifting
 Sequential Logic
 Data latches, S-R Latch
 Clocks and synchronisation
 Registers, Buses, Computer memory
© . Revised and updated by , , and Wee Lum 4

ALU – Arithmetic Logic Unit (Section 7.2)
 The ALU is a general processing element
 It puts everything we have learnt together
 ALUs are combined in parallel for multi-bit versions
Full Adder
© . Revised and updated by , , and Wee Lum 5

Multiplication and Division By 2
To multiply by 2 in binary, shift bits left and insert a zero at the right hand side.
00012 = 110 00102 = 210 01002 = 410
To divide by 2 in binary, shift bits right and insert a zero at the left hand side.
0 Carry out
01112 = 710 00112 = 310 00012 = 110
© . Revised and updated by , , and Wee Lum 6

 Wecanusemultiplexorstoshiftbitsleftandright.
 Weneedtoselecteachoutputbittobetheinputbit
on its left or right side
Shift Left
Shift Right
Sign or 0 Left / Right
4 bit shifter
D3 D2 D1 D0
X3 X2 X1 X0
© . Revised and updated by , , and Wee Lum 7

What if we also want the shifter to not shift or to set the output to zero? Use a 4-input multiplexor
D3 D2 D1 D0
TLRZ TLRZ TLRZ TLRZ
Sign or 0 SEL
X3 X2 X1 X0
© . Revised and updated by , , and Wee Lum Multiplication
 TomultiplybyothernumberssayA*B–wecouldaddAto itself B times, but it’s faster to use shifts and adds like this…
 The powers of 2 you need to add to get the multiplicand determines the number combination of shifts and addition we need to perform on the multiplier (ie the 1s in its binary value)
 Let << denote the binary left shift operator:  10x5=(10x4)+(10x1)=1100102 10 x 4 10 x 1 1010 << 2 1010 << 0 = 1002 + 12 =4+1  10x7=(10x4)+(10x2)+(10x1)=10001102 10 x 4 10 x 2 10 x 1 1010 << 2 1010 << 1 1010 << 0 =1002 +102 +12 =4+2+1 © . Revised and updated by , , and Wee Lum 9 Multiplication Example Multiply SumA x B Check every bit position of B so that if:  bitposition0ofBis1,addAtothesum.  bitposition1ofBis1,addA<<1tothesum.  bitposition2ofBis1,addA<<2tothesum.  bitposition3ofBis1,addA<<3tothesum.  etc.. 10 × 13 = 130 10102 x 11012 Note: 10102 << 1 is not added as bit position 1 of 11012 is 0. 10102 <<0 10102 10102 <<2 1010002 + 10102 <<3 10100002 + 100000102 = 130 © . Revised and updated by , , and Wee Lum 10 Arbitrary Division  Forarbitrarydivisionwecanusebasicbinarylong division. 13 / 3 = 1 1 0 1 / 1 1 = 4 Remainder 1 1 0 0 Answer: 4 1 1 1 1 01 0 0 1 Remainder: 1 © . Revised and updated by , , and Wee Lum 11 Sequential Logic (Section 2.5) Previously we looked at which produces an output as some combination of the input values. Sequential logic produces an output that depends not only on the inputs but on previous inputs as well. combinatorial logic Logic Function Memory Cell © . Revised and updated by , , and Wee Lum 12 Data Latches  Noneofthelogicfunctionswesawbeforecanstore any data... bits come in and go straight out again.  Considerthefollowinglogic: Latch is a logic function that can store bits  Thiscanstorea‘1’bitbutnota‘0’bit.Weneed another input to tell it to store a ‘0’bit, like this. © . Revised and updated by , , and Wee Lum 13 S-R Latch (RS-Bistable)  Let’srearrangethelogicabitasfollowsusingthe rules of logic (using DeMorgan’s Theorem) :  TheresultiscalledtheSR-latch(orRS-Bistable)  BothinputsarenormallyOFF(at0)  TheSinputsetsthedatastateto1  TheRinputsetsthedatastateto0  HavingbothtoONatonceisillegal  WhenbothareOFFthelatchisstable  EitherQ=0andQ=1  Or Q=1andQ=0 © . Revised and updated by , , and Wee Lum 14 Clocks and Synchronisation  Themainproblemwithlatchesisthataftertheinputs change the output is unstable for a short time.  Ifwedirectlyconnecttheoutputofalatchtotheinput of another circuit then the circuit may be unstable  Aclocksignalcancontrolwhenalatchcanloadits inputs after they are stable (ie when the clock is high)  Clockedlatchesaresometimescalled  Thefastertheclock–thefasterthatdatacanbe stored/read into a latch © . Revised and updated by , , and Wee Lum 15 Data Latch (Level-Triggered D-Type bistable)  WecanuseDeMorgan’sTheoremagaintoconvertthe Latch to use NAND gates that is set using OFF inputs.  BothinputsarenormallyON  SettingStoOFFsetsthedatastateto1  SettingRtoOFFsetsthedatastateto0  HavingbothtoOFFatonceisillegal  WhenbothareONthelatchis  Asimplemodificationoftheclockedversionletsus create the useful Latch or D © . Revised and updated by , , and Wee Lum 16 Bits / Bytes / Words  Ifcomputermemorywasonlyaddressedonebitata time, it would take quite a long time to retrieve enough data to any serious processing.  Mostcomputersdonotprocessindividualbitsbut instead group them together into multiples of 8 eg 8, 16, 32, 64 etc.  Thesegroupsaredescribedas length varies depending on the machine.  An8bitwordiscalleda words, but word Nibble so 1 byte = 2 nibbles  A4bitwordiscalleda  Therearenospecialnamesforothersizedwords. © . Revised and updated by , , and Wee Lum 17 Data Latches (Level-Triggered D-Type bistables) allow us to store 1 bit of information but we can group them in parallel This is called a of multiple bits. register to store data consisting wordsize is the number of bits a register D3 D2 D1 D0 Q3 Q2 Q1 Q0 Simple 4 bit register using D-Latches 8 bit register © . Revised and updated by , , and Wee Lum 18  Wecanconnectlogicgatestogetherwithlinesthat convey single bits of information between them.  Withregisterswehavemultipleinputandoutput lines to convey N-bits of data to and from the register  Abusisasetoflinesthatsimultaneouslyconveysa set of bits between components.  Twotypesofbusesarecommonincomputer systems: point-to-point, and multipoint buses. Register A Point to Point Bus Shared Bus (Multipoint) Register B © . Revised and updated by , , and Wee Lum 19 Multipoint Buses use special gates with “tristate” outputs that can be connected together Computer Memory (Section 3.3)  Wecanuseanarrayofregistersinseriestocreate a memory bank.  Everyregisterlocationinthememorybankisgiven a unique address that is used so that we can select it and access the data stored in it.  An8bitmachinewoulduseabankof8bitregisters and access 8 bit words from memory at a time. Location Bit Fetching word at address 003 004 would return the value 011001002 = 6416 = 10010 003 002 001 © . Revised and updated by , , and Wee Lum 20 Computer Memory  A memory bank needs some way of selecting memory addresses  A special register called a memory address register ( is internal to the CPU contains the physical location of the next memory address that will be selected for reading/writing.  Another internal register called the Memory Buffer Register ( MAR) which MBR) MDR)] holds the value that was read [or Memory Data Register ( /written to the selected memory address. Location Bit Read/Write control © . Revised and updated by , , and Wee Lum 21 Have considered:  Arithmetic logic unit  Binary multiplication and division  Shifting  Sequential Logic  Data latches, S-R Latch  Clocks and synchronisation  Registers, Buses, Computer memory © . Revised and updated by , , and Wee Lum 22  Processors © . Revised and updated by , , and Wee Lum 23 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com