Assembly Language for x86 Processors 7th Edition
CHAPTER 2: X86 PROCESSOR ARCHITECTURE
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Chapter Overview
General Concepts
IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
General Concepts
Basic microcomputer design
Instruction execution cycle
Reading from memory
How programs run
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
Basic Microcomputer Design
clock synchronizes CPU operations
control unit (CU) coordinates sequence of execution steps
ALU performs arithmetic and bitwise processing
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Synchronizes all CPU and BUS operations
Machine (clock) cycle measures time of a single operation
Clock is used to trigger events
A cycle duration is the reciprocal of the clock’s speed
1 GHz: cycle duration 1 billionth of a second, 1 nanosecond
Wait state, empty cycle
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Instruction Execution Cycle
Instruction Execution Cycle
Fetch operands
Store output
Reading from Memory
Multiple machine cycles are required when reading from memory, because it responds much slower than the CPU. The steps are:
Place the address of the value you want to read on the address bus.
Assert (changing the value of) the processor’s RD (read) pin.
Wait one clock cycle for the memory chips to respond.
Copy the data from the data bus into the destination operand
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Cache Memory
High-speed expensive static RAM both inside and outside the CPU.
Level-1 cache: inside the CPU
Level-2 cache: outside the CPU
Cache hit: when data to be read is already in cache memory
Cache miss: when data to be read is not in cache memory.
Online reading: How Computer Memory Works
http://computer.howstuffworks.com/computer-memory4.htm
How a Program Runs
As soon as the program begins running, it’s called a Process
A process has its memory and may contains multiple Threads
Multitasking
OS can run multiple programs at the same time.
Multiple threads of execution within the same program.
Scheduler utility assigns a given amount of CPU time to each running program.
Rapid switching of tasks
gives illusion that all programs are running at once
the processor must support task switching.
Task switching: Context, Priority
IA-32 Processor Architecture
Short for “Intel Architecture, 32-bit”
Modes of operation
Basic execution environment
Floating-point unit
Intel Microprocessor history
Modes of Operation
Protected mode
native mode (Windows, Linux)
Real-address mode
native MS-DOS
System management mode
power management, system security, diagnostics
Virtual-8086 mode
hybrid of Protected
each program has its own 8086 computer
allows the execution of real mode applications that are incapable of running directly in protected mode while the processor is running a protected mode operating system.
Basic Execution Environment
Addressable memory
General-purpose registers
Index and base registers
Specialized register uses
Status flags
Floating-point, MMX, XMM registers
Addressable Memory
Protected mode
The range of memory is 4 GB
32-bit address
Real-address and Virtual-8086 modes
1 MB space
20-bit address
General-Purpose Registers
Named storage locations inside the CPU, optimized for speed.
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Accessing Parts of Registers
Use 8-bit name, 16-bit name, or 32-bit name
Applies to EAX, EBX, ECX, and EDX
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Index and Base Registers
Some registers have only a 16-bit name for their lower half:
Some Specialized Register Uses (1 of 2)
General-Purpose
EAX – accumulator
ECX – loop counter
ESP – stack pointer
ESI, EDI – index registers
EBP – extended frame pointer (stack)
CS – code segment
DS – data segment
SS – stack segment
ES, FS, GS – additional segments
Some Specialized Register Uses (2 of 2)
EIP – instruction pointer
IP for 16-bit
status and control flags
each flag is a single binary bit
Status Flags
The Carry flag (CF) is set when the result of an unsigned arithmetic operation is too large to fit into the destination.
The Overflow flag (OF) is set when the result of a signed arithmetic operation is too large or too small to fit into the destination.
The Sign flag (SF) is set when the result of an arithmetic or logical operation generates a negative result.
The Zero flag (ZF) is set when the result of an arithmetic or logical operation generates a result of zero.
The Auxiliary Carry flag (AC) is set when an arithmetic operation causes a carry from bit 3 to bit 4 in an 8-bit operand.
The Parity flag (PF) is set if the least-significant byte in the result contains an even number of 1 bits. Otherwise, PF is clear. In general, it is used for error checking when there is a possibility that data might be altered or corrupted.
If the result of the last operation were 26 (11010 in binary), the parity flag would be 0 since the number of set bits is odd. Similarly, if the result were 10 (1010 in binary) then the parity flag would be 1.
Floating-Point, MMX, XMM Registers
Eight 80-bit floating-point data registers
ST(0), ST(1), . . . , ST(7)
arranged in a stack
used for all floating-point arithmetic
Eight 64-bit MMX registers
a single instruction, multiple data (SIMD) instruction set architecture
MMX instructions operate in parallel on the data values contained in MMX registers
Eight 128-bit XMM registers for single-instruction multiple-data (SIMD) operations
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CISC and RISC
CISC – complex instruction set
large instruction set
high-level operations
requires microcode interpreter
examples: Intel 80×86 family
RISC – reduced instruction set
simple, atomic instructions
small instruction set
directly executed by hardware
ARM (Advanced RISC Machines)
ARM Assembly Language Programming
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IA-32 Memory Management
Real-address mode
Calculating linear addresses
Protected mode
Multi-segment model
Real-Address mode
1 MB RAM maximum addressable
Application programs can access any area of memory
Single tasking
Supported by MS-DOS operating system
Protected Mode
4 GB addressable RAM
(00000000 to FFFFFFFFh)
Each program assigned a memory partition which is protected from other programs
Designed for multitasking
Supported by Linux & MS-Windows
Supported directly by the CPU
Divides each segment into 4096-byte blocks called pages
Sum of all programs can be larger than physical memory
Part of running program is in memory, part is on disk
Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages
Page fault – issued by CPU when a page must be loaded from disk
64-Bit Processors
64-Bit Operation Modes
Compatibility mode – can run existing 16-bit and 32-bit applications (Windows supports only 32-bit apps in this mode)
64-bit mode – Windows 64 uses this
Basic Execution Environment
addresses can be 64 bits (48 bits, in practice)
16 64-bit general purpose registers
64-bit instruction pointer
64-Bit General Purpose Registers
32-bit general purpose registers:
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D
64-bit general purpose registers:
RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9, R10, R11, R12, R13, R14, R15
64-bit Processors
64-bit linear address space
Intel: Pentium Extreme, Xeon, Celeron D, Pendium D, Core 2, and Core i7
IA-32e Mode
Compatibility mode for legacy 16- and 32-bit applications
64-bit Mode uses 64-bit addresses and operands
x64 Assembly Information
x64 Registers: http://www.ntcore.com/files/vista_x64.htm
x86-64: http://en.wikipedia.org/wiki/X86-64
Components of an IA-32 Microcomputer
Motherboard
Video output
Input-output ports
Motherboard
CPU socket
External cache memory slots
Main memory slots
BIOS chips
Sound synthesizer chip (optional)
Video controller chip (optional)
IDE, parallel, serial, USB, video, keyboard, joystick, network, and mouse connectors
PCI(Peripheral Component Interconnect) bus connectors (expansion cards)
Intel D850MD Motherboard
dynamic RAM
Pentium 4 socket
IDE drive connectors
mouse, keyboard, parallel, serial, and USB connectors
bus connector for a high-speed video card
Power connector
memory controller hub
Diskette connector
I/O Controller
Firmware hub
Audio chip
Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification
Intel 965 Express Chipset
Video Output
Video controller
on motherboard, or on expansion card
AGP (accelerated graphics port technology)*
Video memory (VRAM)
Video CRT Display
uses raster scanning
horizontal retrace
vertical retrace
Direct digital LCD monitors
no raster scanning required
* This link may change over time.
Sample Video Controller (ATI Corp.)
128-bit 3D graphics performance powered by RAGE™ 128 PRO
3D graphics performance
Intelligent TV-Tuner with Digital VCR
TV-ON-DEMAND™
Interactive Program Guide
Still image and MPEG-2 motion video capture
Video editing
Hardware DVD video playback
Video output to TV or VCR
read-only memory
erasable programmable read-only memory, ultraviolet light
Dynamic RAM (Random Access Memory) (DRAM)
inexpensive; must be refreshed constantly
Static RAM (SRAM)
expensive; used for cache memory; no refresh required
Video RAM (VRAM)
dual ported; optimized for constant video refresh
complimentary metal-oxide semiconductor
system setup information
Input-Output Ports
USB (universal serial bus)
intelligent high-speed connection to devices
480 megabits/second (2.0), 12 mb/s (1.0)
USB hub connects multiple devices
enumeration: computer queries devices
supports hot connections
short cable, high speed
common for printers
bidirectional, parallel data transfer
Intel 8255 controller chip
Input-Output Ports (cont)
RS-232 serial port
one bit at a time
uses long cables and modems
16550 UART (universal asynchronous receiver transmitter)
programmable in assembly language
Device Interfaces
ATA (advanced technology attachment) host adapters
intelligent drive electronics (hard drive, CDROM)
SATA (Serial ATA)
inexpensive, fast, bidirectional
high speed (800 MB/sec), many devices at once
small amounts of data, short distances, low power usage
Wi-Fi (wireless Ethernet)
IEEE 802.11 standard, faster than Bluetooth
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
Levels of Input-Output
Level 3: High-level language function
examples: C++, Java
portable, convenient, not always the fastest
Level 2: Operating system
Application Programming Interface (API)
extended capabilities, lots of details to master
Level 1: BIOS
drivers that communicate directly with devices
OS security may prevent application-level code from working at this level
Displaying a String of Characters
When a HLL program displays a string of characters, the following steps take place:
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Programming levels
Assembly language programs can perform input-output at each of the following levels:
Central Processing Unit (CPU)
Arithmetic Logic Unit (ALU)
Instruction execution cycle
Multitasking
Floating Point Unit (FPU)
Complex Instruction Set
Real mode and Protected mode
Motherboard components
Memory types
Input/Output and access levels
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
IRVINE, KIP R. ASSEMBLY LANGUAGE FOR X86 PROCESSORS 6/E, 2010.
Central Processor Unit
Memory Storage
control bus
address bus
sends program
gets starting
cluster from
searches for
program in
returns to
16-bit Segment Registers
32-bit General-Purpose Registers
8 bits + 8 bits
80-bit Data Registers
FPU Data Pointer
Tag Register
Control Register
Status Register
FPU Instruction Pointer
Opcode Register
16-bit Control Registers
48-bit Pointer Registers
Application Program
OS Function
BIOS Function
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