DESN2000: Engineering Design & Professional Practice (EE&T)
Input and output interfaces
School of Electrical Engineering & Telecommunications Graduate School of Biomedical Engineering
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Biomedical Microsystems Lab
• GPIO intricacies
• D/A (digital-to-analog) converters
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• The LPC2478 has lots of I/Os (all mem mapped).
• The simplest type:
5 Fast General Purpose I/O ports (GPIO), each with 32 pins:
• Port0 • Port1 • Port2 • Port3 • Port4
P0.1 Port 0
P4.1 Port 4
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Five types of control registers associated with each port.
Each register has:
a particular name, specifying its purpose
an address in memory space for fast GPIO, that is 0x3FFFC000 – 0x3FFFFFFF.
Each port has
DIR PIN SET CLR MASK
GPIO Other func
Memory mapped registers
Each pin is mapped to GPIO by default.
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• Consider the following C code for blinking LEDs connected to pin0.0 – pin0.7 ON and OFF for ever.
#define FIO0DIR *(volatile unsigned int *) (0x3FFFC000) // port-0 dir #define FIO0PIN *(volatile unsigned int *) (0x3FFFC014). // port-0 pin
int main(void) { FIO0DIR = 0xFF;
while (1) { FIO0PIN = 0xFF;
FIO0PIN = 0x00; }
return 0; }
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• Compiling to assembly: With “volatile”
Without “volatile”
FIO0DIR EQU 0x3FFFC000 FIO0PIN EQU 0x3FFFC014
AREA, LEDONOFF, CODE ENTRY
LDR R0, =FIO0DIR LDR R1, =FIO0PIN MOV R2, #0xFF
STR R2, [R0] ; out
MOV R3, #0
loop STR R2, [R1] ; blink
STR R3, [R1]; blink B loop
FIO0DIR EQU 0x3FFFC000 FIO0PIN EQU 0x3FFFC014
AREA, LEDONOFF, CODE ENTRY
LDR R0, =FIO0DIR LDR R1, =FIO0PIN MOV R2, #0xFF
STR R2, [R0] ; out
MOV R3, #0
loop STR R3, [R1] ; blink
B loop END
• Q: what happened when we omit “volatile” in the C code?
The compiler decided the first pin assignment is superfluous and optimized it out.
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• The Universal Asynchronous Receiver/ Transmitter (UART) is a protocol for serial
communication to asynchronously send / receive sequence of bits.
• A simple, inexpensive method for low-speed transmission (up to ~14 kB/s).
E.g. CPU to peripheral device.
• Line held HIGH when idle. Start bit is LOW, followed by sequence of data bits, then a stop bit.
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• Example: UART transmission with 7-bit character length, (optional) parity and 1 stop bit.
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UART register map
• All UART registers are memory mapped:
• configuration registers
• receive and transmit buffers
• status registers
• UART0 has base address 0xE00C000.
• Registers associated with it spans 0xE00C000 ~ 0xE00C030.
• Example: the Line Control Register for UART0 is at 0xE000C00C.
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UART register map
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Generic Name
Description
Bit functions and addresses
To set baud rate
8 bit Data
8 bit Data
Reserved Enable Auto- Baud Time- Out
Enable End of Auto- Baud Interrupt
UARTn Register Name & Address
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
8 bit Read Data
8 bit Write Data
0 Enable RX Line
Status Interrupt
Enable THRE Interrupt
Enable RX Data Available Interrupt
Reserved ABTOInt ABEOint
FIFOs Enabled 0 IIR3 IIR2 IIR1 IIR0
RX Trigger Reserved TX FIFO RX FIFO FIFO Reset Reset Enable
Table 377. UART Register Map
RBR Receiver Buffer (DLAB= Register
THR Transmit (DLAB= Holding 0) Register
DLL Divisor Latch (DLAB= LSB
DLM Divisor Latch (DLAB= MSB
IER Interrupt Enable (DLAB= Register
0xE000 C000
U2RBR – 0xE007 8000 U3RBR –
0xE007 C000
U0THR – 0xE000 C000 U2THR – 0xE007 8000 U3THR – 0xE007 C000
U0DLL – 0xE000 C000 U2DLL – 0xE007 8000 U3DLL – 0xE007 C000
0xE000 C004
U2DLM – 0xE007 8004 U3DLM –
0xE007 C004
U0IER – 0xE000 C004 U2IER – 0xE007 8004 U3IER – 0xE007 C004
U0IIR – 0xE000 C008 U2IIR – 0xE007 8008 U3IIR – 0xE007 C008
U0FCR – 0xE000 C008 U2FCR – 0xE007 8008 U3FCR – 0xE007 C008
0xE000 C00C
U2LCR – 0xE007 800C U3LCR –
0xE007 C00C
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LPC24XX User manual. Document No: UM10237
Interrupt driven IO
IIR FCR LCR
Interrupt ID Register
FIFO Control Register
Line Control DLAB Set Register Break
Stick Parity
Even Parity Parity Enable Select
Number of Stop Bits
Word Length Select
Config UART protocol
© 2022 UNSW Sydney
NXP Semiconductors
UM10237 Chapter 16: LPC24XX UART0/2/3
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
425 of 792
UART register map
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Table 377. UART Register Map
Generic Name
Description
Bit functions and addresses
RX TEMT THRE BI FE PE OE DR FIFO
8 bit Data
Reserved [31:10] ABTO ABEO IntClr IntClr
Reserved PulseDiv FixPulse IrDAInv IrDAEn En
MulVal DivAddVal
TXEN Reserved
UARTn Register Name & Address
Reserved [7:3] Auto Mode Start Reset
Line Status Register
Scratch Pad Register
Auto-baud Control Register
IrDA Control Register
Fractional Divider Register
Transmit Enable Register
U0LSR – 0xE000 C014 U2LSR – 0xE007 8014 U3LSR – 0xE007 C014
U0SCR – 0xE000 C01C U2SCR – 0xE007 801C U3SCR – 0xE007 C01C
0xE000 C020
U2ACR – 0xE007 8020 U3ACR –
0xE007 C020
U3ICR – 0xE000 C024 (UART3 only)
U0FDR – 0xE000 C028 U2FDR – 0xE007 8028 U3FDR – 0xE007 C028
U0TER – 0xE000 C030 U2TER – 0xE007 8030 U3TER – 0xE007 C030
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
© 2022 UNSW Sydney
NXP Semiconductors
UM10237 Chapter 16: LPC24XX UART0/2/
© NXP B.V. 2009. All rights reserve
User manual
Rev. 04 — 26 August 2009
NXP Semiconductors UM10237
UART’s register map
Chapter 16: LPC24XX UART0/2/3
Table 386. UARTn Line Control Register (U0LCR – address 0xE000 C00C, U2LCR – 0xE007 800C, U3LCR – 0xE007 C00C) bit description
For UARTs 0, 2 and 3
1:0 Word Length Select
2 Stop Bit Select
3 Parity Enable
5:4 Parity Select
6 Break Control
7 Divisor Latch Access Bit
Value Reset Value
00 5 bit character length 0 01 6 bit character length
10 7 bit character length
11 8 bit character length
0 1 stop bit. 0 1 2 stop bits (1.5 if UnLCR[1:0]=00).
0 Disable parity generation and checking. 0 1 Enable parity generation and checking.
00 Odd parity. Number of 1s in the transmitted character and 0 the attached parity bit will be odd.
01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
10 Forced “1” stick parity.
11 Forced “0” stick parity.
0 Disable break transmission. 0
1 Enable break transmission. Output pin UART0 TXD is forced to logic 0 when UnLCR[6] is active high.
0 Disable access to Divisor Latches. 0 1 Enable access to Divisor Latches.
Description
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4.8 UARTn Line Status Register (U0LSR – 0xE000 C014, U2LSR – 0xE007 8014, U3LSR – 0xE007 C014, Read Only)
The UnLSR is a read-only register that provides status information on the UARTn TX and RX blocks.
Table 387. UARTn Line Status Register (U0LSR – address 0xE000 C014,
U2LSR – 0xE007 8014, U3LSR – 0xE007 C014, Read Only) bit description
Bit Symbol Value Description Reset
Using UART
• Two steps, configure the hardware pins and the software protocol:
1. Hardware: selects the appropriate pins of LPC2478 as RXD0 (input) and TXD0 (output).
2. Software: configuring UART’s number of data bits, parity, number of stop bits, and baud rate.
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Using UART: configuring pins (HW)
• LPC2478 has 208 pins.
Fig 2. LPC2478 pinning LQFP208 package
2 4 6 8 10 12 14 16
• Pins are multifunctional:
• Row-C column-4 pin can be either GPIO0[2] or
UART0 TXD0.
• Row-D column-6 pin can be either GPIO0[3] or
UART0 RXD0.
• For UART: row-C column-4 pin should be
configured as TXD0 and Row-D column-6 pin should be configured as RXD0.
ball A1 index area
9 11 13 15 17
LPC2478FBD208
LPC2478FET208
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Pin Symbol
1 P3[27]/D27/ CAP1[0]/PWM1[4]
5 P1[4]/ENET_TX_EN
Pin Symbol
6 P1[9]/ENET_RXD0
3 P1[0]/ENET_TXD0
7 P1[14]/ENET_RX_ER
LPC2478 pinning TFBGA208 package Pin allocation table
Transparent top view
Pin Symbol
Using UART: configuring pins (HW)
• Each I/O pin (under the chip package) is connected to a multiplexer, which determines the internal circuits routed to the pin.
Other func
• There are 12 PINSEL registers (PINSEL0 – PINSEL11) for LPC2478, all memory- mapped.
• The address of PINSEL0 register is 0xE002C000.
• Set PINSEL0[5:4] to 0x01 for P0.2 to be used as TXD0.
(the pins would be 0x00 if P0.2 is used as GPIO)
• Set PINSEL0[7:6] to 0x01 for P0.3 to be used as RXD0.
(the pins would be 0x00 if P0.3 is used as GPIO)
Pin (soldering point) under the LPC248 chip
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Using UART: configuring pins (HW)
• Configuring the pins as RXD0 and TXD0 using read-modify-write:
PINSEL0 EQU 0XE002C000 LDR R5, =PINSEL0
LDR R6, [R5] ; read
BIC R6, R6, 0xF0 ; clearing bit 7~4
ORR R6, R6, #0x50 ; P0.2 to TXD0, P0.3 to RXD0 STR R6, [R5] ; write
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Using UART: configuring protocol (SW)
• Base address of UART0 configuration register is 0xE000C000.
• Address offset for registers:
• LCR0 = 0xC addressing the Line Control Register.
• LSR0 = 0x14 addressing the Status Register.
• Setting UART0 for 8 bits data, no parity, 1 stop bit, 9600 baud @ 17.75 MHz APB clock (peripheral clock, reset value 71 MHz ÷ 4).
• Baud rate: transmission speed in bits-per-second (bps).
• APB clock: clock for IO devices.
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Using UART: configuring protocol (SW)
Configuring the UART protocol:
UOSTART EQU 0XE000C000 LCR0 EQU 0XC
[R5, #LCR0]
[R5, #LCR0]
; DLAB=1,no parity, 1 stop bit, 8 bits ; write control byte to LCR
; 9600baud @ 17.75MHz APB clk
; store control byte (DLAB=1)
; DLAB=0, turn off Divisor Latch Access mode
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Using UART: writing data
• Now ready to send and receive UART data.
• Putting a character in the transmit buffer, but only after the previous character has been
transmitted (check the Transmitter Holding Register Empty bit):
UOSTART EQU 0XE000C000 LSR0 EQU 0X14
LDR R5, =UOSTART
wait LDRB R6, [R5, #LSR0] ; get buffer status
CMP R6, #0x20
STRB R0, [R5]
; THRE HI (TX buffer empty)? ; spin till buffer empty
; R0 contains the character
• For general purpose TX: write a subroutine that sends one character at a time, then call it as many times as needed to send a message out of UART0.
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Using UART: complete transmitter
AREA UARTDEMO, CODE, READONLY PINSEL0 EQU 0xE002C000
U0START EQU 0xE000C000 LCR0 EQU 0xC
LSR0 EQU 0x14 RAMSTART EQU 0x40000000
BL uartConfig
; start of LPC2478 on-chip RAM
SP, =RAMSTART ; set up stack pointer LDR R1, =CharData ; string addr
CMP A1, #0 Transmit msg till ‘/0’
BLNE transmit
BNE loop done B done
A1, [R1], #1
Mem-mapped I/O definitions
Main function
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Using UART: complete transmitter
uartConfig
STMIA SP!, {R5, R6, LR} LDR R5, =PINSEL0
LDR R6, [R5]
BIC R6, R6, 0xF0
ORR R6, R6, #0x50 STR R6, [R5]
LDR R5, =UOSTART MOV R6, #0x83
STRB R6, [R5, #LCR0] MOV R6, #0x73
STRB R6, [R5]
MOV R6, #3
STRB R6, [R5, #LCR0] LDMDB SP!, {R5, R6, PC}
UART pin configuration
UART protocol configuration
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Using UART: complete transmitter
STMIA SP!, {R5, R6, LR} LDR R5, =UOSTART LDRB R6, [R5, #LSR0] CMP R6, #0x20
STRB A1, [R5]
LDMDB SP!, {R5, R6, PC}
TX a byte at a time
DCB “Watson, come quickly!”, 0 END
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D/A converter
• In many signal processing and control applications, an analog input is sampled, processed then converted back into an analog output.
Analog in A/D Proc. D/A Analog out
• The LPC2478’s D/A converter takes a 10-bit binary value and generates a voltage on
AOUT which is proportional to a reference voltage VREF:
Aout = V Vref 1024
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D/A converter: configuring pins
• To use the D/A converter, pin P0.26 (row E, column 1) must be configured for AOUT, achieved by setting PINSEL1[21:20] (at 0xE002C004) to 0x10:
Other func
PINSEL1 21:20
EQU 0xE002C004
LDR r6, =PINSEL1
LDR r7, [r6]
OOR r7,r7, #1:SHL:21 ; set bit-21 HI
BIC r7,r7, #1:SHL:20 ; set bit-20 LO
STR r7, [r6] ; write (P0.26 now Aout)
Pin (soldering point) under the LPC248 chip
; read pin
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D/A converter: configuring DACR
DACR register (0xE006C000) is used to configure the converter
provide a value for conversion
DACR[15:6]: 10-bit value for setting AOUT. DACR[16]: Sets the DAQ’s settling speed.
Fast settling → quicker output change → use more power.
NXP Semiconductors UM10237 Chapter 29: LPC24XX Digital-to Analog Converter (DAC)
Table 599: D/A Converter Register (DACR – address 0xE006 C000) bit description
Bit Symbol Value Description Reset Value
15:6 VALUE
Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined.
After the selected settling time after this field is written with a 0 new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 × VREF.
The settling time of the DAC is 1 μs max, and the maximum 0 current is 700 μA.
The settling time of the DAC is 2.5 μs and the maximum current is 350 μA.
Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined.
5. Operation
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Bits 21:20 of the PINSEL1 register (Section 9–5.2 “Pin Function Select Register 1
(PINSEL1 – 0xE002 C004)” on page 180) control whether the DAC is enabled and
Sine wave generator
• Can generate arbitrary waveforms (e.g. sine waves) using the D/A converter.
• General strategy:
1. Create a table of sine wave values f: timeàvalue.
2. Build a loop counting from 0o to 359o to generate a complete sine wave.
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Representing sine values
• Sine waves have fractional values between 0 ~ 1:
sin (30) = 0.500000000000 sin (1) = 0.017452406437 sin (70) = 0.9396926207859
• Q-notation is a simple technique to represent fractions.
• Q-16 would use bits 15 – 0 to represent the fractional part and bits 31 – 16 for the
integer part.
Integer . Fraction 16 bits 16 bits
• Representing a number x using Q-notation:
1. Multiply x by 2m, where m is the Q-number.
2. Convert the resulting integer part into 32-bit binary.
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Representing sine values
• The integer part is never greater than 1 for our sine wave. So use Q-31, giving 31 bits to the fraction.
• sin(30) in Q-31:
= 0.500000000000 * 231 = 1,073,741,824
= 0x40000000
• sin(1) in Q-31:
= 0.017452406437 * 231
= 37,478,757 (ignoring the decimals) = 0x023BE164
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Sine wave generator
Only store values for 0 ~ 90 o, other angles are symmetries of these.
If register R1 has the angle, then:
• 90
r0, [r4, r1, LSL #2] ; look up table
sine_ret LDR
CMP r7, #180
RSBGT r0, r0, #0 ; negation for > 180
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Sine wave generator
• The sine routine outputs have to be scaled and shifted to fit the D/A converter’s input range (0 ~ 1023):
DACR = 512 ⇥ sin(R1) + 512 = 512⇥R0+512
• With the sine value in R0, update D/A converter output:
DACR EQU 0xE006C000 LDR r8, =DACR
MOV r0, r0, ASR #16 MOV r0, r0, LSL #9 MOV r0, r0, ASR #15 ADD r0, r0, #512 MOV r0, r0, LSL #6 STRH r0, [r8]
; Q-31 à Q-15
; multiply by 512
; remove fraction (Q-15 à int) ; 512*r0 + 512
; DACR[5:0] are reserved bits ; write to DACR
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Sine wave generator
PINSEL1 DACR STACKST
EQU 0xE002C004 EQU 0xE006C000 EQU 0x40000200 AREA SINEWAVE, CODE ENTRY
LDR sp, =STACKST
LDR r6, =PINSEL1
LDR r8, =DACR
LDR r7, [r6]
ORR r7, r7, #1:SHL:21 BIC r7, R7, #1:SHL:20 STR r7, [r6]
MOV r6, #360
RSB r1, r6, #360
MOV r0,r0,ASR#16 ;toD/A MOV r0, r0, LSL #9
MOV r0, r0, ASR #15
ADD r0, r0, #512
MOV r0, r0, LSL #6
STRH r0, [r8]
SUBS r6, r6, #1 BNE inloop
outloop inloop
; config D/A
sine STMFD sp!, {r4, r5, r7, lr} MOV r7, r1
LDR r5, =270
ADR r4, sine_data
CMP r1, #90
BLE sine_ret CMP r1, #180 RSBLE r1, r1,#180 BLE sine_ret CMP r1, r5 SUBLE r1, r1, #180 BLE sine_ret RSB r1, r1, #360
sine_ret LDR r0, [r4, r1, LSL #2] CMP r7, #180
RSBGT r0, r0, #0
LDMFD sp!, {r4, r5, r6, r7, pc} done B done
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Sine wave generator
DCD 0X00000000, 0X023BE164, 0X04779630,0X06B2F1D8 DCD 0X08EDC7B0, 0X0B27EB50, 0X0D613050, 0X0F996A30 DCD 0X11D06CA0, 0X14060B80,0X163A1A80, 0X186C6DE0 DCD 0X1A9CD9C0, 0X1CCB3220, 0X1EF74C00, 0X2120FB80 DCD 0X234815C0, 0X256C6F80, 0X278DDE80, 0X29AC3780 DCD 0X2BC750C0, 0X2DDF0040,0X2FF31BC0,0X32037A40 DCD 0X340FF240, 0X36185B00,0X381C8BC0, 0X3A1C5C80 DCD 0X3C17A500, 0X3E0E3DC0,0X40000000,0X41ECC480 DCD 0X4
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