DESN2000: Engineering Design & Professional Practice (EE&T)
Week 10 Exceptions and interrupts
School of Electrical Engineering & Telecommunications Graduate School of Biomedical Engineering
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Biomedical Microsystems Lab
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• Exceptions
• Interrupts and errors
• ARM processor modes
• Configuring the CPSR and SPSR
• Vector table & exception handler
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Exceptions
• Events that break the normal execution flow
• Benign Moving mouse, pressing keyboard, …
• Catastrophic Bus error, memory access error, …
• Categorized into two classes: 1. Interrupts
2. Error conditions
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Interrupts
• Hardware interrupts
Exceptions raised asynchronously by I/O devices so that they can be served by the CPU.
• Software interrupt
Exception raised within the application (i.e. by the CPU). It is a user defined synchronous exception.
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Hardware interrupts
• An efficient way for I/O devices to get the CPU’s attention.
• ARM has two hardware interrupt lines:
1. IRQ general use
2. FIQ high-priority and fast interrupts.
• I/O interrupts are asynchronous (can any time, not sync’ed to the CPU’s clock edges).
• Can occur in the middle of an executing instruction.
Hardware Interrupts
External lines for I/O Interrupt
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Error conditions
• These arise within the software (assembly program).
• Can occur for many reasons, and indeed, could occur more often than hardware interrupts.
• These include:
Undefined instruction
Floating point instructions emulated in software.
Data abort
Grabbing data in memory that do not physically exist (paging, swap file / virtual memory).
Attempts to write data in read-only memory region. Prefetch abort
Attempts to read an instruction from memory and something goes wrong.
Why the distinction between Data abort and Prefetch abort?
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Exceptions in ARM
ARM processors support these exceptions:
Undef. instruction Software Interrupt Prefetch Abort
Data Abort IRQ
Processor reset pin is asserted (signalling power-up).
The currently executing instruction is not recognized.
A user-defined synchronous interrupt instruction.
Attempts to execute an instruction that was not fetched due to illegal address.
Transfer instruction trying to load / store at an illegal address. Interrupt Request pin is asserted.
Fast Interrupt Request pin is asserted.
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ARM modes of operation
• • • • • • •
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Privileged mode
Non-privileged mode
10000 User Normal user code
10111 Abort 11011 Undef 11111 System
Handling fast interrupts
Handling standard interrupts
Handling software interrupts (SWIs) Handling memory faults
Handling undefined instruction
Running privileged operating system tasks
Program Status Register
Both CPSR and SPSR have the following format
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Do not modify / Read as Zero
• Bit [31:28] – conditional flags – N – Negative
– C – Carry over
User vs privileged modes
• User applications run in User Mode.
• Privileged modes used for
• Servicing hardware / software interrupts.
• Handling undefined instructions.
• Running privileged tasks.
• Privileged modes ⇒ User mode: always OK.
• User mode ⇒ Privileged modes: only via controlled mechanisms:
• Hardware interrupts
• Software interrupts
• Error conditions
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ARM modes and registers
ARM modes and Registers
• Except for System mode, every ARM mode has a set of dedicated registers that • Each mode has some set of registers that “swap in” and
“swaps in” and replaces the normal regs upon switching into the privileged mode.
replace normal registers
Usable in user mode Privileged mode only
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ARM modes and registers
The registers tell you a lot about the design intents of each mode.
Why does FIQ mode have more dedicated registers than the other modes? Why doesn’t System mode have any dedicated registers?
FIQ should be fast (Gbit Ethernet, HDDs, etc). ARM swap in/out (using dedicated circuits) lots of extra regs for you to use. System mode is intended to be used by OS tasks needing privileged accesses but doesn’t need extra registers.
ARM modes and Registers
• Each mode has some set of registers that “swap in” and replace normal registers
Usable in user mode Privileged mode only
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ARM hardware interrupts
Program Status Register
• The CPSR affects how the processor handles hardware interrupts.
• Both CPSR and SPSR have the following format CPSR
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Do not modify / Read as Zero
• Bit [31:28] – conditional flags
– N – Negative
Interrupt masks
• Setting the mask bit high disables the corresponding interrupt:
– C – Carry over Normal interrupt (IRQ) mask bit
– V – Overflow Fast interrupt (FIQ) mask bit
• Bit [4:0] – Current Mode
• I – IRQ ( disable IRQ if it is set)
• F – FIQ ( disable FIQ if it is set)
• T – set to 0 for ARM code ( otherwise THUMB code)
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Configuring the C/SPSR
Modify the CPSR (current program status register) to change:
Program Status Register
Conditional flags
Disable / enable interrupts (IRQ, FIQ)
• Both CPSR and SPSR have the following format Mode
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Do not modify / Read as Zero
• Bit [31:28] – conditional flags – N – Negative
– C – Carry over
Up to two PSRs are visible at any time:
SPSR (saved program status register, the previous mode’s PSR).
– V – Overflow
User and System modes do not have SPSR.
• Bit [4:0] – Current Mode
• I – IRQ ( disable IRQ if it is set)
In User mode: only the condition flags can be edited, all other bits are protected.
• F – FIQ ( disable FIQ if it is set)
In the privileged modes: the entire CPSR can be edited.
• T – set to 0 for ARM code ( otherwise THUMB code)
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Configuring the C/SPSR
Copying a general register into a PSR:
MSR CPSR, R0
MSR SPSR, R0
MSR CPSR_f, R0 MSR CPSR_f, #1<<28
; R0 into CPSR
; R0 into SPSR
; flag bits of R0 into CPSR
; flag bits (immediate) into CPSR
Weird _f notation: will discuss shortly
Copying the PSR into a general register:
MRS R0, CPSR ; CPSR into R0 MRS R0, SPSR ; SPSR into R0
Can only edit the SPSR of the current mode.
Example: if in IRQ mode, you cannot edit the SPSR of FIQ.
Switch to FIQ mode first, if you want to change FIQ’s SPSR (SPSR_fiq).
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Configuring the C/SPSR
• Two ways to modify the CPSR / SPSR.
• Method 1: read-write-modify strategy.
1. Transfer PSR to general register using MRS
2. Modify relevant bits
3. Transfer updated value to PSR register using MSR
• Example: changing to Supervisor mode
MRS a1, CPSR
BIC a1, a1, #0x1F ; clear mode bits ORR a1, a1, #0x13 ; set SVC mode MSR CPSR, a1
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Configuring the C/SPSR
Method 2: using the bit-field flags.
The CPSR / SPSR register is divided into 4 sections:
Combine flags for compound effects. Example:
control bits, [7-0]: including I/F disable, Thumb mode, processor mode. extension bits, [15-8]
status bits, [23-16]
flag bits, [31-24]: including NZCV flags
MSR CPSR_c, #0x9B ; switch to Undef mode, mask IRQ MSR CPSR_c, #0x93 ; switch to SVC mode, mask IRQ
Program Status Register
MSR CPSR_f, #0x93 ; clear flag bits, ctrl bits ignored MSR CPSR_cf, #0x93 ; clear flag bits and switch to SVC mode
• Both CPSR and SPSR have the following format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
N Z C V Do not modify / Read as Zero
7 6 5 4 3 2 1 0
I F T M M M M M
10011011 10010011
• Bit [31:28] - conditional flags #0x93:0 0 0 0 ....
#0x9B:0 0 0 0 ....
– N - Negative © 2022 UNSW Sydney – Z - Zero
– C - Carry over
Binary format for MRS
CPSR and SPSR Transfer Instructions
Configuring the C/SPSR
The MRS instruction moves the value of the CPSR or the SPSR of the current mode into a general-purpose register
MRS moves the CPSR or the SPSR of the current mode into a general-purpose
register: syntax: MRS{cond MRS{cond
Binary format:
00 000000 0000
ForCPSR,R=0
For CPSR, R = 0. For SPSR, R = 1.
ForSPSR,R=1
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} Rd, CPSR
} Rd, SPSR
Configuring the C/SPSR
CPSR and SPSR Transfer Instructions
The MSR instruction transfers the value of the general-
MpSu PrSpRosoer trheegSisPtSeRr voafltuhee icnutrorethnet CPSR / SPSR of the current
Binary format (immediate):
mmodoed.e. This is used to update the value of the condition code flags, interrupt enables, or the processor mode.
The MSR also moves the value of the 32-bit immediate to the CPSR or the SPSR.
Useful for changing condition flags, interrupt masks or processor mode.
MSR{conds}yntCaPx:SR<_fields>, #32bit_immediate MSR {
MSR{cond} CPSR<_fields>, Rm
MSR {
MSR{cond} SPSR<_fields>, #32bit_immediate
MSR {
MSR{cond} SPSR<_fields>, Rm
MSR {
Binary formats for MSR ( immediate)
8_bit_imme
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Configuring the C/SPSR • Binary format for MSR ( register)
Binary format for MSR (register):
CPSR and SPSR Transfer Instructions
00 00000 0
s (bit 18)
Modifies only the status bits ([23:16]) of CPSR or SPSR
f (bit 19)
Modifies only the flags bits ([31:24]) of CPSR or SPSR
• R==00fofroCrCPSPRSR • R = 1 for SPSR
• R=1forSPSR
• Condition code for
sets bit[16]- control field mask bit – CPSR or SPSR [7:0]
c (bit 16)
sets bit [17]- extension field mask bit –CPSR or SPSR [15:8]
Modifies only the control bits ([7:0]) of CPSR or SPSR
sets bit [18]- the status field mask bit – CPSR or SPSR [23:16] sets bit [19] – the flags field mask bit – CPSR or SPSR [31:24]
x (bit 17)
Modifies only the extension bits ([15:8]) of CPSR or SPSR
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Mode switching
Hardware does the register swap (fast, 1-clk cycle).
Usable Re giste rs
Hidden Re giste rs
Hidden Re giste rs
Usable Re giste rs
Return address calculated and saved
Fresh set of R8 … R14 becomes available
… mode bits in CPSR updated.
… SPSR_fiq is USER mode’s CSPR.
0x0000001C
The banked registers replace the ordinary ones during the exception. The ordinary ones cannot be seen directly.
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Mode switching
Questions: while in FIQ mode:
What does the mode bits ([5:0]) of CPSR indicates? What about those of the SPSR_fiq?
CPSR[5:0] indicate “FIQ”
SPSR_fiq[5:0] would indicate the prev.
state before the FIQ occurred… so it’s “User”.
Cannot access R0 ~ R7 of USER mode.
Can you access registers R0 ~ R7 of USER mode?
Usable Re giste rs
Hidden Re giste rs
Hidden Re giste rs
Usable Re giste rs
Return address calculated and saved
0x0000001C
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Mode switching: to exception handler
• When exception occurs, ARM processor takes the following steps:
Save current (USER mode) CPSR in SPSR_
Some USER mode registers become invisible, replaced by banked registers.
Update CPSR:
Switch to ARM state if it was in THUMB state.
Setting the mode bits in CPSR.
IRQ automatically disabled (CPSR[7] = 1) on entry to all exceptions.
FIQ automatically disabled (CPSR[6] = 1) on entry to RESET and FIQ exceptions.
Copy address of next instruction (return address) into LR_
Exception handler – a piece of code that deals with the exception condition.
• The processor does the above for you.
• We use the names “LR_fiq”, “R13_fiq”, etc… But in practice you still write “LR”, “R13”, etc., respectively, in your assembly code to refer to these regs while in FIQ mode.
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Mode switching: from exception handler
• To return to the USER mode, the programmer must:
1. Move the return address (in LR_
2. Restore original (before the exception occurred) CPSR.
• Must be done simultaneously, using the ‘S’ variant:
MOVS PC, LR ; restore PC and CPSR
• Similarly achieved using ^ qualifier with LDMFD:
LDMFD SP!, {R0-R1, PC}^ ; restore regs, PC and CPSR
• On executing above instruction:
1. Processor goes into USER mode.
2. Banked registers are hidden, USER mode registers become available.
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The vector table
• Beside SYSTEM exception,TtheereVisecatodredTicabteled block of code, called an exception
handler, used by the proces•soThretPorohgaranmdcloeuntthereweillxbceelopatdieodnw.ith one of the following vector address depending on the particular
• The vector table has an entry for every exception type:
• In the vector address, ARM uses actual instructions, often a change-of flow instruction types.
• When an exception occurs, the PC is automatically loaded with the matching exception handler’s address from the vector table.
• Besides FIQ, each entry is 32 bits… enough for one instruction.
• 0x00 RESET is where PC starts upon system power-up.
exception occurred
0x1C 0x18 0x14
(Reserved)
Data Abort
Prefetch Abort
Software interrupt
Undefined instruction
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The vector table
The vector table contains change-of-flow instruction(s):
Use B Use MOV Use LDR
Jump to exception handler that is within 32 MB range.
Update PC with a new address representable by a 8-bit value with rotation.
Data can be stored in instruction memory and accessed using an PC-offset (assisted by literal pools), e.g. LDR PC, [PC, offset]
The Vector Table
0xFF Servicing routines can be placed directly in the vector table. 0x30
FIQ (last entry) does not have the 32-bit space limit
Undefi branch
SWI exc approp
FFFFFF 080000
000000 00000
Undef handler
SWI handler
IRQ handler
0x14 0x10 0x0C 0x08 0x04 0x00
FIQ handler
B IRQ_handler
(Reserved)
Data Abort
Prefetch Abort
MOV PC,#0x30000000
LDR PC, [PC,#0xFF0]
Allows FIQ interrupts to be serviced quickly… no branching, no pipeline stalling.
0x30 >32MB 0x20
IRQ ha 0 instruc
Literal undef h
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The vector table
The Vector Table
0xFFFFFFFF
0x30080000
0x30000000 >32MB 0x2000000
0x1000 < 4KB
0x14 0x10 0x0C 0x08 0x04 0x00
Undefined handler outside 32MB branch instruction range
SWI exception handler placed appropriate address boundary
IRQ handler within 32MB branch instruction range
Literal pool containing address o undef handler
FIQ handler follows vector table
Undef handler
SWI handler
IRQ handler
FIQ handler
B IRQ_handler
(Reserved)
Data Abort
Prefetch Abort
MOV PC,#0x30000000
LDR PC, [PC,#0xFF0]
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Writing exception handlers
• SUMMARY: when exception (other than SYSTEM) occurs:
1. Saves USER mode CPSR to SPSR_
2. Modifies the appropriate bits of the CPSR
3. Puts the return address in LR_
4. Loads the PC with the appropriate handler address from the vector table
• All of above are done by the processor.
• Following mode change, the exception handler has access to its own SP, LR and CPSR
(except SYSTEM mode).
ARM modes and Registers
• Each mode has some set of registers that “swap in” and replace normal registers
• Your task is to write an appropriate exception handler:
1. Deal with the exception
2. Cleanly resume original execution path in User mode.
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Writing exception handlers
The hardware swaps in banked registers (e.g. R13 / SP and R14 / LR). Other registers will need to be saved if you use them, like function calls:
STMFD SP!, {R0-R12, LR} ; save all non-banked registers and return addr
Note the SP above is the privileged mode’s stack pointer (why?), which can be different from the USER mode’s SP.
After the exception we resume the original instruction stream:
LDMFD SP!, {R0-R12, PC}^ ; restore non-banked regs and ret addr
The above is an atomic operation (done in a single step).
Imagine what happens if another exception is allowed to interrupt the processor while
the above instruction takes place.
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Exception Priorities
• When multiple exceptions occur at the same time, the processor should know which one to attend first.
Exception priorities
• Suppose A/D converter has asserted IRQ line and at the same time the processor tries to access a memory location that is undefined
• When multiple exceptions occur simultaneously, higher priority exceptions are handled
while another high-priority interrupt tries to tell the processor first. that we are about to lose power in two minutes
Exception priorities
Handler usually branches straight to main routine
Data Abort
Can sometimes be helped with MMU
Current instruction completes, then the interrupt is acknowledged
Current instruction completes, then interrupt is acknowledged.
Prefetch Abort
Can sometimes be helped with hardware (MMU)
Execution of the instruction causes the exception
Undefined instruction
SWI and Undef are actually exclusive, so they have the same priority
• Q: Suppose A/D converter has asserted IRQ line and the processor tries to access a
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