Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C (Dr. )
Chapter 4 ARM Arithmetic and Logic Instructions
ECE3375B: Microprocessors and Microcomputers Electrical and Computer Engineering Western University
Dr. Leod (Section 1, Dr. (Section 2,
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Arithmetic and Logic Instructions
LSL (logic shift left), LSR (logic shift right), ASR (arithmetic shift right), ROR (rotate right), RRX (rotate right with extend)
AND (bitwise and), ORR (bitwise or), EOR (bitwise exclusive or), ORN (bitwise or not), MVN (move not)
Bit set/clear
BFC (bit field clear), BFI (bit field insert), BIC (bit clear), CLZ (count leading zeroes)
Bit/byte reordering
RBIT (reverse bit order in a word), REV (reverse byte order in a word), REV16 (reverse byte order in each half-word independently), REVSH (reverse byte order in each half-
word independently)
Addition
ADD, ADC (add with carry)
Subtraction
SUB, RSB (reverse subtract), SBC (subtract with carry)
Multiplication
MUL (multiply), MLA (multiply-accumulate), MLS (multiply-subtract), SMULL (signed long multiply-accumulate), SMLAL (signed long multiply-accumulate), UMULL (unsigned
long multiply-subtract), UMLAL (unsigned long multiply-subtract) Division
SDIV (signed), UDIV (unsigned) Sign extension
SXTB (signed), SXTH, UXTB, UXTH Bit field extract
SBFX (signed), UBFX (unsigned) Syntax
2 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Example: Add
Unified Assembler Language (UAL) Syntax
ADD r1, r2, r3
ADD r1, r2, #4
Traditional Thumb Syntax ADD r1, r3
ADD r1, #15
; r1 = r2 + r3
; r1 = r2 + 4
; r1 = r1 + r3
; r1 = r1 + 15
3 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Commonly Used Arithmetic Operations
ADD {Rd,} Rn, Op2
Add.Rd Rn+Op2
ADC {Rd,} Rn, Op2
Add with carry. Rd Rn + Op2 + Carry
SUB {Rd,} Rn, Op2
Subtract. Rd Rn – Op2
SBC {Rd,} Rn, Op2
Subtract with carry. Rd Rn – Op2 + Carry – 1
RSB {Rd,} Rn, Op2
Reverse subtract. Rd Op2 – Rn
MUL {Rd,} Rn, Rm
Multiply. Rd (Rn × Rm)[31:0]
MLA Rd, Rn, Rm, Ra
Multiply with accumulate.
Rd (Ra + (Rn × Rm))[31:0]
MLS Rd, Rn, Rm, Ra
Multiply and subtract, Rd (Ra – (Rn × Rm))[31:0]
SDIV {Rd,} Rn, Rm
Signed divide. Rd Rn / Rm
UDIV {Rd,} Rn, Rm
Unsigned divide. Rd Rn / Rm
4 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Example: Short Multiplication and Division ; MUL: Signed multiply
MUL r6,r4,r2 ;r6=LSB32(r4×r2) ; UMUL: Unsigned multiply
UMUL r6, r4, r2 ; r6 = LSB32( r4 × r2 ) ; MLA: Multiply with accumulation
MLA r6,r4,r1,r0 ;r6=LSB32(r4×r1)+r0 ; MLS: Multiply with subtract
MLS r6,r4,r1,r0 ;r6=LSB32(r4×r1)-r0
LSB32: Least significant 32 bits
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A.
Example: Long Multiplication
UMULL RdLo, RdHi, Rn, Rm
Unsigned long multiply
RdHi,RdLo unsigned(Rn × Rm)
SMULL RdLo, RdHi, Rn, Rm
Signed long multiply
RdHi,RdLo signed(Rn × Rm)
UMLAL RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
RdHi,RdLo unsigned(RdHi,RdLo + Rn × Rm)
SMLAL RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
RdHi,RdLo signed(RdHi,RdLo + Rn × Rm)
The result has 64 bits, placed in two registers.
UMULLr3,r4,r0,r1 SMULLr3,r4,r0,r1 UMLALr3,r4,r0,r1 SMLALr3,r4,r0,r1
;r4:r3=r0 r1,r4=MSBbits,r3=LSBbits ;r4:r3=r0 r1
;r4:r3=r4:r3+r0 r1
;r4:r3=r4:r3+r0 r1
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
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Bitwise Logic
AND {Rd,} Rn, Op2
Bitwise logic AND
Rd Rn & operand2
ORR {Rd,} Rn, Op2
Bitwise logic OR
Rd Rn | operand2
EOR {Rd,} Rn, Op2
Bitwise logic exclusive OR
Rd Rn ^ operand2
ORN {Rd,} Rn, Op2
Bitwise logic NOT OR
Rd Rn | (NOT operand2)
BIC {Rd,} Rn, Op2
Rd Rn & NOT operand2
BFC Rd, #lsb, #width
Bit field clear
Rd[(width+lsb–1):lsb] 0
BFI Rd, Rn, #lsb, #width
Bit field insert
Rd[(width+lsb–1):lsb] Rn[(width-1):0]
MVN Rd, Op2
Move NOT, logically negate all bits
Rd 0xFFFFFFFF EOR Op2
7 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Example: AND r2, r0, r1
r0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 r1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
10000000000000010000000000000001
Bit-wise Logic AND
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
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Example: ORR r2, r0, r1
r01 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 r11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
r21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit-wise Logic OR
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
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Example: BIC r2, r0, r1 Bit Clear
r2 = r0 & NOT r1
r1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 NOT r1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
r01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOT r1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
11111111111111111111111111110000
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
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Example: BFC and BFI
Bit Field Clear (BFC) and Bit Field Insert (BFI).
BFC Rd, #lsb, #width
BFI Rd, Rn, #lsb, #width
Examples:
BFC R4, #8, #12
; Clear bit 8 to bit 19 (a total of 12 bits) of R4
BFI R9, R2, #8, #12
; Replace bit 8 to bit 19 (12 bits) of R9
; with bit 0 to bit 11 from R2.
11 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Updating NZCV flags in PSR
Flags not changed
ADD SUB MUL UDIV AND ORR LSL MOV
Flags updated
ADDS SUBS MULS UDIVS ANDS ORRS LSLS MOVS
⟶ ⟶ ⟶ ⟶ ⟶ ⟶ ⟶ ⟶
Most instructions update NZCV flags only if S suffix is present
Some instructions update NZCV flags even if no S is specified.
• CMP: Compare, like SUBS but without destination register
• CMN: Compare Negative, like ADDS but without destination register
• TST: Test, like ANDS but without destination register
• TEQ: Test equivalence, like EORS but without destination register
12 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
CMP r1, r2 vs SUBS r0, r1, r2
ADD vs ADDS
ADD r0, r1, r2 ; r0 = r1 + r2, NZCV flags unchanged
ADDS r0, r1, r2 ; r0 = r1 + r2, NZCV flags updated ADD does not update flags
ADDS updates flags
CPSR.N = bit 31 of result
CPSR.Z = IsZero(result)
CPSR.C = carry, assuming r1 and r2 representing unsigned integers CPSR.V = overflow, assuming r1 and r2 representing signed integers
13 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Suffix S: Update Flags
LDR r0, =0xFFFFFFFF LDR r1, =0x00000001 ADDS r3, r0, r1
0xFFFFFFFF r0
0x00000001 r1
0x00000000 sum
N (Negative) = 0 Z (Zero) = 1
C (Carry) = 1
V (oVerflow) = 0
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Reverse Order
RBIT Rd, Rn
Reverse bit order in a word
for(i=0;i<32;i++) Rd[i] RN[31–i]
REV Rd, Rn
Reverse byte order in a word
Rd[31:24] Rn[7:0], Rd[23:16] Rn[15:8], Rd[15:8] Rn[23:16], Rd[7:0] Rn[31:24]
REV16 Rd, Rn
Reverse byte order in each half-word Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:24] Rn[23:16], Rd[23:16] Rn[31:24]
REVSH Rd, Rn
Reverse byte order in bottom half-word and sign extend
Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:16] Rn[7] & 0xFFFF
RBIT Rd, Rn Rn
Rd Example:
LDR r0, =0x12345678 ; r0 = 0x12345678
RBIT r1, r0 ; Reverse bits, r1 = 0x1E6A2C48
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Reverse Order
RBIT Rd, Rn
Reverse bit order in a word
for(i=0;i<32;i++) Rd[i] RN[31–i]
REV Rd, Rn
Reverse byte order in a word
Rd[31:24] Rn[7:0], Rd[23:16] Rn[15:8], Rd[15:8] Rn[23:16], Rd[7:0] Rn[31:24]
REV16 Rd, Rn
Reverse byte order in each half-word Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:24] Rn[23:16], Rd[23:16] Rn[31:24]
REVSH Rd, Rn
Reverse byte order in bottom half-word and sign extend
Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:16] Rn[7] & 0xFFFF
REV Rd, Rn Rn
Rd Example:
LDR R0, =0x12345678 REV R1, R0
; R0 = 0x12345678 ; R1 = 0x78563412
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Reverse Order
RBIT Rd, Rn
Reverse bit order in a word
for(i=0;i<32;i++) Rd[i] RN[31–i]
REV Rd, Rn
Reverse byte order in a word
Rd[31:24] Rn[7:0], Rd[23:16] Rn[15:8], Rd[15:8] Rn[23:16], Rd[7:0] Rn[31:24]
REV16 Rd, Rn
Reverse byte order in each half-word Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:24] Rn[23:16], Rd[23:16] Rn[31:24]
REVSH Rd, Rn
Reverse byte order in bottom half-word and sign extend
Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:16] Rn[7] & 0xFFFF
REV16 Rd, Rn Rn
Rd Example:
LDR R0, =0x12345678 REV16 R2, R0
; R0 = 0x12345678 ; R2 = 0x34127856
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Reverse Order
RBIT Rd, Rn
Reverse bit order in a word
for(i=0;i<32;i++) Rd[i] RN[31–i]
REV Rd, Rn
Reverse byte order in a word
Rd[31:24] Rn[7:0], Rd[23:16] Rn[15:8], Rd[15:8] Rn[23:16], Rd[7:0] Rn[31:24]
REV16 Rd, Rn
Reverse byte order in each half-word Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:24] Rn[23:16], Rd[23:16] Rn[31:24]
REVSH Rd, Rn
Reverse byte order in bottom half-word and sign extend
Rd[15:8] Rn[7:0], Rd[7:0] Rn[15:8], Rd[31:16] Rn[7] & 0xFFFF
REVSH Rd, Rn Rn
Rd Example:
LDR R0, =0x33448899 REVSH R1, R0
; R0 = 0x33448899 ; R0 = 0xFFFF9988
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Sign and Zero Extension
int8_t a = -1; // a signed 8-bit integer, a = 0xFF
int16_t b = -2; int32_t c;
c = a; c = b;
// a signed 16-bit integer, b = 0xFFFE // a signed 32-bit integer
// sign extension required, c = 0xFFFFFFFF // sign extension required, c = 0xFFFFFFFE
19 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Sign and Zero Extension
SXTB {Rd,} Rm {,ROR #n}
Sign extend a byte
Rd[31:0] Sign Extend((Rm ROR (8 × n))[7:0])
SXTH {Rd,} Rm {,ROR #n}
Sign extend a half-word
Rd[31:0] Sign Extend((Rm ROR (8 × n))[15:0])
UXTB {Rd,} Rm {,ROR #n}
Zero extend a byte
Rd[31:0] Zero Extend((Rm ROR (8 × n))[7:0])
UXTH {Rd,} Rm {,ROR #n}
Zero extend a half-word
Rd[31:0] Zero Extend((Rm ROR (8 × n))[15:0])
LDR R0, =0x55AA8765
SXTB R1, R0 SXTH R1, R0 UXTB R1, R0 UXTH R1, R0
; R1 = 0x00000065 ; R1 = 0xFFFF8765 ; R1 = 0x00000065 ; R1 = 0x00008765
20 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Move Data between Registers
Rd operand2
Rd NOT operand2
MRS Rd, spec_reg
Move from special register to general register
MSR spec_reg, Rm
Move from general register to special register
MOV r4, r5 ; Copy r5 to r4
MVN r4, r5 ; r4 = bitwise logical NOT of r5 MOVr1,r2,LSL#3 ;r1=r2<<3
MOV r0, PC ; Copy PC (r15) to r0
MOV r1, SP ; Copy SP (r14) to r1
21 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Move Immediate Number to Register
MOVW Rd, #imm16
Move Wide, Rd #imm16
MOVT Rd, #imm16
Move Top, Rd #imm16 << 16
MOV Rd, #const
Move, Rd const
Example: Load a 32-bit number into a register
• MOVW will zero the upper halfword
• MOVTwon’tzerothelowerhalfword
Order does matter!
MOVW r0, #0x4321 ; r0 = 0x00004321
MOVT r0, #0x8765 ; r0 = 0x87654321
MOVT r0, #0x8765 ; r0 = 0x8765xxxx MOVW r0, #0x4321 ; r0 = 0x00004321
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Flexible 2nd Source Operand
LSL,LSR,ASR,
ADD r0, r1, Operand2
Add r0, r1, r2 ; r0 = r1 + r2
Add r0, r1, #1 ; r0 = r1 + 1
Add r0, r1, r2 LSL #2 ; r0 = r1 + r2 << 2
23 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Use Barrel shifter to speed up multiplication and division Shifting left 1 bit multiplies a number by 2
Examples:
r1 = 9 × r0
ADD r1, r0, r0, LSL #3 <=> MOV r2, #9 ; r2 = 9
r0 + r0 << 3 = r0 + 8 × r0
MUL r1, r0, r2 ; r1 = r0 * 9
ADD r1, r0, r0, LSR #3
; r1 = r0 + r0 >> 3 = r0 + r0/8 (unsigned)
ADD r1, r0, r0, ASR #3
; r1 = r0 + r0 >> 3 = r0 + r0/8 (signed)
24 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Barrel Shifter
Logical Shift Left (LSL)
Arithmetic Shift Right (ASR)
Logical Shift Right (LSR)
Rotate Right (ROR)
Rotate Right Extended (RRX)
Why is there rotate right but no rotate left?
Rotate left can be replaced by a rotate right with a different rotate offset.
25 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Updating APSR Flags
If “S” is present, the instruction update flags. Otherwise, the flags are not updated. Let R be the final 32-bit result
IsZeroBit(R)
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Quiz 1: ANDS
N=?, Z=?, C=?, V=?
LDR r0, =0xFFFFFF00 LDR r1, =0x00000001 ANDS r2, r1, r0, LSL #1
27 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Quiz 1: ANDS
LDR r0, =0xFFFFFF00 LDR r1, =0x00000001 ANDS r2, r1, r0, LSL #1
Update carry flag
Z = 1, C = 1, V = 0
AND{S} {
if ConditionPassed() then
EncodingSpecificOperations();
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C); result = R[n] AND shifted;
R[d] = result;
if setflags then
APSR.N = result<31>; APSR.Z = IsZeroBit(result); APSR.C = carry;
// APSR.V unchanged
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
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ARMv7-M Architecture Reference Manual
Quiz 2: ADDS
N=?, Z=?, C=?, V=?
LDR r0, =0xFFFFFF00 LDR r1, =0x00000001 ADDS r2, r1, r0, LSL #1
29 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Quiz 2: ADDS
LDR r0, =0xFFFFFF00 LDR r1, =0x00000001 ADDS r2, r1, r0, LSL #1
N = 1, Z = 0, C = 0, V = 0 ADD{S} {
Does NOT update carry flag
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], shifted, ‘0’); if d == 15 then
ALUWritePC(result); // setflags is always FALSE here else
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result); APSR.C = carry;
APSR.V = overflow;
ARMv7-M Architecture Reference Manual
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Implementation of Barrel Shifter
Can we shift or shift or rotate n bits within a single clock cycle?
31 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Implementation of Barrel Shifter
Typically, Barrel shifters are implemented as a cascade of parallel 2-to-1 multiplexers.
Example four-bit Barrel shifter that performs rotate right
32 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
D0 D3 D2 D1
D2 D1 D0 D3
Implementation of Barrel Shifter
Example: S1S0 = 00
Example four-bit Barrel shifter that performs rotate right
33 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
D0 D3 D2 D1
D2 D1 D0 D3
Implementation of Barrel Shifter
Example: S1S0 = 01
Example four-bit Barrel shifter that performs rotate right
34 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
D0 D3 D2 D1
D2 D1 D0 D3
Implementation of Barrel Shifter
Example: S1S0 = 10
Example four-bit Barrel shifter that performs rotate right
35 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
D0 D3 D2 D1
D2 D1 D0 D3
Implementation of Barrel Shifter
Example: S1S0 = 11
Example four-bit Barrel shifter that performs rotate right
36 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
D0 D3 D2 D1
D2 D1 D0 D3
Set a Bit in C
a |= (1 << k)
a = a | (1 << k)
Example: k = 5
a 1 << k a | (1 << k)
The other bits should not be affected.
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4
ECE 3375b (A. Reyhani)
Set a Bit in Assembly
a |= (1 << 5)
Solution 1:
MOVS r4, #1 LSLS r4, r4, #5 ORRS r0, r0, r4
; r4 = 1<<5
; r0 = r0 | 1<<5
Solution 2:
MOVS r4, #1 ; r4 = 1
ORRS r0, r0, r4, LSL #5 ; r0 = r0 | 1<<5
38 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 4 ECE 3375b (A. Reyhani)
Clear a Bit in C
Example: k = 5
a &= ~(1<