CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
Block Design using Latches
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We can create our own D Flip Flop from D Latches. This kind of technique is called Master-Slave, it summarizes the relationship between the 2 latches used.
Start off by adding a blank block diagram schematic to your project. Create 2 of the built-in symbol DLatch, a not gate, 4 inputs, and 1 output. You can find the DLatch in the symbol menu like we did last time.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
Connect the pieces as such, notice that the CLK is inverted for the first latch but not the second one. This yields a positive-edge triggered response, by inverting the second latch¡¯s clock signal instead we would have a negative-triggered one.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
Create VHDL from this design.
As usual we cannot change the file name, and this will lead to a compile error later since the block diagram has the same name. I recommend to use our usual trick of manually renaming the VHDL file then opening it and replacing all instances where the filename is still the old one.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
First, find the folder of your project and manually rename the file.
Then, open the file in Quartus (make sure Add file to current project is ticked). Find the feature Edit > Replace… and Replace All instances where the name is wrong.
You can compile the file but we will do it in ModelSim.
ModelSim Simulation
Follow the usual steps in ModelSim (project folder select, add existing file).
First, if the project is not set up yet, create a new one and for the Project Location, you have to Browse to the folder where the VHDL file we created is.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
Then add that file to the project with Add Existing File
Start the simulation and select the file.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
As always drag the non-Internal signals to the wave.
CSC 343 Spring 2022 Laboratory Exercise Tutorial: Design Entry Specified:
D FlipFlop Master-Slave from D Latches, with ModelSim Simulation
Instructor: Professor Izidor Gertner
The visible behavior of this design is the same as a regular D Flip Flop.
I kept PRN and CLRN forced at 1 so they don¡¯t interfere. The CLK I had at an oscillation period of 75, while D was at 200. To summarize, at the moment the CLK is moving from 0 to 1, the value of D is sent through the circuit to the output Q.
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