School of Electronics and Mechanical Engineering Technology
DGS355 – Digital Systems Lab 21 – JK and T Flip-Flops
Name: _____________________________________________ Section: _______ Note: This handout is an adaptation of Lab 21 of Dueck, Robert K., Digital Design with CPLD
Applications and VHDL, 2/e for the Online Delivery. Objectives
• Use the Quartus II Block Editor to create a circuit for an asynchronous binary counter, using JK or T flip-flops.
• Create a simulation that verifies the operation of the counter made with JK flip-flops. Book Reference
• Chapter 8: Introduction to Sequential Logic.
Part 1 – Experimental Notes
The JK flip-flop can operate in a number of synchronous modes, which include no change (JK = 00), reset (JK = 01), set (JK = 10), and toggle (JK = 11). One of the more useful modes of the JK flipflop is the toggle mode, which allows the device to be used as an element in a binary counter. If several flip-flops are all configured to toggle, they can be arranged so that the Q output on one flip-flop clocks the next one. If the flip-flops are negative-edge triggered, the effect of this arrangement is to generate a binary count sequence.
The T (“toggle”) flip-flop can fulfill the same function as a JK flip-flops. It has a synchronous input called T, which switches the flip-flop between a toggle mode (when T = 1) and a no change mode (when T = 0). If a T flip-flop is configured to toggle on each clock pulse, it can be directly substituted into a circuit that uses JK flip-flops for the same function.
In addition to the synchronous JK and T inputs, both types of flip-flops have asynchronous clear and preset functions. These functions act immediately when made LOW to set the Q output of the flip-flop to 0 (when preset = 0) or to 1 (when clear = 0). The primary use of these functions is to set the flip-flop to a known initial state, from which point functions are usually determined by the state of the synchronous inputs and the clock.
Part 2 – Procedure
Asynchronous Counter (JK Flip-Flops): Design Entry and Simulation
1. Openanewproject.
2. Create a 4-bit asynchronous counter in the Quartus II Block Editor, as shown in Figure 1, and save it as asynch_ctr_JK.bdf.
3. Writeasetofsimulationcriteriatoverifythecorrectnessofthecircuitdesign.Usethese criteria to make a Quartus II simulation.
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School of Electronics and Mechanical Engineering Technology
Simulation Criteria: ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________
Figure 1: 4-Bit Asynchronous Binary Counter.
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