School of Electronics and Mechanical Engineering Technology
DGS355 – Digital Systems
Lab 23 – Binary and BCD Counters with Control Inputs (VHDL)
Name: _____________________________________________ Section: _______ Note: This handout is an adaptation of Lab 23 of Dueck, Robert K., Digital Design with CPLD
Applications and VHDL, 2/e for the Online Delivery. Objectives
• Enter the design for a presettable binary counter in VHDL
• Enter the design for a presettable BCD counter in VHDL. Book Reference
• Chapter 9: Counters and Shift Registers.
Part 1 – Experimental Notes
Programming Behaviorally-Designed Binary and BCD Counters in VHDL
Counters can be designed in VHDL with functions such as count enable, directional control, synchronous or asynchronous clear, and synchronous or asynchronous load. These functions can be implemented by assigning a value to a count variable or directly updating an output port, depending on conditions specified in one or more IF statements within a PROCESS. For details, refer to Section 9.6 in Digital Design with CPLD Applications and VHDL, 2/e.
A 2-digit BCD (binary coded decimal) counter advances in decimal from 00 to 99 (0000 0000 to 1001 1001) and then rolls over to 00. Values representing hex numbers from A through F are not valid in this code.
For a 2-digit BCD counter, we use an 8-bit output, but divide the range into two groups of four bits: one group for the one’s digit and one group for the ten’s digit. This type of counter can be implemented in a similar way to the behaviorally-designed binary counter, but requires a more complex algorithm for increasing the count. Rather than simply incrementing a single count variable with a range of 0 to 255, we must have two variables, each with a range of 0 to 9. When the one’s digit is at 9, it must be set to 0 on the next count and the ten’s digit incremented. If both digits are at 9, both must be set to 0 on the next count. After each clock pulse, the two BCD variables are assigned to output pins, where they can be displayed directly as binary numbers or decoded to display a numerical output.
Part 2 – Procedure Presettable Binary Counter
1. Openanewproject.
2. Write a VHDL file for an 8-bit counter with active-LOW asynchronous clear, active-HIGH synchronous load, active-HIGH count enable, and a directional input that makes the circuit count up when DIRECTION = 1 and down when DIRECTION = 0. Save the file as ct8bit.vhd. Compile the project.
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3. Writeasetofsimulationcriteriathatverifiestheoperationofthecounter.Thesimulationmust contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable. Use the simulation criteria to make a simulation in Quartus II.
Simulation Criteria: ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________
4. Createatestcircuitforthe8-bitcounter,asshowninFigure1.Savethefileasct8bit_r.bdf. Compile the project. Create a simulation for this testing circuit accounting for the following checklist:
a. Binary up count (include a rollover from FF to 00)
b. Binary down count (include a rollover from 00 to FF)
c. Clear
d. Load
e. Countenable
f. Check precedence of function: clear overrides load, which overrides enable
BCD Counter
1. Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable. Save the file as ct2bcd.vhd.
The counter must count up from 00 to 09, then 10 to 19, and so on until it reaches 99. At that point the counter must roll over to 00. The parallel inputs should load any value from 0 to 9 on each digit. If a parallel binary input falls outside the valid BCD range (1010 to 1111) for either digit, the circuit should set that digit to 9 when the parallel input is loaded.
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Figure 1: Test Circuit for an 8-Bit Presettable Counter.
2. Compiletheproject.Writeasetofsimulationcriteriaanduseittocreateasimulationforthe BCD counter. All functions must be tested, including whether the load function is synchronous and how parallel inputs greater than 9 are handled on each digit. Use the simulation criteria to make a simulation in Quartus II.
3. SimulationCriteria:
___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________
4. Create a test circuit for the 2-digit BCD counter, as shown in Figure 2 Save the file as ct2bcd_r.bdf.
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5. Create a simulation for this testing circuit accounting for the following checklist:
a. BCD count (include a rollover from 00 to 19 and from 99 to 00)
b. Clear
c. Load
d. Binary value between 1010 and 1111 on either digit loads as 9 (1001)
e. Countenable
f. Check precedence of function: clear overrides load, which overrides enable
Figure 2: Test Circuit for a 2-Digit BCD Counter.
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