School of Electronics and Mechanical Engineering Technology
DGS355 – Digital Systems
Lab 22 – Binary Counters (Block Diagram File)
Name: _____________________________________________ Section: _______ Note: This handout is an adaptation of Lab 22 of Dueck, Robert K., Digital Design with CPLD
Applications and VHDL, 2/e for the Online Delivery. Objectives
• Enter the design for a binary counter with synchronous load using the Quartus II Block Editor.
• Simulate the functions of the counter in this laboratory exercise. Book Reference
• Chapter 9: Counters and Shift Registers. Part 1 – Experimental Notes
Binary Counters from Flip-Flops
Though binary counters can be designed using any type of flip-flop, JK and D flip-flops are commonly used for this function. The synchronous input equations of the JK flip-flops of a binary counter follow a predictable sequence:
D flip-flops can also be used for binary counter. Their synchronous input equations also follow a predictable sequence:
These equations determine the next state of a counter by generating a toggle condition or a no change condition for each flip-flop throughout the count sequence. Typically, designing a counter with JK flip-flops yields simpler equations, but requires more work than D flip-flops, since the synchronous input of a D flip-flop is the same as its required next state, whereas the inputs of a JK flip-flop must be derived from an excitation table. For more detail, see Section 9.3 in Digital Design with CPLD Applications and VHDL, 2/e.
The logic diagram of a 3-bit binary counter based on D flip-flops is shown in Figure 1. Figure 2 shows a simulation of the 3-bit counter.
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School of Electronics and Mechanical Engineering Technology
Figure 1: 3-Bit Binary Counter.
Figure 2: Simulation of a 3-Bit Counter.
Figure 3: 3-Bit Binary Counter with Synchronous Load.
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School of Electronics and Mechanical Engineering Technology
The 3-bit counter can be modified as shown in Figure 3 to include a synchronous load function. Each flip-flop is fed by an AND-OR network (essentially a 2-to-1 multiplexer) that directs either the count logic or a parallel input to the synchronous input of the flip-flop. A simulation of this counter is shown in Figure 4. We can see that the load function is really synchronous because the first load pulse does not overlap or immediately precede a positive clock edge and is therefore ignored.
Figure 4: Simulation of a 3-Bit Binary Counter with Synchronous Load. Part 2 – Procedure
1. Openanewproject.
2. UsetheQuartusIIBlockEditortoenterthepresettable3-bitcountershowninFigure3.Save
the file as 3bit_dct_sl.bdf. Compile the project and create a simulation to verify its operation. Simulation criteria: ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________
3. Create a symbol for the 3-bit presettable counter from procedure 1.
4. Use the Quartus II Block Editor to create a test circuit for the counter, as shown in Figure 5. Save the file as 3bit_load.bdf. Compile the project and create a simulation to verify its operation.
Figure 5: 3-Bit Counter Test Circuit.
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