School of Electronics and Mechanical Engineering Technology
DGS355 – Digital Systems
Lab 20 – NAND Latches, D Latches, and D Flip-flops
Name: _____________________________________________ Section: _______ Note: This handout is an adaptation of Lab 20 of Dueck, Robert K., Digital Design with CPLD
Applications and VHDL, 2/e for the Online Delivery. Objectives
• Use the Quartus II Block Editor to create a NAND latch.
• Create multiple-bit latches and flip-flops in VHDL.
• Create simulations for the latches and flip-flops.
Book Reference
• Chapter 8: Introduction to Sequential Logic.
Part 1 – Experimental Notes
NAND Latch:
Figure 1 shows a NAND latch created using the Quartus II Block Editor.
Figure 1: NAND latch schematic.
The latch gates in Figure 1 are negative NAND gates. The component name for this gate in Quartus II is BOR2, meaning, somewhat inaccurately, “bubbled-OR, 2-input.” We label the inputs nS, nR and the outputs Q, nQ, where the “n” indicates logical negation (NOT function), thus telling us that nS, nR, and nQ are all active-LOW terminals.
D Latches and D Flip-Flops:
Two important digital circuits are the D latch and the D flip-flop, both of which are used to store
data. The main difference between the circuits is the conditions under which the data are stored.
In a D latch (or “transparent latch”), the output Q takes on the value of the input D only when an enable input (EN) is HIGH. (We say, “Q follows D.”) If D changes while EN = 1, Q will follow immediately. If EN = 0, Q retains its previous value and does not change with D. In a flip-flop, Q also follows D, but only when there is a transition on an enabling input called the clock (CLK). Typically, the clock input is shown as a triangle, indicating that it is a dynamic input. For a positive edge-triggered D flip-flop, Q follows D when the clock makes a transition from LOW to HIGH.
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Otherwise, Q will not change. Latches and flip-flops can also have multiple inputs and outputs, as shown in Figure 2. For these devices, all Qs follow all Ds on the appropriate enable condition. For example, if D3D2D1D0 = 0101, then Q3Q2Q1Q0 will equal 0101 after the first positive clock edge for the flip-flop or as soon as EN = 1 for the latch.
Figure 2: 4-Bit D Flip-Flop and Latch. VHDL Implementation of Latches and Flip-Flops:
There are a number of different ways to implement multibit latches and flip-flops in VHDL. Several methods for implementing latches are detailed in Chapter 8 of Digital Design with CPLD Applications and VHDL, 2/e. For a behavioural description of a D latch, an IF statement in a PROCESS is written to indicate the “Q follows D” property of the latch:
The PROCESS statement tests for a change in either en or d, since a change in either one of these alone, can make q change. A D flip-flop can be implemented in a similar way:
The construct clk’ EVENT (pronounced “clock tick event”) indicates that a change has just happened on the clock. This, combined with the test for a logic HIGH on the clock, indicates that a positive clock edge has just occurred. The PROCESS statement tests only for a change in clk, since no change of q is possible without a positive clock edge. Input d is not tested because it cannot make q change on its own. In both these structures, the ports Q and D can be single- variable ports (type BIT or STD_LOGIC) or multiple-bit ports (type BIT_VECTOR or STD_LOGIC_VECTOR).
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Part 2 – Procedure NAND Latch:
1. Openanewproject.
2. Create the schematic in Figure 1, and save it as nand_latch.bdf. Compile the project.
3. CreateasimulationthatshowstheSet\Resetbehaviourofthelatch.StartbymakingnSand nR both HIGH for the whole simulation period. Then add a LOW-going pulse on an input by dragging the mouse cursor across a portion of one of the input waveforms and clicking the “0” toolbar button. Repeat in several non-overlapping places for both input waveforms.
4-Bit D latch:
1. UsetheQuartusIITextEditortocreateaVHDLfilefora4-bitDlatch.Theinputportsshould consist of an enable input and a 4-bit d input. The output should be a 4-bit port called q. Save the file as dlatch.vhd and use it to create a Quartus II project. Compile the project.
2. Create a simulation that shows the behaviour of the 4-bit D latch. Suggested input:
a. Overwrite the d input with a group value (any single-digit hexadecimal number). Do this by highlighting the d waveform and clicking the “Arbitrary Value” toolbar button on the Waveform Editor toolbar. (This button has a “?” on it.)
b. Highlight the middle half of the d waveform by dragging the mouse cursor across it. Invert the value in the portion of d by clicking the “INV” toolbar button on the Waveform Editor toolbar.
c. Create a HIGH-going pulse on enable: highlight a small portion of the enable input close to the beginning and click the “1” toolbar button.
d. Highlight a second portion of the enable input shortly after the change on the d input and click the “1” toolbar button to create a second pulse.
3. CreateagraphicsymbolfromtheVHDLfileforthelatchbyselectingCreate/Update,Create Symbol Files for Current File from the Quartus II File menu.
4. UsetheQuartusIIBlockEditortocreatethecircuitshowninFigure3Savethefileasdrive: 4_bit_latch.bdf and use it to create a Quartus II project. Compile the project.
To connect the output of the D latch to the inputs of the seven-segment decoder, you must label the lines, as shown in Figure 3. Draw a line out of the latch. Click on the line to highlight it. Right-click the highlighted line, select Properties from the pop-up menu, and type q[3..0]. Repeat the procedure to label the lines going to the seven-segment decoder.
5. Create a new simulation that shows the behaviour of the 4-bit D latch connected to the HEX7SEG_CC.
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4-Bit D Flip-Flop
Figure 3: D Latch and Seven-Segment Decoder
1. Use the Quartus II Text Editor to create a VHDL file for a 4-bit D flip-flop. Save the file as d_flip_flop.vhd and use it to create a Quartus II project. Compile the project.
2. Create a simulation that shows the operation of the flip-flop.
3. Describethesimulationcriteriabelow: ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________
4. CreateagraphicsymbolfromtheVHDLfilefortheflip-flop.UsetheQuartusIIBlockEditor to create the circuit shown in Figure 4. Save the file as 4_bit_flip_flop.bdf and use it to create a Quartus II project. Compile the project.
Figure 4: 4-Bit Flip-Flop and Seven-Segment Decoder
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