LABORATORY 6 CHECKLIST
(Print this sheet to hardcopy and obtain initials)
PRE-LAB: You must show the TA that you have written the Verilog modules for the c17 circuit testbench at the BEGINNING of the lab session. No credit for writing your Verilog modules DURING the lab session. Your testbench should include a clock generator and should be used to simulate the c17 circuit implemented with different numbers of pipeline stages.
TA Initials: ____________________
DEMO: Demonstrate that your pipelined c17 design will function with different numbers of pipeline stages. You should show that the c17 circuit is functionally correct with 0, 1, 2, and 3 stages of pipelining.
TA Initials: ____________________
POST-LAB:
Write one paragraph and attach to this sheet in hardcopy describing the most difficult portion of this lab and also give two different things that you learned from doing this lab. Describe your process for determining the maximum clock frequency of your design.
Neatly draw a diagram of the c17 circuit with 0, 1, 2, and 3 pipeline stages. Determine the maximum clock frequency for each of the four different c17 designs (that is for 0, 1, 2, and 3 pipeline stages. You will need to report the following and you must show the detailed calculations for each (or the Vivado report if you use the tool).
Max. Clock Frequency (0 pipeline stages): _________________ Max. Clock Frequency (1 pipeline stages): _________________ Max. Clock Frequency (2 pipeline stages): _________________ Max. Clock Frequency (3 pipeline stages): _________________
Laboratory 6 Bit-level Pipelining
The objective of this lab is to introduce the student to bit-level pipelining using the c17 benchmark circuit. the student will also gin experience in instantiating a separately written module within another module.
You are provided with a Verilog file for a combinational logic circuit called ¡°c17.¡± You goal is to demonstrate that this design is functional by creating a testbench that exhaustively tests all possible circuit test vectors for the design as provided.
You should also create a separate module called Dff.v that instantiates a single D-flip-flop with a synchronous input that is activated at the rising edge of the clock. Dff.v should also have asynchronous set and reset inputs that are asserted with positive-true logic. You should write a separate testbench that instantiates and tests your Dff.v design. The testbench should include a clock generator that creates clock signal with a 20% duty cycle. Make sure your Dff.v testbench exercises all possible modes of operation including both the synchronous and asynchronous inputs.
Next, using the results of your c17.v simulation as the correct functional output, you are to create several pipelined versions of the c17 design as follows:
1) Create single stage pipeline by placing D-flip-flops at the inputs and outputs of the circuit. You should create a separate module called Dff.v that instantiates a single D-flip-flop with a synchronous input that is activated at the rising edge of the clock.
2) Create a pipelined version of c17 that has two pipeline stages and use your testbench to verify that your design is functionally correct.
3) Create a pipelined version of c17 that has three pipeline stages and use your testbench to verify that your design is functionally correct.
Implementation Guidelines
To pipeline the c17 circuit, you must determine where to place the Dff inside the netlist. You should not include the Verilog description of a D-flip-flop inside your pipelined c17 Verilog module. Instead, you should simply instantiate the Dff.v module just as you would instantiate another primitive gate.
If you do not receive the correct outputs in your pipelined designs, it is likely the case that you have unequal pipeline stages. This means that you either need to add additional flip-flops, or you have too many. Each internal path in the circuit must be broken into equal delay (as close as possible) partitions.
Timing and Maximum Clock Speed
Assuming that we have determined how to use the Vivado timing analyzer, use the tool to determine maximum clock speed for each pipelined design. In the event that this is not possible, you will need to calculate the maximum clock speed for each pipelined design (0, 1, 2, and 3 stages) manually. If we have to do the calculations manually, you will turn these calculations in with the post-lab report and you will use a delay value of 10ns for each NAND gate.
Pre-lab:
You must show the TA that you have written the Verilog modules (testnbenches for c17 and Dff as well as the pipelined version of c17 for pipeline stages 1, 2, and 3. No credit for writing your Verilog modules DURING the lab session. Your designs do NOT have to be perfectly functional, but you should show that you have actually attempted to capture the designs in Verilog before your lab meeting time starts.
Demo:
Show that your Dff is functioning correctly and show that your c17 testbench exhaustively tests the combinational logic version of c17. You should also demonstrate that your pipelined versions of c17 are functioning properly. This includes all three pipelined versions with stages of length 1, 2, and 3.