CS代写 Instruction Set Architecture

Instruction Set Architecture – I
1. Compare zero, one, two, and three-address machines by writing instructions to compute the following.
i) X = (A + B) ∗ (C + D)
The instructions available for use are as follows:

0 Address Stack
PUSH X Push the word at address X to the top of the Stack POP XPop the word from the top of stack to address X ADD  Add the top two elements in the stack
MUL  Multiply the top two elements in the stack
1 Address Accumulator
 AC←AC+M[X]
 AC←AC*M[X]
 R1←R1+M[X]
MUL R1, R2
 R1 ← R1∗R2
MUL R1, R2
R1 ← R1∗R2
ADD R1, X, Y
 R1←M[X]+M[Y]
MUL X, R1, R2
 M[X]←R1∗R2
* TOS = Top of Stack

2. Write the instructions for computing Y = (A-B) / (C + (D * E)) based on a stack architecture. You may refer to the table in question 1 to find out the respective definitions of operation in a stack based architecture.
In postfix notation, this will be: AB – CDE * + /. So, the instructions for the program will be as below:
; (A-B), C
; (A-B), C, D
; (A-B), C, D, E
; (A-B), C, (D*E)
; (A-B), (C+(D*E)) ; (A-B) / (C+(D*E))
3. A hypothetical machine has the following characteristics:
034 1501 15 S
Instruction Format
Program Counter (PC) Instruction Register (IR) Accumulator (AC)
Internal CPU Registers
Integer Format
0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory 0011 = Load AC from I/O
0111 = Store AC to I/O
Partial List of Opcodes
The 12-bit address identifies a particular I/O device. Show the program execution steps where the contents (e.g., 03) of the memory word at address 94016 are added to the contents (e.g., 02) of the memory word at address 94116 and the result stored in the latter location 94116.

4. Consider a toy machine with the following details.
The toy machine’s architecture:
The machine has 16 registers numbered 0 through F (in hexadecimal). Each register is two bytes (sixteen bits) long. Similar to MIPS the contents of register 0 is always 0 for this toy machine.
There are 256 cells in the machine’s main memory (addressed from 0x00 to 0xFF). Each cell contains two bytes (sixteen bits) of data.
The machine also has a special 8-bit register as the program counter (PC).
The toy machine’s language:
The machine can support maximum 16 different instructions, which can be used to make changes in the contents of the registers, memory, and PC in specified, well-defined ways. The machine supports two different instruction formats. The instruction formats and the description of the instructions (in Hex notation) are provided in the below diagram:

i. Consider that the memory location 0x00 and 0x01 holds the value 0x0008 and 0x0005 respectively. Write the instructions that will add the contents of these two memory cells, and store the result in the memory cell 0x02.
0x8A00 (Load register location 0xA with the contents from memory location 0x00)
0x8B01 (Load register location 0xB with the contents from memory location 0x01)
0x1CAB (Add the contents of register location 0xA and 0xB, and put the result in register location 0xC)
0x9C02 (Store the computed result to memory location 0x02)
0x0000 (Halt)
ii. Give a single instruction that changes the program counter to memory address 15 regardless of the contents of any registers or memory cells.

5. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes (opcode) are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits.
For each instruction set architecture shown in Figure above, how many addresses, or names, appear in each instruction for the code to compute C = A + B, and what is the total code size?
// one address appears in the instruction, code size = 8 bits (opcode) + 64 bits (memory address) = 72 bits;
// one address appears in the instruction, code size = 72 bits; Add
// zero address appears in the instruction, code size = 8 bits; Pop C
// one address appears in the instruction, code size = 72 bits; Total code size = 72 + 72 + 8 + 72 = 224 bits.
2) Accumulator
// one address appears in the instruction, code size = 8 bits (opcode) + 64 bits (memory address) = 72 bits;

// one address appears in the instruction, code size = 72 bits; Store C
// one address appears in the instruction, code size = 72 bits; Total code size = 72 + 72 + 72 = 216 bits.
3) Register-memory
Load R1, A
// two addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 64 bits (memory address) = 78 bits;
Add R3, R1, B
// three addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 6 bits (register address) + 64 bits (memory address) = 84 bits;
Store R3, C
// two addresses appear in the instruction, code size = 78 bits;
Total code size = 78 + 84 + 78 = 240 bits.
4) Register-register
Load R1, A
// two addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 64 bits (memory address) = 78 bits;
Load R2, B
// two addresses appear in the instruction, code size = 78 bits;
Add R3, R1, R2
// three addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 6 bits (register address) + 6 bits (register address) = 26 bits;
Store R3, C
// two addresses appear in the instruction, code size = 78 bits;
Total code size = 78 + 78 + 26 + 78 = 260 bits.

Instruction Set Architecture – II
1. The following problems deal with translating from C to MIPS. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program:
f = g + (h – 5)
For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions.
sub f, g, h
addi f, h, -5 add f,g,f
2. Write the MIPS instructions for the following C program.
# $s0 = i, $s1 = sum
addi $s1, $0, 0
add $s0, $0, $0
addi $t0, $0, 10
for: beq $s0, $t0, done
add $s1, $s1, $s0
addi $s0, $s0, 1
j for done:
#If i=10 go to done
#sum=sum+i

In the snippet of MIPS assembler code below, how many times is instruction memory accessed? How many times is data memory accessed? (Count only accesses to memory for each individual instruction, not registers.)
lw $t0, 0($t1)
addi $t0, $t0, 1 sw $t1, 0($t1) addi $t0, $t0, 1 Answer:
The instruction memory is accessed four times (as there are four instructions), and the data memory is accessed twice (once for the lw instruction and the other for the sw instruction).
Use the register and memory values in the table below for the next questions. Assume a 32-bit machine with addressing modes as discussed in H&P. Assume each of the following questions starts from the table values; that is, DO NOT use value changes from one question as propagating into future parts of the question.
Give the values of R1, R2, and R3 after this instruction: add R3, R2, R1 What values will be in R1 and R3 after this instruction is executed:
load R3, 12(R1)
What values will be in the registers after this instruction is executed:
addi R2, R3, 16
i. 12+16=28=>atend:R1=12,R2=16,R3=28
ii. Address to load from = 12 + 12 = 24. Value in mem location 24 = 28. So at end:
R1=12 still and R3=28
iii. 20 + 16 = 36. So at end of instruction: R3=20, R2=36

Decode the following MIPS instructions (explain in English what are the effects of these instructions to the least significant 16 bits of $t2).
ori $t0, $zero, 0xFF2B
and $t2, $t2, $t0
After the first instruction. $t0 contains 0xFF2B. This is equivalent to:
1111 1111 0010 1011
That is, in location 2, 4, 6, and 7 we have a zero, and when doing an AND operation with the contents of $t0 will set the corresponding bits of the output to zero.
So, this will clear/ turn off bits 2, 4, 6, and 7 of register $t2.
ori $t2, $t2, 0x00E9
0x00E9 is equivalent to binary representation of: 0000 0000 1110 1001
That is, in location 0, 3, 5, 6, and 7 we have a one, and when doing an OR operation with this, the resultant value will have these corresponding bits of the output set to one. So, this will set/ turn on bits 0, 3, 5, 6, and 7 of register $t2.
xori $t2, $t2, 0x85
0x0085 is equivalent to binary representation of: 0000 0000 1000 0101
That is, in location 0, 2, and 7 we have a one, and when doing an XOR operation with this, the resultant value will have these corresponding bits flipped/complemented in the output.
So, this will flip bits 0, 2, and 7 of register $t2.

6. What’s wrong with the following picture? Correct the corresponding MIPS code.
7. Write the MIPS code segment for the following snippet of C program.

8. Write the MIPS code segment for the following snippet of C program.

9. Write the MIPS code segment for the following snippet of C program.
You can use the following branch instruction to translate the code: bge $t0,$t1,target # branch to target if $t0 >= $t1.
For your reference, a list of additional branch instructions and their description is included in the following table:
Branch Instruction
blt $t0,$t1,target ble $t0,$t1,target bgt $t0,$t1,target bge $t0,$t1,target
# branch to target if $t0 < $t1 # branch to target if $t0 <= $t1 # branch to target if $t0 > $t1 # branch to target if $t0 >= $t1

10. Look at registers $12 and $13 and memory (given below). Write the instruction that puts the value 0x00000004 into register $12.
 Register $12 contains 0xFFFFFFFF
 Register $13 contains 0x00040000
Complete the instruction below to put the value 0x00000004 into register $12.: lw$ , ($ )
lw $12, 0x0010($13) or
lw $12, 16($13)
The original value in $12 is irrelevant; it is replaced with a value from memory (memory remains unchanged).

11. Considering the contents of the memory location as described in the previous question, and the specified register location with the following contents:
 Register $12 contains 0xFFFFFFFF
 Register $13 contains 0x00040014
Complete the instruction below to put the word 0xFFFFFFFF into memory location 0x0004000C. It is OK to specify the 16-bit offset as a signed decimal integer.
sw$ , ($ )
sw $12, 0xFFF8($13) or
sw $12, -8($13)

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