程序代写代做代考 data structure clock cache kernel algorithm Carnegie Mellon

Carnegie Mellon
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
1
14
–
513
18
–
613

Carnegie Mellon
Virtual Memory: Concepts
15-213/18-213/14-513/15-513/18-613: Introduction to Computer Systems
17th Lecture, October 27, 2020
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
2

Carnegie Mellon
Informal Survey Summary
 40% of Students Responded to the Survey
▪ Thank you!
 Over 35% felt the labs were the strongest feature
▪ Another 25% think the lectures contribute
▪ And 10% feel they learn significantly from the written assignments
 Around 20% of students note the pace is too fast
▪ Therefore, many feel that recorded lectures support their learning
 Chat is a great avenue for asking questions ▪ Can also be distracting
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
3

Carnegie Mellon
Informal Survey Summary (cont)  Many students feel welcomed and included
▪ Teaching Assistants and professors who care
 TA OH are an important part of learning
▪ Keeping to 10 minutes and understanding expectations ▪ Expect a separate Piazza post
 The instructors are happy to discuss the feedback further in their office hours
▪ Many other valuable points and suggestions Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
4

Carnegie Mellon
Hmmm, How Does This Work?!
Process 1 Process 2 Process n
Solution: Virtual Memory (today and next lecture)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
5

Carnegie Mellon
Today
 Address spaces
 VM as a tool for caching
 VM as a tool for memory management  VM as a tool for memory protection
 Address translation
CSAPP 9.1-9.2
CSAPP 9.3 CSAPP 9.4 CSAPP 9.5 CSAPP 9.6
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
6

Carnegie Mellon
A System Using Physical Addressing
Main memory
0: 1: 2: 3:
CPU 4 4: 5: 6: 7: 8:
M-1:
Data word
 Used in “simple” systems like embedded microcontrollers in
devices like cars, elevators, and digital picture frames
Physical address
(PA)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
7
…

Carnegie Mellon
A System Using Virtual Addressing
CPU Chip
Main memory
0: 1: 2: 3: 4: 5: 6: 7: 8:
M-1:
Virtual address
CPU (VA) MMU 4100
Physical address (PA)
4
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
8
Data word
 Used in all modern servers, laptops, and smart phones  One of the great ideas in computer science
…

Carnegie Mellon
Address Spaces
 Linearaddressspace:Orderedsetofcontiguousnon-negativeinteger addresses:
{0, 1, 2, 3 … }
 Virtual address space: Set of N = 2n virtual addresses {0, 1, 2, 3, …, N-1}
 Physical address space: Set of M = 2m physical addresses {0, 1, 2, 3, …, M-1}
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
9

Carnegie Mellon
Why Virtual Memory (VM)?  Uses main memory efficiently
▪ Use DRAM as a cache for parts of a virtual address space  Simplifies memory management
▪ Each process gets the same uniform linear address space
 Isolates address spaces
▪ One process can’t interfere with another’s memory
▪ User program cannot access privileged kernel information and code
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
10

Carnegie Mellon
Today
 Address spaces
 VM as a tool for caching
 VM as a tool for memory management  VM as a tool for memory protection
 Address translation
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
11

Carnegie Mellon
VM as a Tool for Caching
 Conceptually, virtual memory is an array of N contiguous bytes stored on disk.
 The contents of the array on disk are cached in physical memory (DRAM cache)
▪ These cache blocks are called pages (size is P = 2p bytes)
Unallocated
Cached
Uncached
Unallocated
Cached
Uncached
Cached
Uncached
VP 0 VP 1
0
Virtual memory
Physical memory
0
PP 0 PP 1
PP 2m-p-1
Empty
Empty
Empty
VP 2n-p-1
M-1
Virtual pages (VPs) stored on disk
Physical pages (PPs) cached in DRAM
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
12
N-1

Carnegie Mellon
DRAM Cache Organization
 DRAM cache organization driven by the enormous miss penalty ▪ DRAM is about 10x slower than SRAM
▪ Disk is about 10,000x slower than DRAM
▪ Time to load block from disk > 1ms (> 1 million clock cycles)
▪ CPU can do a lot of computation during that time
 Consequences
▪ Large page (block) size: typically 4 KB
▪ Linux “huge pages” are 2 MB (default) to 1 GB ▪ Fully associative
▪ Any VP can be placed in any PP
▪ Requires a “large” mapping function – different from cache memories ▪ Highly sophisticated, expensive replacement algorithms
▪ Too complicated and open-ended to be implemented in hardware
▪ Write-back rather than write-through Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
13

Carnegie Mellon
Enabling Data Structure: Page Table
 A page table is an array of page table entries (PTEs) that maps virtual pages to physical pages.
▪ Per-process kernel data structure in DRAM
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
14

Carnegie Mellon
Page Hit
 Page hit: reference to VM word that is in physical memory (DRAM cache hit)
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
0
null
1
1
0
1
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
15
Memory resident page table (DRAM)

Carnegie Mellon
Page Fault
 Page fault: reference to VM word that is not in physical memory (DRAM cache miss)
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
0
null
1
1
0
1
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
16
Memory resident page table (DRAM)

Carnegie Mellon
Triggering a Page Fault
 User writes to memory location
80483b7: c7 05 10 9d 04 08 0d movl $0xd,0x8049d10
 That portion (page) of user’s memory is currently on disk
 MMU triggers page fault exception ▪ (More details in later lecture)
▪ Raise privilege level to supervisor mode
▪ Causes procedure call to software page fault handler
User code Kernel code
movl
Exception: page fault
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
17
Execute page fault handler
int a[1000]; main ()
{
a[500] = 13; }

Carnegie Mellon
Handling Page Fault

Page miss causes page fault (an exception)
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
0
null
1
1
0
1
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
18
Memory resident page table (DRAM)

Carnegie Mellon
Handling Page Fault
 
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
0
null
1
1
0
1
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
19
Memory resident page table (DRAM)

Carnegie Mellon
Handling Page Fault
 
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
0
null
1
1
1
0
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
20
Memory resident page table (DRAM)

Carnegie Mellon
Handling Page Fault
  
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)
Offending instruction is restarted: page hit!
Physical memory (DRAM)
PP 0
PP 3
Virtual address
Physical page number or disk address
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
0
null
1
1
1
0
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Key point: Waiting until the miss to copy the page to DRAM is known as demand paging
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
21
Memory resident page table (DRAM)

Carnegie Mellon
Completing page fault
 Page fault handler executes return from interrupt (iret) instruction
▪ Like ret instruction, but also restores privilege level ▪ Return to instruction that caused fault
▪ But, this time there is no page fault
80483b7: c7 05 10 9d 04 08 0d movl $0xd,0x8049d10
User code
movl
Kernel code
int a[1000];
main ()
{
a[500] = 13; }
Exception: page fault
Return and reexecute movl
Copy page from disk to memory
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
22

Carnegie Mellon
Allocating Pages
 Allocating a new page (VP 5) of virtual memory.
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
0
null
1
1
1
0
0
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 5
VP 6
VP 7
 Subsequent miss will bring it into memory Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
23
Memory resident page table (DRAM)

Carnegie Mellon
Locality to the Rescue Again!
 Virtual memory seems terribly inefficient, but it works because of locality.
 At any point in time, programs tend to access a set of active virtual pages called the working set
▪ Programs with better temporal locality will have smaller working sets
 If (working set size < main memory size) ▪ Good performance for one process (after cold misses)  If (working set size > main memory size )
▪ Thrashing: Performance meltdown where pages are swapped (copied) in and out continuously
▪ If multiple processes run at the same time, thrashing occurs if their total working set size > main memory size
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
24

Carnegie Mellon
VM as a Tool for Memory Management
 Key idea: each process has its own virtual address space ▪ It can view memory as a simple linear array
▪ Mapping function scatters addresses through physical memory
▪ Well-chosen mappings can improve locality
PP 2
PP 6
PP 8
VP 1
VP 2
Virtual Address Space for Process 1:
0
Address 0 translation
Physical Address Space (DRAM)
(e.g., read-only library code)
…
VP 1
VP 2
Virtual Address Space for Process 2:
N-1
0
…
…
N-1
M-1
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
26

Carnegie Mellon
VM as a Tool for Memory Management  Simplifying memory allocation
▪ Each virtual page can be mapped to any physical page
▪ A virtual page can be stored in different physical pages at different times  Sharing code and data among processes
▪ Map virtual pages to the same physical page (here: PP 6)
PP 2
PP 6
PP 8
VP 1
VP 2
Virtual Address Space for Process 1:
0
Address 0 translation
Physical Address Space (DRAM)
(e.g., read-only library code)
…
VP 1
VP 2
Virtual Address Space for Process 2:
N-1
0
…
…
N-1
M-1
27
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Carnegie Mellon
Simplifying Linking and Loading  Linking
▪ Each program has similar virtual address space
▪ Code, data, and heap always start at the same addresses.
 Loading
▪ execve allocates virtual pages for .text and .data sections & creates PTEs marked as invalid
▪The.text and.data sections are copied, page by page, on demand by the virtual memory system
0x400000
Memory invisible to user code
%rsp
(stack pointer)
Kernel virtual memory
User stack (created at runtime)
Memory-mapped region for shared libraries
Run-time heap (created by malloc)
Read/write segment (.data, .bss)
Read-only segment (.init, .text, .rodata)
Unused
brk
Loaded from
the executable file
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
0 28

Carnegie Mellon
VM as a Tool for Memory Protection  Extend PTEs with permission bits
 MMU checks these bits on each access
Process i:
VP 0: VP 1: VP 2:
SUP READ
WRITE
EXEC
Address
Physical Address Space
No
Yes
No
Yes
PP 6
No
Yes
Yes
Yes
PP 4
Yes
Yes
Yes
No
PP 2
PP 2
PP 4
PP 6
PP 8
PP 9
PP 11
Process j:
VP 0: VP 1: VP 2:
SUP READ WRITE EXEC
Address
• • •
No
Yes
No
Yes
PP 9
Yes
Yes
Yes
Yes
PP 6
No
Yes
Yes
Yes
PP 11
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
SUP: requires kernel mode 30

Carnegie Mellon
Quiz Time!
Check out:
https://canvas.cmu.edu/courses/17808
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
31

Carnegie Mellon
VM Address Translation  Virtual Address Space
▪ V = {0, 1, …, N–1}
 Physical Address Space
▪ P = {0, 1, …, M–1}
 Address Translation ▪ MAP: V → P U {} ▪ For virtual address a:
▪ MAP(a) = a’ if data at virtual address a is at physical address a’ in P ▪ MAP(a) =  if data at virtual address a is not in physical memory
– Either invalid or stored on disk
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
33

Carnegie Mellon
Summary of Address Translation Symbols
 Basic Parameters
▪ N = 2n : Number of addresses in virtual address space
▪ M = 2m : Number of addresses in physical address space ▪ P = 2p : Page size (bytes)
 Components of the virtual address (VA) ▪ VPO: Virtual page offset
▪ VPN: Virtual page number
 Components of the physical address (PA) ▪ PPO: Physical page offset (same as VPO)
▪ PPN: Physical page number
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
34

Carnegie Mellon
Address Translation With a Page Table
Virtual address
n-1
Page table
p p-1 0
Page table base register (PTBR) (CR3 in x86)
Virtual page number (VPN)
Virtual page offset (VPO)
Physical page table address for the current process
Valid bit = 0: Page not in memory (page fault)
Valid bit = 1
m-1
Physical address
Valid
Physical page number (PPN)
p p-1 0
Physical page number (PPN)
Physical page offset (PPO)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
35

Carnegie Mellon
Address Translation: Page Hit
2
PTEA PTE 3
PA
4
CPU Chip
CPU
1
VA
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
36
Data
5
MMU
Cache/ Memory

Carnegie Mellon
Address Translation: Page Fault
Exception
4
2
PTEA PTE
3
Page fault handler
Victim page
5
New page
6
CPU Chip
CPU
1
VA
7
MMU
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory
4) Valid bit is zero, so MMU triggers page fault exception
5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restarting faulting instruction Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
37
Cache/ Memory
Disk

Carnegie Mellon
Integrating VM and Cache PTE
PTEA
PTE
CPU Chip
CPU
VA
MMU
PA
PTEA
PA
Memory
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
38
Data
L1 cache
VA: virtual address, PA: physical address, PTE: page table entry, PTEA = PTE address
PTEA hit
PTEA miss
PA miss
PA hit
Data

Carnegie Mellon
Speeding up Translation with a TLB
 Page table entries (PTEs) are cached in L1 like any other memory word
▪ PTEs may be evicted by other data references ▪ PTE hit still requires a small L1 delay
 Solution: Translation Lookaside Buffer (TLB)
▪ Small set-associative hardware cache in MMU
▪ Maps virtual page numbers to physical page numbers
▪ Contains complete page table entries for small number of pages
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
39

Carnegie Mellon
Summary of Address Translation Symbols
 Basic Parameters
▪ N = 2n : Number of addresses in virtual address space
▪ M = 2m : Number of addresses in physical address space ▪ P = 2p : Page size (bytes)
 Components of the virtual address (VA) ▪ TLBI: TLB index
▪ TLBT: TLB tag
▪ VPO: Virtual page offset
▪ VPN: Virtual page number
 Components of the physical address (PA) ▪ PPO: Physical page offset (same as VPO)
▪ PPN: Physical page number
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
40

Carnegie Mellon
Accessing the TLB
 MMU uses the VPN portion of the virtual address to access the TLB:
T = 2t sets
p p-1 0
TLBT matches tag of line within set
VPN n-1 p+t p+t-1
TLB tag (TLBT)
TLB index (TLBI)
VPO
v
tag
PTE
v
tag
PTE
Set 0 Set 1
Set T-1
TLBI selects the set
v
tag
PTE
v
tag
PTE
v
tag
PTE
v
tag
PTE
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
41
…

Carnegie Mellon
TLB Hit
CPU Chip
TLB
PTE
3
2
VPN
CPU
1
VA
MMU
PA
4
Cache/ Memory
Data
5
A TLB hit eliminates a cache/memory access
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
42

Carnegie Mellon
TLB Miss
CPU Chip
TLB
2
VPN
4
PTE
3
PTEA
PA
5
CPU
1
VA
MMU
Cache/ Memory
Data
6
A TLB miss incurs an additional cache/memory access (the PTE)
Fortunately, TLB misses are rare. Why?
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
43

Carnegie Mellon
Multi-Level Page Tables  Suppose:
▪ 4KB (212) page size, 48-bit address space, 8-byte PTE
Level 2 Tables
 Problem:
▪ Would need a 512 GB page table!
Level 1 Table
▪248 *2-12 *23 =239 bytes
 Common solution: Multi-level page table
 Example: 2-level page table
▪ Level 1 table: each PTE points to a page table (always
memory resident)
▪ Level 2 table: each PTE points to a page (paged in and out like any other data)
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
44
…
…

Carnegie Mellon
A Two-Level Page Table Hierarchy
Level 1 page table
Level 2 page tables
Virtual memory
0
VP 0
…
VP 1023
VP 1024
…
VP 2047
Gap
1023 unallocated pages
VP 9215
PTE 0
…
PTE 1023
PTE 0
2K allocated VM pages for code and data
PTE 1
PTE 2 (null)
PTE 3 (null)
PTE 0
…
PTE 1023
PTE 4 (null)
PTE 5 (null)
PTE 6 (null)
PTE 7 (null)
6K unallocated VM pages
PTE 8
1023 null PTEs
(1K – 9) null PTEs
PTE 1023
64 bit addresses, 8KB pages, 8-byte PTEs
1023 unallocated pages
1 allocated VM page for the stack
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
45
…

Carnegie Mellon
Translating with a k-level Page Table
Page table base register (PTBR)
n-1
VIRTUAL ADDRESS
p-1 0
VPN 1
the Level 1 page table
a Level 2 page table
a Level k page table
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
46
VPN 2
…
… …
m-1
p-1 0
PPN
PPO
PHYSICAL ADDRESS
VPN k
VPO
PPN

Carnegie Mellon
Summary
 Programmer’s view of virtual memory
▪ Each process has its own private linear address space ▪ Cannot be corrupted by other processes
 System view of virtual memory
▪ Uses memory efficiently by caching virtual memory pages
▪ Efficient only because of locality
▪ Simplifies memory management and programming
▪ Simplifies protection by providing a convenient interpositioning point to check permissions
 Implemented via combination of hardware & software ▪ MMU, TLB, exception handling mechanisms part of hardware
▪ Page fault handlers, TLB management performed in software
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
47

Related Posts