L2_1 – Instruction Set Architecture – Introduction
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission
Learning Objectives
• To identify the information of an Instruction Set Architecture (ISA)
• Be able to identify trade-offs relevant to ISA design
• Identify basic, course-granularity operation of a computer • Fetch, Decode, Execute
EECS 370 – Introduction to Computer Organization
2
Instruction Set Architecture (a.k.a. Architecture)
Instruction Set Architecture (ISA)
• An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory accesses, I/O, and so on.
Instruction Set Architecture (ISA) Includes anything programmers need to know to make a binary program work correctly
Instruction Set Architecture (ISA)
Defines interface between hardware and software
EECS 370 – Introduction to Computer Organization
3
ISAs
Application software Compilers
Architecture – a.k.a. ISA
• Platform-specific
• A limited set of assembly language commands
available by hardware
• e.g., ADD, LOAD, STORE, RET
The software / hardware divide
Microarchitecture – hardware implementation of ISA
• Intel Core i9/i7/i5 implements x86 ISA (desktop/laptop)
• Apple A9 implements ARM v8-A ISA (iPhone)
Circuits Devices
EECS 370 – Introduction to Computer Organization
4
ISAs
Application software
Compilers
Implementation of design specification for software and hardware for – ISA
Architecture – a.k.a. ISA
• Platform-specific
• A limited set of assembly language commands
available by hardware
• e.g., ADD, LOAD, STORE, RET
Microarchitecture – hardware implementation of ISA
• Intel Core i9/i7/i5 implements x86 ISA (desktop/laptop)
• Apple A9 implements ARM v8-A ISA (iPhone)
Circuits
The software / hardware divide
Devices
EECS 370 – Introduction to Computer Organization
5
(Simplified) System Organization
CPU
Memory
ALU Registers
X0 = 0 X1 = … X2 = … …
32 x 64 bits PC
0x0A02
0xFFFF
0x0000
LOAD STORE
CPU – Central Processing Unit
ALU – Arithmetic Logic Unit, executes instructions
PC – Program Counter, holds address (in memory) of next instruction
EECS 370 – Introduction to Computer Organization
6
von Neumann Architecture
• von Neumann Architecture
• Data and instructions are stored in the same memory
• Programs (instructions) can be viewed as data – simplifies storage
• Data can be viewed as instructions – complicates security
Program counter (PC)
0x0A02
Instruction register (IR)
0x0A0001
EECS 370 – Introduction to Computer Organization
7
von Neumann Architecture
• von Neumann Architecture
• Data and instructions are stored in the same memory
• Programs (instructions) can be viewed as data – simplifies storage
• Data can be viewed as instructions – complicates security
• Instructions are stored sequentially in memory
• Accessed by the program counter (PC) —it contains the
address/location of the instruction the hardware is executing
• The PC is simply incremented to “point to” the next instruction
• “jumps” / “branches” override fetching the sequential next instruction
• Terminology: Jumps are usually unconditional, and branches are conditional on a flag being checked
• there are conditional jumps…. EECS 370 – Introduction to Computer Organization
8
Program counter (PC)
0x0A02
Instruction register (IR)
0x0A0001
von Neumann Architecture
1.
Fetch – get the next instruction. Use the PC to find instruction, put into instruction register (IR).
1. The PC is changed to “point” to the next instruction in the program
2. Assume that the next instruction is sequential and contiguous in memory
Program counter (PC)
0x0A02
Instruction register (IR)
0x0A0001
EECS 370 – Introduction to Computer Organization
9
von Neumann Architecture
1.
Fetch – get the next instruction. Use the PC to find instruction, put into instruction register (IR).
1. The PC is changed to “point” to the next instruction in the program
2. Assume that the next instruction is sequential and contiguous in memory
Decode – control logic examines the contents of the IR to decide what functionality to perform
Program counter (PC)
0x0A02
2.
Instruction register (IR)
0x0A0001
EECS 370 – Introduction to Computer Organization
10
von Neumann Architecture
1.
Fetch – get the next instruction. Use the PC to find instruction, put into instruction register (IR).
1. The PC is changed to “point” to the next instruction in the program
2. Assume that the next instruction is sequential and contiguous in memory
Decode – control logic examines the contents of the IR to decide what functionality to perform
Execute – the outcome of the decoding process dictates:
1. An arithmetic or logic operation on data
2. The kind of access to data in the same memory as instructions
3. OR the outcome is a change of contents of the PC
Program counter (PC)
0x0A02
2. 3.
Instruction register (IR)
0x0A0001
EECS 370 – Introduction to Computer Organization
11
von Neumann Architecture
1.
Fetch – get the next instruction. Use the PC to find instruction, put into instruction register (IR).
1. The PC is changed to “point” to the next instruction in the program
2. Assume that the next instruction is sequential and contiguous in memory
Decode – control logic examines the contents of the IR to decide what functionality to perform
Execute – the outcome of the decoding process dictates:
1. An arithmetic or logic operation on data
2. The kind of access to data in the same memory as instructions
3. OR the outcome is a change of contents of the PC
Go to step 1
Program counter (PC)
0x0A02
2. 3.
Instruction register (IR)
0x0A0001
4.
EECS 370 – Introduction to Computer Organization
12
Instruction Set Architecture – Design Space 1
• What instructions should be included?
• add, multiply, divide, sqrt [functions]
• branch [flow control]
• load/store [storage management]
• Whatstoragelocations?
• How many registers?
• How much memory?
• Any other “architected” storage?
• How should instructions be formatted?
• 0, 1, 2 or more operands?
• Immediate operands
CPU
Memory
ALU Registers
32 x 64 bits PC
0x0A02
X0 = 0
X1 = …
X2 = …
…
0xFFFF
0x0000
LOAD STORE
EECS 370 – Introduction to Computer Organization
13
Instruction Set Architecture – Design Space 2
• How to encode instructions?
• RISC (Reduced Instruction Set Computer):
all instructions are same length (e.g. ARM, LC2K)
smaller set of simpler instructions
• CISC (Complex Instruction Set Computer):
instructions can vary in size (Digital Equipment’s VAX, x86)
large set of simple and complex instructions • What instructions can access memory?
• For ARM and LC2K, only loads and stores can access memory (called a “load-store architecture”)
• Intel x86 is a “register-memory architecture”, that is, other instructions beyond load/store can access memory
• Also Compute in Memory (currently a research topic) – simple operations performed in memory without data moving to/from the processor.
EECS 370 – Introduction to Computer Organization
14
Many Choices, Many ISAs
• Why are there many ISAs?
• Many problem domains, design constraints (e.g., power), differences of
opinion
• How often are new architectures created?
• New embedded processors are created all the time
• Existing ISAs are extended for new problem domains • X86: MMX, MMX2, SSE, AVX, x87, x64
• Can you design one? • Yes!
EECS 370 – Introduction to Computer Organization
15
High-Level to Low-Level Language to Hardware
int main() {
int a, *b, c;
c = a + *b;
}
.text
.global_main
X1 = LOAD(X2);
X3 = ADD(X1, X4);
0x7456
0xA16B
C program
Assembly Code
Machine Code
Machine
EECS 370 – Introduction to Computer Organization
16
Compile
Assemble
Load
Logistics
• No worksheet for this video
EECS 370 – Introduction to Computer Organization
17
L2_2 Assembly and Instruction Encoding
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission
Learning Objectives
• To understand the process of encoding an assembly instruction • Converting from assembly to machine code
• After completing this video and associated worksheet:
• You should be able to encode assembly instructions, necessary for Project 1
EECS 370 – Introduction to Computer Organization
2
Assembly Code – Instruction Encoding
• Fields
• Opcode – What instruction to perform
• Source (input) operand specifier(s) • What data to perform operation on
• Destination (output) operand specifiers(s) • What data to updated
opcode dest src1
src2
ADD
X2
X1
100
Execution: value in register X2 = contents reg. X1 + constant 100 EECS 370 – Introduction to Computer Organization
3
Assembly Code – Properties
• Generally 1-1 correspondence with machine language
• Mnemonic codes facilitate programming
• Labels ( symbolic names )
• Direct control of the what processor does
• May execute fast, if you’re good at it, but compilers can typically generate better code
• Still hard to use and not portable to other brands of machines
EECS 370 – Introduction to Computer Organization
4
Assembly – ARM Execution Example
Program
Opcode
Destination Register
Source Reg. 1
Source Reg. 2 / Immediate
Pseudocode
ADD
X3,
X1,
X2
X3 = X1 + X2
ADDI
X3,
X3,
#3
X3 = X3 + 3
SUB
X2,
X3,
X1
X2 = X3 – X1
Register
Initial
ADD X3, X1, X2
ADDI X3, X3, #3
SUB X2, X3, X1
X1
25
X2
-4
X3
57
EECS 370 – Introduction to Computer Organization
5
Assembly – ARM Execution Example
Program
Opcode Destination Register
Source Reg. 1
ADD X3, ADDI X3, SUB X2,
Register Initial
X1, X3, X3,
ADD X3, X1, X2
Source Reg. 2 / Immediate
X2 #3 X1
ADDI X3, X3, #3
Pseudocode
X3 = X1 + X2
X3 = X3 + 3
X2 = X3 – X1
SUB X2, X3, X1
X1 X2 X3
25 -4 57
EECS 370 – Introduction to Computer Organization
6
Assembly – ARM Execution Example
Program
Opcode
Destination Register
Source Reg. 1
Source Reg. 2 / Immediate
Pseudocode
ADD
X3,
X1,
X2
X3 = X1 + X2
ADDI
X3,
X3,
#3
X3 = X3 + 3
SUB
X2,
X3,
X1
X2 = X3 – X1
Register
Initial
ADD X3, X1, X2
ADDI X3, X3, #3
SUB X2, X3, X1
X1
25
25
25
25
X2
-4
-4
-4
-1
X3
57
21
24
24
EECS 370 – Introduction to Computer Organization
7
Assembly – Instruction Encoding
• Instructions are stored as data in memory • Each instruction is encoded as a number
opcode
dest src1 src2
ADD
X2
X3
X1
011011
010
011
001
011011010011001 = 20 + 23 + 24 + 27 + 29 + 210 + 212 + 213 = 13977 EECS 370 – Introduction to Computer Organization
8
Assembly – Register Addressing
opcode dest src1 src2
ADD
X2
X3
X1
011011
010
011
001
Using 6 bits, how many opcodes can this ISA implement?
EECS 370 – Introduction to Computer Organization
9
Assembly – Register Addressing
opcode dest src1 src2
X2 X3 X1 011011 010 011 001
Using 6 bits, how many opcodes can this ISA implement?
ADD
EECS 370 – Introduction to Computer Organization
10
Assembly – Register Addressing
opcode
dest
src1 src2
ADD
X2
X3
X1
011011
010
011
001
Using 6 bits, how many opcodes can this ISA implement?
• m bits can encode 2m different values
• n values can be encoded in ⎡log2(n)⎤ bits • Forabove
• Can encode 26 = 64 opcodes
• Can encode 23 = 8 src/destination registers
EECS 370 website has a lot of video tutorials, including binary representation https://www.youtube.com/watch?v =KGPfymjE2z8&feature=youtu.be
EECS 370 – Introduction to Computer Organization
11
Instruction Encoding – Example 1
What is the max number of registers that can be designed in a machine given: * 16-bit instructions
* Num. opcodes = 100
* All instructions are (reg, reg) reg
(i.e., 2 source operands, 1 destination operand, all operands can access all registers)
opcode
dest
src1
src2
EECS 370 – Introduction to Computer Organization
12
16 Bits total
Instruction Encoding – Example 1
What is the max number of registers that can be designed in a machine given: * 16-bit instructions
* Num. opcodes = 100
* All instructions are (reg, reg) reg
(i.e., 2 source operands, 1 destination operand, all operands can access all registers)
opcode dest src1 src2 16 Bits total
EECS 370 – Introduction to Computer Organization
13
Instruction Encoding – Example 1
What is the max number of registers that can be designed in a machine given: * 16-bit instructions
* Num. opcodes = 100
* All instructions are (reg, reg) reg
(i.e., 2 source operands, 1 destination operand, all operands can access all registers)
opcode
dest
src1
src2
16 Bits total
1.num opcode bits = ⎡log2(100)⎤ = 7 2.num bits for operands = 16 –7 = 9 3.num bits per operand = 9 / 3 = 3 4.maximum number of registers = 2^3 = 8
EECS 370 – Introduction to Computer Organization
14
Instruction Encoding – Example 2
Given the following ISA instruction fields:
ADD opcode is 53
Register fields encoded with register number
What is the binary / hex / decimal encoding?
opcode
dest
src1
src2
binary hex
decimal
7 bits
3 bits
3 bits 3 bits
dest src1 src2
opcode
ADD
X2
X3
X1
EECS 370 – Introduction to Computer Organization
15
Instruction Encoding – Example 2
Given the following ISA instruction fields:
ADD opcode is 53
Register fields encoded with register number
What is the binary / hex / decimal encoding?
binary hex
decimal
opcode 7 bits
dest 3 bits
src1
3 bits dest
src2
3 bits src1
opcode
ADD
src2
EECS 370 – Introduction to Computer Organization
16
X2 X3 X1
Instruction Encoding – Example 2
Given the following ISA instruction fields:
ADD opcode is 53
Register fields encoded with register number
What is the binary / hex / decimal encoding?
opcodec
dest
src1
src2
binary hex
decimal
7 bits
3 bits
3 bits 3 bits
dest src1 src2
opcode
ADD
X2
X3
X1
011 0101
010
011
001
0x6A99
27289
EECS 370 – Introduction to Computer Organization
17
Logistics
• This is the second of 3 videos for lecture 2 • L2_1 – ISA Introduction
• L2_2 – Assembly and Instruction Encoding • L2_3 – Assembly Decoding
• There is one worksheet for lecture 2
• One exercise on encoding, one for decoding
• Move on to L2_3.
EECS 370 – Introduction to Computer Organization
18
L2_3 Assembly Instruction Decoding
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission
Learning Objectives
• To understand the process of decoding an assembly instruction • Converting from machine to assembly code
• After completing this video and associated worksheet:
• You should be able to decode machine code instructions, necessary for
Project 1
EECS 370 – Introduction to Computer Organization
2
Instruction Decoding – Example
• Decoding: Given a machine instruction in decimal, convert to assembly decimal
7 bits 3 bits 3 bits 3 bits
27292
opcodec
dest
src1
src2
What steps are used to decode a machine code instruction?
EECS 370 – Introduction to Computer Organization
3
Instruction Decoding – Example
• Decoding: Given a machine instruction in decimal, convert to assembly decimal
27292
opcodec
dest
src1
src2
1. Convert to binary
2. Separate into fields
3. Convert to decimal
4. Convert assembly instruction fields
EECS 370 – Introduction to Computer Organization
4
7 bits
3 bits
3 bits
3 bits
1. Convert to Binary
• Given a machine instruction in decimal, convert to binary
decimal
27292
EECS 370 – Introduction to Computer Organization
5
1. Convert to Binary
• Given a machine instruction in decimal, convert to binary decimal
Convert with powers of two:
27292 = 214 (16384) + 213 (8192) + 211 (2048) + 29 (512) + 27 (128) + 24 (16) + 23 (8) + 22 (4) = 0110 1010 1001 1100
27292
EECS 370 – Introduction to Computer Organization
6
2. Separate into Fields
• Given a machine instruction in binary, separate into fields
decimal
0110 1010 1001 1100
27292
opcodec 7 bits
dest 3 bits
src1
3 bits
src2
3 bits
EECS 370 – Introduction to Computer Organization
7
2. Separate into Fields
• Given a machine instruction in binary, separate into fields decimal
27292
0110 1010 1001 1100
0110101
7 bits
010
3 bits
011
3 bits
100
3 bits
opcodec
dest
src1
src2
EECS 370 – Introduction to Computer Organization
8
3. Convert Fields to Decimal
• Given a machine instruction in binary in fields, convert to decimal decimal
27292
0110101 010
011 100
opcodec dest src1
src2
EECS 370 – Introduction to Computer Organization
9
3. Convert Fields to Decimal
• Given a machine instruction in binary in fields, convert to decimal decimal
27292
0110101 010
011 100
53
2
3
4
EECS 370 – Introduction to Computer Organization
10
opcode dest src1
src2
4. Convert to Assembly
• Given a machine instruction in fields in decimal, convert to assembly decimal
0110101 010 011 100
53 2 3 4
27292
From previous example:
ADD opcode is 53
EECS 370 – Introduction to Computer Organization
11
opcodec dest src1
src2
4. Convert to Assembly
• Given a machine instruction in in decimal, convert to assembly decimal
0110101 010 011 100
53 2 3 4
27292
ADD
X2
X3
X4
EECS 370 – Introduction to Computer Organization
12
opcodec dest src1
src2
From previous example:
ADD opcode is 53
Decoding Example 2: LC-2K
Decode LC-2K machine code to LC-2K assembly: 16842754
EECS 370 – Introduction to Computer Organization
13
Logistics
• This is the final of 3 videos for lecture 2 • L2_1 – ISA Introduction
• L2_2 – Assembly and Instruction Encoding • L2_3 – Assembly Decoding
• There is one worksheet for lecture 2
• One exercise on encoding, one for decoding
• Complete the participation quiz for lecture 2 on Canvas • Due by 9/6 at 11:59 pm
EECS 370 – Introduction to Computer Organization
14