程序代写代做代考 x86 arm assembly C L4_1 ARM-ISA_Arithmetic- Logical_Instructions

L4_1 ARM-ISA_Arithmetic- Logical_Instructions
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission

Learning Objectives
• Recognize the set of instructions for ARM Architecture (ISA) and be able to describe the operations and operands for instructions
• LEGv8 subset
• Ability to create simple ARM assembly programs, e.g., using
mathematical, logic, and memory operations
EECS 370 – Introduction to Computer Organization
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Resources
• Many resources on 370 website
• https://www.eecs.umich.edu/courses/eecs370/eecs370.f20/resources/
• ARMv8 references • Discussion recordings
• Piazza
• Office hours
EECS 370 – Introduction to Computer Organization
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ARMs and LEGs
• ARMv8 is the 64 bit version—all registers are 64 bits wide COMPUTER ORGANIZATION AND DESIGN | 235mm x 191mm Trim | 23.813 mm spine
• Addresses are calculated to be 64 bits too
COMPUTER ORGANIZATION
AND DESIGN
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PATTERSON HENNESSY
COMPUTER
• BUT: Instructions are 32 bits
• We use a (small) subset of the v8 ISA used
ORGANIZATION
®
ARM EDITION
DAVIDA.PATTERSON | JOHNL.HENNESSY
“ W e a r e d e l i g h t e d t o s u p p o r t t h i s e d i t i o n o f Co m p u t e r O r g a n i z a t i o n a n d D e s i g n , a t e x t b o o k t h a t h a s i n s p i r e d g e n e r a t i o n s o f computer scientists and engineers.This new edition will enable students and engineers worldwide to learn and master the theory,whilepracticingwiththemostwidelyusedprocessor architectureinmobilecomputingtoday.”
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The new ARM Edition of Computer Organization and Design has been updated to feature a subset of the ARMv8- A architecture, which is used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memoryhierarchies,andI/O.
With the post- PC era now upon us, Computer Organization and Design moves forward to explore this generational change with examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Updated content featuring tablet computers, Cloud infrastructure, and the ARM (mobile computing devices) and x86 (Cloud computing) ar chitectures is included.
ARM EDITION FEATURES
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ARM® EDITION
DAVID A. PATTERSON JOHNL.HENNESSY
For evaluation purposes only. Distribution or duplication is not allowed without permission in writing from the publisher.
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A n o n l i n e c o m p a n i o n W e b s i t e p r o v i d e s l i n k s t o a f r e e Co m m u n i t y E d i t i o n o f t h e A R M D S – 5 p r o f e s s i o n a l s o f t w a r e s u i t e w h i c h c o n t a i n s an ARMv8- A (64- bit) architecture simulator, as well as additional advanced content for fur ther study, appendices, glossar y, references, and recommended reading.
in P+H
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that
• Discussesandhighlightsthe“EightGreatIdeas”ofcomputerarchitecture: PerformanceviaParallelism;Performancevia
improve perf
ormance by 200X
Pipelining;PerformanceviaPrediction;Designfor Moore’sLaw;HierarchyofMemories;AbstractiontoSimplifyDesign;Make
the Common Case Fast; and Dependability via Redundancy • Includes a full set of updated and improved exercises
ABOUT THE AUTHORS
David A. Patterson
Pardee Chair of Computer Science University of California at Berkeley
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President
Stanford University
EECS 370 – Introduction to Computer Organization
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COMPUTER ORGANIZATION AND DESIGN

ARM Instruction Set—LEGv8 subset
• The main types of instructions fall into the familiar classes we saw with LC-2K:
1.Arithmetic
• Add, subtract, multiply (not in LEGv8)
2.Data transfer
• Loads a stores—LDUR (load unscaled register), STUR, etc.
3. Logical
• AND,ORR,EOR,etc.
• Logical shifts, LSL, LSR
4.Conditional branch • CBZ,CBNZ,B.cond
5.Unconditional branch (jumps) • B, BR, BL
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LEGv8 Arithmetic Instructions
• Format: three operand fields
• Destination register usually the first one – check instruction format
• ADD X3, X4, X7 – Think ADD X3 = X4, X7
• LC-2K generally has the destination on the right!!!!
• e.g. add 1 2 3 // r3 = r1 + r2
• C-code example: f = (g + h) – (i + j)
Map operands to registers
ADD X1, X3, X4 ADD X2, X5, X6 SUB X7, X1, X2
Map to ARM (simple) operations
ADD t0, g, h
ADD t1, i, j
SUB f, t0, t1
Register to variable mapping
X3→g X4→h X5→i X6→j
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LEGv8 R-instruction Fields
• Register-to-register operations
• Consider ADD X3, X4, X7
• R[Rd] = R[Rn] + R[Rm]
• Rd = X3, Rn = X4, Rm = X7
• Rm = second register operand • shamt = shift amount
• not used in LEG for ADD/SUB and set to 0
•Rn=first registeroperand
• Rd = destination register
• ADD opcode is 10001011000, what are the other fields?
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LEGv8 Arithmetic Operations
• Machine State—more on this concept as our understanding evolves
1. Registers: 32 registers, 64-bit wide. X31 aliased to XZR which is always 0
– cannot use as a destination
2. PC—Program counter
3. FLAGS: NZVC – record the results of (arithmetic) operations Negative, Zero, oVerflow, Carry—not present in LC2K
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I-instruction fields
• Format: second source operand can be a register or Immediate—a constant in the instruction itself
• e.g., ADDI X3, X4, #10
• Format: 12 bits for immediate constants 0-4095
• Do not need negative constants because we have SUBI
ARM LEGv8
ADDI X7, X5, #10 SUBI X7, X5, #10
C-code instructions
f = g + 10 f = g – 10
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LEGv8 Logical Instructions
• Logical operations are bit-wise
• For example assume
• X9 = 11111111 11111111 11111111 00000000 00000000 00000000 00001101 11000000 • X14 = 00000000 00000000 11011010 00000000 00000000 00000000 00111100 00000000
AND X2, X13, X9 would result in
• X2 = 00000000 00000000 11011010 00000000 00000000 00000000 00001100 00000000
• AND and OR correspond to C operators & and |
• For immediate fields the 12-bit constant is padded with zeros to the left—zero extended
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LEGv8 Shift Logical Instructions
• LSR X6, X23, #2
X23 = 11111111 11111111 11111111 00000000 00000000 00000000 11011010 00000010 X6 = 00111111 11111111 11111111 11000000 00000000 00000000 00110110 10000000
• C-code equivalent : X6 = X23 >> 2;
• Question: LSL X6, X23, #2 ?
• What register gets modified?
• What does it contain after executing the LSL instruction?
• In shift operations Rm is always 0—shamt is 6-bit unsigned
Shifting right by one bit -> divide by 2 Shifting left by one bit -> multiple by 2
EECS 370 – Introduction to Computer Organization
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LEGv8 Shift Logical Instructions
• LSR X6, X23, #2
X23 = 11111111 11111111 11111111 00000000 00000000 00000000 11011010 00000010 X6 = 00111111 11111111 11111111 11000000 00000000 00000000 00110110 10000000
• C-code equivalent : X6 = X23 >> 2;
• Question: LSL X6, X23, #2 ?
• What register gets modified?
• What does it contain after executing the LSL instruction?
LSL X6, X23, #2
X23 = 11111111 11111111 11111111 00000000 00000000 00000000 11011010 00000010 X6 = 11111111 11111111 11111100 00000000 00000000 00000011 01101000 00001000
• In shift operations Rm is always 0—shamt is 6-bit unsigned EECS 370 – Introduction to Computer Organization
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Shifting right by one bit -> divide by 2 Shifting left by one bit -> multiple by 2

Pseudo Instructions
• Instructions that use a shorthand “mnemonic” that expands to an assembly instruction
• Exception to the “1-1 correspondence between assembly and MC” rule
• Example:
• MOV X12, X2 // the contents of X2 copied to X12 — X2 unchanged
• This gets expanded to:
• ORR X12, XZR, X2
• What alternatives could we use instead of ORR? EECS 370 – Introduction to Computer Organization
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Pseudo Instructions
• Instructions that use a shorthand “mnemonic” that expands to an assembly instruction
• Exception to the “1-1 correspondence between assembly and MC” rule
• Example:
• MOV X12, X2 // the contents of X2 copied to X12 — X2 unchanged
• This gets expanded to:
• ORR X12, XZR, X2
• What alternatives could we use instead of ORR? – ADD X12, ZXR, X2 EECS 370 – Introduction to Computer Organization
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LEGv8 Assembly Example #1
• Show the C and LEGv8 assembly for extracting the value in bits 15:10 from a 64-bit integer variable
63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0
Assume the variable is in register X1
Wantthesebits
EECS 370 – Introduction to Computer Organization
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LEGv8 Assembly Example #1
• Show the C and LEGv8 assembly for extracting the value in bits 15:10 from a 64-bit integer variable
63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0
Assume the variable is in register X1
Wantthesebits
ARM LEGv8
LSR X1, X1, #10 ANDI X1, X1, #0x3F
C-code instructions
x = x >> 10; x = x & 0x3F
EECS 370 – Introduction to Computer Organization
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Logistics
• There are 4 videos for lecture 4
• L4_1 – ARM-ISA_Arithmetic-Logical_Instructions
• L4_2 – ARM-ISA_Memory-Instructions
• L4_3 – ARM-ISA_Memory-Instructions_Examples • L4_4 – C-to-Assembly
• There are two worksheets for lecture 4
1. LEGv8 Assembly
2. C to Assembly
EECS 370 – Introduction to Computer Organization
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L4_2 ARM-ISA_Memory- Instructions
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission

Learning Objectives
• Recognize the set of instructions for ARM Architecture (ISA) and be able to describe the operations and operands for instructions
• Ability to create simple ARM assembly programs, e.g., using mathematical, logic, and memory operations
EECS 370 – Introduction to Computer Organization
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Word vs Byte Addressing
• A word is a collection of bytes
• Exact size depends on architecture • in LC-2K and ARM, 4 bytes
• Double word is 8 bytes
• LC-2K is word addressable
• Each address refers to a particular word in memory
• Want to move forward one int? Increment address by one • Want move forward one char? Uhhh… no
• ARM (and most modern ISAs) is byte addressable
• Each address refers to a particular byte in memory
• Want to move forward one int? Increment address by four • Want to move forward one char? Increment address by one
EECS 370 – Introduction to Computer Organization
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LEGv8 Memory Instructions
• Employs base + displacement addressing mode • Base is a register
• Displacement is 9-bit immediate ±256 bytes
• Load signed word will sign extended to 64 bits • Load half and load byte will zero extend
EECS 370 – Introduction to Computer Organization
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D-Instruction fields • Data transfer
• opcode and op2 define data transfer operation • address is the ±256 bytes displacement
• Rn is the base register
• Rt is the destination (loads) or source (stores)
• More complicated modes are available in full ARMv8
EECS 370 – Introduction to Computer Organization
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LEGv8 Memory Instructions
• Registers are 64 bits wide
• But sometimes we want to deal with non-64-bit entities
• e.g. ints (32 bits), chars (8 bits)
• When we load smaller elements from memory, what do we set the other bits to?
• Option A: set to zero – LEGv8 instructionsLDURH, LDURB 0xF6 0x0000..00F6
• Option B: sign extend – LEGv8 instruction LDURSW
0xF6
0xFFFF..FFF6
EECS 370 – Introduction to Computer Organization
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Load Instruction Sizes
How much data is retrieved from memory at the given address?
• LDUR X3, [X4, #100]
• Load (unscaled) to register—retrieve a double word (64 bits) from address (X4+100)
• LDURH X3, [X4, #100]
• Load halfword (16 bits) from address (X4+100) to the low 16 bits of X3—top 48 bits
of X3 are set zero
• LDURB X3, [X4, #100]
• Load byte (8 bits) from address (X4+100) and put in the low 8 bits of X3—zero
extend the destination register X3 (top 56 bits)
• What about loading words?
• LDURSW X3, [X4, #100]
• retrieve a word (32 bits) from address (X4+100) and put in lower half of X3—top 32
bits of X3 are sign extended EECS 370 – Introduction to Computer Organization
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LEGv8 Data Transfer Instructions–Stores
• Store instructions are simpler—there is no sign/zero extension to consider • STUR X3, [X4, #100]
• Store (unscaled) register—write the double word (64 bits) in register X3 to the 8 bytes at address (X4+100)
• STURW X3, [X4, #100]
• Store word—write the word (32 bits) in the low 4 bytes of register X3 to the 2 bytes
at address (X4+100)
• STURH X3, [X4, #100]
• Store half word—write the half word (16 bits) in the low 2 bytes of register X3 to the 2 bytes at address (X4+100)
• STURB X3, [X4, #100]
• Store byte—write the least significant byte (8 bits) in register X3 to the byte at
address (X4+100)
EECS 370 – Introduction to Computer Organization
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Load Instruction in Action
• LDURB X3, [X4, #100] // load byte Retrieves 8-bit value from memory location (X4+100) and puts the result into X3. The other 56 most significant bits are 0—zero extended
10
10
2500
2600
X3 X4
Calculate address: 2500 + 100 = 2600
EECS 370 – Introduction to Computer Organization
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Load Instruction in Action – Example #2
• LDURSW X3, [X4, #100] // load signed word Retrieves 4-byte value from memory location (X4+100) and puts the result into X3 (sign extended)
Sign extend (0xE0295EFE) to
64 bits → 0x FFFFFFFFE0295EFE
FE
5E
29
E0
FFFF…5EFE
2504
X3 X4
2604 2605 2504 + 100 = 2604 2606 2607
Calculate address:
Example mixes decimal and hex to keep the numbers easy to read
Recall that E = 1110 and thus is treated as a negative 2’s complement number
EECS 370 – Introduction to Computer Organization
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Load Instruction in Action – Example #2
• LDURSW X3, [X4, #100] // load signed word Retrieves 4-byte value from memory location (X4+100) and puts the result into X3 (sign extended)
Sign extend (0xE0295EFE) to
64 bits → 0x FFFFFFFFE0295EFE
5E 2605 2504 + 100 = 2604 29 2606 E0 2607
Example mixes decimal and hex to keep the numbers easy to read
Recall that E = 1110 and thus is treated as a negative 2’s complement number
EECS 370 – Introduction to Computer Organization
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X3
X4 2504
FFFF…5EFE
Calculate address:
FE 2604

Big Endian vs. Little Endian
• Endian-ness: ordering of bytes within a word
• Little – increasing numeric significance with increasing memory addresses
• Big – The opposite, most significant byte first
• The Internet is big endian, x86 is little endian, LEG and ARMv8 can switch
• But in general assume little endian. (Figures from Wikipedia)
EECS 370 – Introduction to Computer Organization
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L4_3 ARM-ISA_Memory- Instructions_Examples
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission

Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR X4, [X5, #100] LDURB X3, [X5, #102] STUR X3, [X5, #100] STURB X4, [X5, #102]
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0) ARM LEGv8
Memory
(each location is 1 byte)
workspace start
0x02 100 0x03 101 0xFF 102 0x05 103 0xC2 104 0x06 105 0xFF 106 0xE5 107
little endian
LDUR LDURB STUR STURB
X4, [X5, #100] X3, [X5, #102] X3, [X5, #100] X4, [X5, #102]
register file
EECS 370 – Introduction to Computer Organization
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X3 X4

Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR X4, [X5, #100]
LDURB X3, [X5, #102] STUR X3, [X5, #100] STURB X4, [X5, #102]
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR X4, [X5, #100]
LDURB X3, [X5, #102]
STUR X3, [X5, #100] STURB X4, [X5, #102]
0x00000000000000FF
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0xFF
0x02
0x00
0x03
0x00
0xFF
0x00
0x05
0x00
0xC2
0x00
0x06
0x00
0xFF
0x00
0xE5
ARM LEGv8
LDUR X4, [X5, #100] LDURB X3, [X5, #102] STUR X3, [X5, #100] STURB X4, [X5, #102]
0x00000000000000FF
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #1
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0xFF
0x02
0x00
0x03
0x002
0xFF
0x00
0x05
0x00
0xC2
0x00
0x06
0x00
0xFF
0x00
0xE5
ARM LEGv8
LDUR X4, [X5, #100] LDURB X3, [X5, #102] STUR X3, [X5, #100] STURB X4, [X5, #102]
0x00000000000000FF
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Pause
The next example is a review of Lecture 4 worksheet 1. Pause, complete the worksheet, then proceed.
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #2
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR
LDURB
STURB
LDURSW X4,[X5,#100]
X4, [X5, #100] X3, [X5, #102] X3, [X5, #103]
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #2
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR
X4, [X5, #100]
LDURB
STURB
LDURSW X4,[X5,#100]
X3, [X5, #102] X3, [X5, #103]
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #2
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR
LDURB
X4, [X5, #100]
X3, [X5, #102]
STURB
LDURSW X4,[X5,#100]
X3, [X5, #103]
0x00000000000000FF
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #2
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR
LDURB
STURB
LDURSW X4,[X5,#100]
X4, [X5, #100]
X3, [X5, #102]
X3, [X5, #103]
0x00000000000000FF
0xE5FF06C205FF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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Example Code Sequence #2
• What is the final state of memory once you execute the following instruction
sequence? (assume X5 has the value of 0)
0x02
0x03
0xFF
0xFF
0x05
0xC2
0x06
0xFF
0xE5
ARM LEGv8
LDUR
LDURB
STURB
LDURSW X4, [X5, #100]
X4, [X5, #100]
X3, [X5, #102]
X3, [X5, #103]
0x00000000000000FF
0xFFFFFFFFFFFF0302
X3 X4
Memory
(each location is 1 byte)
workspace start
100 register file 101 102 103
104
105
106
107
little endian
EECS 370 – Introduction to Computer Organization
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L4_4 C-to-Assembly
EECS 370 – Introduction to Computer Organization – Fall 2020
EECS 370 – Introduction to Computer Organization – © Bill Arthur 1 The material in this presentation cannot be copied in any form without written permission

Learning Objectives
• Translate C-code statements to ARM assembly code
• Break down complex C-code instructions into a series of assembly operations • Map variables to registers
EECS 370 – Introduction to Computer Organization
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Converting C to assembly – Example #1
Write ARM assembly code for the following C expression (the array holds 64-bit integers):
Register to variable mapping
X1→a
X2→b
X3→i
X4→start address of
names
C-code instruction
a = b + names[ i ];
EECS 370 – Introduction to Computer Organization
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Converting C to assembly – Example #1
Write ARM assembly code for the following C expression (the array holds 64-bit integers):
ARM LEGv8
LSL X5, X3, #3 // calculate array offset i*8
ADD X6, X4, X5 // calculate address of names[i]
LDUR X7, [X6, #0] // load names[i]
ADD X1, X2, X7 // calculate b + names[i]
Register to variable mapping
X1→a
X2→b
X3→i
X4→start address of
names
C-code instruction
a = b + names[ i ];
EECS 370 – Introduction to Computer Organization
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Converting C to assembly – Example #2
Write ARM assembly code for the following C expression (assume an int is 4 bytes, unsigned char is 1 byte)
Register to variable mapping
X1→pointer to y
C-code instructions
struct { int a; unsigned char b, c; } y; y.a =y.b+y.c;
ARM LEGv8
LDURB X2, [X1, #4] // load y.b
LDURB X3, [X1, #5] // load y.c
ADD X4, X2, X3 // calculate y.b + y.c STURW X4, [X1, #0] // store y.a
See supplemental video for detailed explanation
How do you determine offsets for struct sub-fields? Next lecture will detail
EECS 370 – Introduction to Computer Organization
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