CS代写 CSE 141L: Introduction to Computer Architecture Lab

CSE 141L: Introduction to Computer Architecture Lab
Microprocessor Architecture & ISAs
Pat Pannuto, UC San SE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

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Logistics Update: Waitlists
• This is a big, hard project class
– Younowhavethefullscopeofthebig,hardproject
If you are considering dropping this course, please do so ASAP Please do not wait until the deadline [Friday!]
• If you are far back on the waitlist for 141, then please make room in 141L
• 141 will be offered next quarter
– (I’mteachingit)
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 2

Logistics Updates
• Project spec released for the quarter
– Skimthewholedocument
– Readthealltherequirements
– ReadMilestone1indepth
– Readthealltherequirementsagain
– Focusontheprogramstostart—whatmustyourprocessordo?
• Milestone 1 is due in 16 days
• Viva la Zoom
– FullremotethroughJan31atleast
– Remoteparticipationwillalwaysbeanoptionfor141Lthisquarter
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 3

Logistics Advice
• Use Version Control
– Thisishowyourgroupshouldshareacrossmachines
• Shouldn’t matter if you use Questa/ModelSim locally, CloudLabs, etc… – GoodfeedbackfromfolksusingVSCodetoedit&managecode
• Especially as it has built-in git support – Pleasenopublicrepositories!
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 4

ISA Design and Processor Architecture are Interrelated
• Your ISA expresses what your processor can do – Soyourarchitecturehastobeabletodoit!
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 5

The Instruction Set Architecture
• that part of the architecture that is visible to the programmer – availableinstructions(“opcodes”)
– numberandtypesofregisters
– instructionformats
– storageaccess,addressingmodes
– exceptionalconditions
• How do each of these affect your ISA design?
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Key questions to ask when designing an ISA
• operations
– how many?
– which ones? • operands
– how many?
– location
– how to specify?
• instruction format – size
destination operand
source operands
– how many formats?
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others
how does the computer know what 0001 0101 0001 0010 means?
add r5, r1, r2
Syntax choice Design choice
add r5, r1, r2 add r5, r1– r4 add [r1, r2], r5

Instruction Formats: What does each bit mean?
• Having many different instruction formats…
– complicatesdecoding
– usesmoreinstructionbits(tospecifytheformat)
– Couldallowustotakefulladvantageofavariable-lengthISAnotin141L!
VAX 11 instruction format
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

The MIPS Instruction Format
Register R-type Immediate I-type Jump J-type
the opcode tells the machine which format
6bits 5bits 5bits 5bits 5bits 6bits
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Example of instruction encoding:
6bits 5bits 5bits 5bits 5bits 6bits
Register R-type Immediate I-type Jump J-type
add r5, r1, r2
opcode=0, rs=1, rt=2, rd=5, sa=0, funct=32
000000 00001 00010 00101 00000 100000
00000000001000100010100000100000
0x00222420
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Accessing the Operands
add r5, r1, r2 • operands are generally in one of two places:
aka, what’s allowed to go here
– registers(32options) – memory(232locations)
• registers are
– easytospecify
– closetotheprocessor(fastaccess)
6bits 5bits 5bits 5bits 5bits 6bits
RegisterR-type
Immediate I-type rs
• the idea that we want to use registers whenever possible led to load-store architectures.
– normalarithmeticinstructionsonlyaccessregisters – onlyaccessmemorywithexplicitloadsandstores
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others
rs rt rd rt
Jump J-type

Poll Q: Accessing the Operands
There are typically two locations for operands: registers (internal storage – $t0, $a0) and memory. In each column we have which (reg or mem) is better.
Which row is correct?
Faster access
Fewer bits to specify
More locations
None of the above
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Q: How does all of this align with the project restrictions?
• [After class], re-read the restrictions with these slides in mind
• Design Question you must answer:
– HowwillyourISAencodeoperationsandoperands?
– Andhowwillthatimpacthowyourmachineoperates?
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 13

How Many Operands?
aka how many of these?
• Most instructions have three operands (e.g., z = x + y).
• Well-known ISAs specify 0-3 (explicit) operands per instruction.
• Operands can be specified implicitly or explicity.
add r5, r1, r2
r6, r7, r8, …
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Historically, many classes of ISAs have been explored, and trade off compactness, performance, and complexity
Accumulator
General Purpose Register
Load/Store:
# Operands
addABRc addARc
addRaRbRc load Ra Rb store Ra A
tos(N-1) ¬ tos(N) + tos(N-1) acc ¬ acc + mem[A]
mem[A] ¬ mem[B] + Rc mem[A] ¬ mem[A] + Rc
Ra ¬ Rb+Rc Ra ¬ mem[Rb] mem[A] ¬ Ra
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Comparing the Number of Instructions
Code sequence for C = A + B for four classes of instruction sets:
Stack Accumulator GP Register GP Register (register-memory) (load-store)
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Comparing the Number of Instructions
Push A Push B Add Pop C
Accumulator
GP Register (register-memory)
GP Register (load-store)
Code sequence for C = A + B for four classes of instruction sets:
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Comparing the Number of Instructions
PushA PushB Add Pop C
Accumulator
Load A Add B Store C
GP Register (register-memory)
GP Register (load-store)
Code sequence for C = A + B for four classes of instruction sets:
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Comparing the Number of Instructions
PushA PushB Add Pop C
Accumulator
Load A Add B Store C
GP Register (register-memory)
ADD C, A, B
GP Register (load-store)
Code sequence for C = A + B for four classes of instruction sets:
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Comparing the Number of Instructions
PushA PushB Add Pop C
Accumulator
Load A Add B Store C
GP Register (register-memory)
GP Register (load-store) Load R1,A LoadR2,B Add R3,R1,R2 Store C,R3
Code sequence for C = A + B for four classes of instruction sets:
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Exercise: Working through alternative ISAs [if time]
Stack Architecture
Accumulator
GPR GPR (Load-store)
Accumulator
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others
__ 12 3 4 5 __

Example: load-store (aka register-register) ISA
• load words from memory to reg file
• operate in reg file
• store results into memory from reg file
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

r3 8 r2 12 r1 1 r0 2
24 23 22 21 20
(beq r0, r1, 2) (sw r3, 0(r0))
(lw r2, 1(r0)) (add r1, r2, r3)
add r1, r2, r3
r3 8 r2 12 r1 20 r0 2
23 (beq r0, r1, 2)
Instruction Set Architecture
Assumptions
Ÿ8 bit ISA
Ÿ# of registers = 4 + PC (Program Counter) ŸMemory size = 64B
22 (sw r3, 0(r0)) 21 (lw r2, 1(r0)) 20 (add r1, r2, r3)
Before Register and Memory After Register and Memory

r3 8 r2 12 r1 20 r0 2
24 23 22 21 20
(beq r0, r1, 2) (sw r3, 0(r0))
(lw r2, 1(r0)) (add r1, r2, r3)
lw r2, 1(r0)
r3 8 r2 7 r1 20 r0 2
23 (beq r0, r1, 2)
Instruction Set Architecture
Assumptions
Ÿ8 bit ISA
Ÿ# of registers = 4 + PC (Program Counter) ŸMemory size = 64B
22 (sw r3, 0(r0)) 21 (lw r2, 1(r0)) 20 (add r1, r2, r3)
Before Register and Memory After Register and Memory

r3 8 r2 7 r1 20 r0 2
24 23 22 21 20
(beq r0, r1, 2) (sw r3, 0(r0))
(lw r2, 1(r0)) (add r1, r2, r3)
sw r3, 0(r0)
r3 8 r2 7 r1 20 r0 2
23 (beq r0, r1, 2)
Instruction Set Architecture
Assumptions
Ÿ8 bit ISA
Ÿ# of registers = 4 + PC (Program Counter) ŸMemory size = 64B
22 (sw r3, 0(r0)) 21 (lw r2, 1(r0)) 20 (add r1, r2, r3)
Before Register and Memory After Register and Memory

r3 8 r2 7 r1 20 r0 2
24 23 22 21 20
(beq r0, r1, 2) (sw r3, 0(r0))
(lw r2, 1(r0)) (add r1, r2, r3)
beq r0, r1, 2
r3 8 r2 7 r1 20 r0 2
23 (beq r0, r1, 2)
Instruction Set Architecture
Assumptions
Ÿ8 bit ISA
Ÿ# of registers = 4 + PC (Program Counter) ŸMemory size = 64B
22 (sw r3, 0(r0)) 21 (lw r2, 1(r0)) 20 (add r1, r2, r3)
Before Register and Memory After Register and Memory

r3 8 r2 7 r1 20 r0 0
24 23 22 21 20
(beq r0, r1, 2) (sw r3, 0(r0))
(lw r2, 1(r0)) (add r1, r2, r3)
r3 8 r2 7 r1 20 r0 0
23 (beq r0, r1, 2)
Instruction Set Architecture
Assumptions
Ÿ8 bit ISA
Ÿ# of registers = 4 + PC (Program Counter) ŸMemory size = 64B
22 (sw r3, 0(r0)) 21 (lw r2, 1(r0)) 20 (add r1, r2, r3)
Before Register and Memory After Register and Memory

Addressing Modes
aka: how do we specify the operand we want?
• Register direct
• Immediate (literal)
• Direct (absolute)
• Register indirect
• Base+Displacement
• Base+Index
• Scaled Index
• Autoincrement
• Autodecrement
• Memory Indirect
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others
#25 M[10000]
M[R3 + 10000]
M[R3 + R4]
M[R3 + R4*d + 10000] M[R3++]
M[ M[R3] ]

What does memory look like anyway?
• Viewed as a large, single-dimension array, with an address.
• A memory address is an index into the array
• “Byte addressing” means that the index (address) points to a byte of memory.
0 1 2 3 4 5 6 …
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

Which kinds of things can a processor do? • arithmetic
– add,subtract,multiply,divide • logical
– and,or,shiftleft,shiftright • data transfer
– loadword,storeword
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

“Control Flow” describes how programs execute
• Procedure call (jump subroutine)
• Conditional Branch
– Usedtoimplement,forexample,if-then-elselogic,loops,etc.
• Control flow must specify two things
– Conditionunderwhichthejumporbranchistaken
– Iftake,thelocationtoreadthenextinstructionfrom(“target”)
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

How do you specify the destination of a branch/jump?
• Unconditional jumps may go long distances – Functioncalls,returns,…
• Studies show that almost all conditional branches go short distances from the current program counter
– loops,if-then-else,…
• A relative address requires (many) fewer bits than an absolute address
– e.g.,beq$1,$2,100 => if($1==$2): PC=(PC+4)+100*4
CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others

MIPS in one slide
MIPS operands
32 registers
$s0-$s7, $t0-$t9, $zero, $a0-$a3, $v0-$v1, $gp, $fp, $sp, $ra, $at
Fast locations for data. In MIPS, data must be in registers to perform arithmetic. MIPS register $zero always equals 0. Register $at is reserved for the assembler to handle large constants.
230 memory words
Memory[0],
Memory[4], …, Memory[4294967292]
Accessed only by data transfer instructions. MIPS uses byte addresses, so
sequential words differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls.
MIPS assembly language
Instruction
Arithmetic
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands; data in registers
sub tr act
sub $s1, $s2, $s3
$s1 = $s2 – $s3
Three operands; data in registers
add immediate
addi $s1, $s2, 100
$s1 = $s2 + 100
Used to add constants
Data transfer
lw $s1,100($s2)
$s1 =Memory[$s2+100]
Word from memory to register
store word
sw $s1,100($s2)
Memory[$s2+100] = $s1
Word from register to memory
lb $s1,100($s2)
$s1 =Memory[$s2+100]
Byte from memory to register
store byte
sb $s1,100($s2)
Memory[$s2+100] = $s1
Byte from register to memory
loadupper i mm e di ate
lui $s1, 100
$s1 = 100 * 2 16
Loads constant in upper 16 bits
Conditional branch
branch on equal
beq $s1, $s2, 25
if ($s1 == $s2 ) go to PC + 4 + 100
Equal test; PC-relative branch
branch on not equal bne $s1, $s2, 25
if ($s1 != $s2 ) go to PC + 4 + 100
Not equal test; PC-relative
set on less than
slt $s1, $s2, $s3
if ($s2 < $s3) $s1 = 1; else$s1 = 0 Compare less than; for beq, bne set less than i mm e di ate slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else$s1 = 0 Compare less than constant Uncondi- tional jump go to 10000 Jump to target address jump register For switch, procedure return jump and link $ra = PC + 4; go to 10000 For procedure call CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others More Information? More Machine Types? • 141 will talk some about other machine types – The141textbookgoesintomoredetail • I will post a collection of slides and resources from others in Canvas • Many additional resources online CSE 141L CC BY-NC-ND Pat Pannuto – Content derived from materials from , , , and others 35 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com