Virtual Memory
Review (1/2)
°Caches are NOT mandatory: • Processor performs arithmetic
• Memory stores data
• Caches simply make things go faster
°Each level of memory hierarchy is just a subset of next higher level
°Caches speed up due to temporal locality: store data used recently
°Block size > 1 word speeds up due to spatial locality: store words adjacent to the ones used recently
Review (2/2)
°Cache design choices:
• size of cache: speed v. capacity
• direct-mapped v. associative
• for N-way set assoc: choice of N • block replacement policy
• 2nd level cache?
• Write through v. write back?
°Use performance model to pick between choices, depending on programs, technology, budget, …
Another View of the Memory Hierarchy
Regs
Instr. Operands Blocks
Upper Level
Faster
Thus far{
Blocks
Cache
L2 Cache
Next: { Virtual Memory
Pages Files
Memory
Disk
Larger
Lower Level
Tape
Virtual Memory
°If Principle of Locality allows caches to offer (usually) speed of cache memory with size of DRAM memory, then recursively why not use at next level to give speed of DRAM memory, size of Disk memory?
°Called “Virtual Memory”
• Also allows OS to share memory, protect
programs from each other
• Today, more important for protection vs. just another level of memory hierarchy
• Historically, it predates caches
Virtual to Physical Addr. Translation
Physical memory (incl. caches)
Program operates in its virtual address space
HW mapping
virtual address (inst. fetch load, store)
physical address (inst. fetch load, store)
°Each program operates in its own virtual address space; ~only program running
°Each “process” is protected from the other
°OS can decide where each goes in memory
°Hardware (HW) provides virtual -> physical mapping
Simple Example: Base and Bound Reg
¥
$base+
$bound
$base
Enough space for User D, but discontinuous (“fragmentation problem”)
°Want discontinuous mapping
°Also want Process size >> memory size
°Base/Bound Addition not enough!
=> use Indirection!
User C
User B
User A
OS
0
Mapping Virtual Memory to Physical Memory
°Divide into equal sized chunks (about 4KB)
¥Virtual Memory
Stack
Heap
Static
Code
°Any chunk of Virtual Memory assigned to any chunk of Physical Memory (“page”)
64 MB
Physical Memory
0
0
Virtual Memory Mapping Function
°Cannot have simple function to predict arbitrary mapping
°Use table lookup of mappings Virtual address:
°Use table lookup (“Page Table”) for mappings: Page number is index
°Virtual Memory Mapping Function
• Physical Offset = Virtual Offset
• Physical Page Number
= PageTable[Virtual Page Number]
(P.P.N. also called “Page Frame”)
Page Number
Offset
Page Table
° A page table is an operating system structure which contains the mapping of virtual addresses to physical locations
• There are several different ways, all up to the operating system, to keep this data around
°Each process running in the operating system has its own page table
• “State” of process is PC, all registers, plus page table
• OS changes page tables by changing contents of Page Table Base Register
Address Mapping: Page Table
Virtual Address:
(actually concatenation)
page no.
offset
Page Table
Page Table Base Reg
…
V
Val -id
A.R.
P. P. A.
Access Physical
Page Address
V
Rights
P. P. A.
V
A.R.
P. P. A.
.A.R. …
||
index into page table
Physical Memory Address
Page Table located in physical memory
Page Table Continued
°Page Table Entry (PTE) Contains either Physical Page Number or indication not in Main Memory (Valid = 0)
•OS maps to disk if Not Valid (V = 0) …
Val -id
Access Rights
Physical Page Number
V
V
A.R.
P. P.N.
A.R.
…
P. P. N.
Page Table
P.T.E.
°If valid, also check if have permission to use page: Access Rights (A.R.) may be Read Only, Read/Write, Executable
Notes on Page Table
°Solves Fragmentation problem: all chunks same size, so all holes can be used
°OS must reserve “Swap Space” on disk for each process
°To grow a process, ask Operating System • If unused pages, OS uses them first
• If not, OS swaps some old pages to disk
• (Least Recently Used to pick pages to swap)
°Each process has own Page Table
°Will add details, but Page Table is essence of Virtual Memory
Analogy
°Book title like virtual address °Library of Congress call number like
physical address
°Card catalogue like page table,
mapping from book title to call number
°On card for book, in local library vs. in another branch like valid bit indicating in main memory vs. on disk
°On card, available for 2-hour in library use (vs. 2-week checkout) like access rights
Comparing the 2 levels of hierarchy
°Cache Version °Block (or Line) °Miss
°Block Size: 32-64B
Virtual Memory vers.
Page
Page Fault
Page Size: 4K-8KB Fully Associative
Least Recently Used (LRU)
Write Back
°Placement:
Direct Mapped,
N-way Set Associative
°Replacement: LRU or Random
°Write Thru or Back
Virtual Memory Problem #1
°Map every address Þ 1 indirection via Page Table in memory per virtual address Þ 1 virtual memory access = 2 physical memory accesses Þ SLOW!
°Observation: since locality in pages of data, there must be locality in virtual address translations of those pages
°Since small is fast, why not use a small cache of virtual to physical address translations to make translation fast?
°For historical reasons, cache is called a Translation Lookaside Buffer, or TLB
Translation Look-Aside Buffers
•TLBs usually small, typically 128 – 256 entries • Like any other cache, the TLB can be direct
mapped, set associative, or fully associative
hit miss
Trans- lation
VA Processor
PA miss hit
TLB Lookup
Cache
Main Memory
data
Typical TLB Format
Virtual Address
Physical Address
Dirty
Ref Valid
Access Rights
• TLB just a cache on the page table mappings
• TLB access time comparable to cache (much less than main memory access time)
• Dirty: since use write back, need to know whether or not to write page to disk when replaced
•Ref: Used to help calculate LRU page on replacement. Cleared by OS periodically, then checked to see if page was referenced
What if not in TLB?
°Option 1: Hardware checks page table and loads new Page Table Entry into TLB
°Option 2: Hardware traps to OS, up to OS to decide what to do
°MIPS follows Option 2: Hardware knows nothing about page table
TLB Miss (simplified format)
°If the address is not in the TLB, MIPS traps to the operating system
• When in the operating system, we don’t do translation (turn off virtual memory)
°The operating system knows which program caused the TLB fault, page fault, and knows what virtual address was requested
• So we look the data up in the page table valid virtual physical
1
2
9
If the data is in memory
°We simply add the entry to the TLB, evicting an old entry from the TLB
valid virtual physical
1
7
32
1
2
9
What if the data is on disk?
°We load the page off the disk into a free block of memory, using a DMA transfer
• Meantime we switch to some other process waiting to be run
°When the DMA is complete, we get an interrupt and update the process’s page table
• So when we switch back to the task, the desired data will be in memory
What if we don’t have enough memory?
°We chose some other page belonging to a program and transfer it onto the disk if it is dirty
• If clean (disk copy is up-to-date), just overwrite that data in memory
• We chose the page to evict based on replacement policy (e.g., LRU)
°And update that program’s page table to reflect the fact that its memory moved somewhere else
Virtual Memory Problem #2
°Not enough physical memory!
• Only, say, 64 MB of physical memory
• N processes, each 4 GB (232 B) of virtual memory!
• Could have 1K virtual pages/physical page! °Spatial Locality to the rescue
• Each page is 4 KB, lots of nearby references °No matter how big program is, at any time
only accessing a few pages
• “Working Set”: recently used pages
Virtual Memory Problem #3
°Page Table too big!
• 4GB Virtual Memory ÷ 4 KB page
Þ ~ 1 million Page Table Entries
Þ 4 MB just for Page Table for 1 process, 25 processes Þ 100 MB for Page Tables!
°Variety of solutions to tradeoff memory size of mapping function for slower when miss TLB
• Make TLB large enough, highly associative so rarely miss on address translation
2-level Page Table
2nd Level Page Tables
Physical Memory
Virtual Memory
Super Page Table
¥
Stack
Heap
Static
Code
64 MB
…
0
0
Page Table Shrink :
°Single Page Table
20 bits 12 bits
°Multilevel Page Table
Page Number
Offset
Super Page No.
Page Number
Offset
10 bits 10 bits 12 bits
°Only have second level page table for valid entries of super level page table
Space Savings for Multi-Level Page Table
°If only 10% of entries of Super Page Table have valid entries, then total mapping size is roughly 1/10-th of single level page table
• Exercise 7.35 explores exact size
Things to Remember 1/2
°Apply Principle of Locality Recursively
°Reduce Miss Penalty? add a (L2) cache
°Manage memory to disk? Treat as cache • Originally included protection as bonus,
now protection is critical
• Use Page Table of mappings vs. tag/data in cache
°Virtual memory to Physical Memory Translation too slow?
• Add a cache of Virtual to Physical Address Translations, called a TLB
Things to Remember 2/2
°Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound
°Spatial and Temporal Locality means Working Set of Pages is all that must be in memory for process to run fairly well
°TLB to reduce performance cost of VM
°Need more compact representation to reduce memory size cost of simple 1-level page table (especially when 32-bit address Þ 64-bit address) . Hence, a 2-level page table