CAMOSUN COLLEGE E161:E.11
Department of Electronics 2020/10 Rev 4.2
ECET 161 Lab Exercise
Exercise 11
Multiplexer design in VHDL
Reference: Handout
Lab preparation required: Read sec. 6.3.
Design a (4-Bit) 2 to 1 Multiplexer.
Reference: Handout
Lab preparation required: Read sec. 6.3.
Design a (4-Bit) 2 to 1 Multiplexer.
REQUIRED:
• VHDL Design screen shot for a (4-Bit) 2 to 1 Multiplexer.
• Graphical screen shot of the final circuit design.
• Construct the circuit and test using 8 bits of your dip switch.
• Picture of your wiring
•
•
• PROCEDURE:
•
Construct a (4-Bit) 2 to 1 Multiplexer. Use the 7 segment decoder symbol you created from lab 10. Include the lab 10 files as part of the library files for the lab 11 project. From your VHDL file for the multiplexer in Lab 11 create a different symbol file. Connect the 7 segment decoder file and the multiplexer symbols in the top level Graphical Design File.
The multiplexer allows more than one digit to be displayed on the 4 digit display. The onboard 12 MHz clock will be used to test the circuit. When the clock signal is high digit 3 (MSD) will display the value from bits 7 to 4 of the dip switch. When the clock signal is low digit 4 (LSD) will display the value from bits 3 to 0 of the dip switch. Use an inverter (NOT symbol) to connect the clock to LSDenable.
Requirement Specification:
Two HEX numbers are to be multiplexed to two digits of a 4 digit, common cathode, LED display, with the overall circuit based on the block diagram of Figure 1 and the cyc1000Layout doc.
Use the following pin definitions:
• Bits for the MSD (most significant digit) are to be entered as bits 1 to 4 of an 8-bit DIP switch.
• Bits for the LSD are to be entered as bits 5 to 8 of the DIP switch.
• Connect the “clock” to the 12MHz system clock.
• The transistors are used as simple switches in this design.
2N3904
470ohm
R1
2N3904
470ohm
R2
LTC-4727JR
4
4
FPGA
+
Decoder
HEX TO 7 SEG
Multiplexer
8-bit DIP Switch
(MSD)
(LSD)
Digit 3/MSD Cathode
Digit 4/LSD Cathode
12 MHz System Clock
(4-Bit) 2 to 1
Inverter is part of the FPGA
LSD ENABLE
MSD ENABLE
MSD/LSD Enable
Divide by
128k
2N3904
470ohm
R1
2N3904
470ohm
R2
LTC-4727JR
4
4
FPGA
+
Decoder
HEX TO 7 SEG
Multiplexer
8-bit DIP Switch
(MSD)
(LSD)
Digit 3/MSD Cathode
Digit 4/LSD Cathode
12 MHz System Clock
(4-Bit) 2 to 1
Inverter is part of the FPGA
LSD ENABLE
MSD ENABLE
MSD/LSD Enable
Divide by
128k
Optional Challenge: Multiplex all four digits.
Pin Plan for this Lab:
VHDL Design screen shot for a (4-Bit) 2 to 1 Multiplexer:
Graphical screen shot of the final circuit design:
Picture of your wiring: