Computer architecture: interconnects
Dr Fei Xia and Dr Alex Bystrov
Let’s play mash-up
Copyright By PowCoder代写 加微信 powcoder
Architecture topics, EEE8087 1
Communication requirements are unpredictable at design time. We need systematic arrangements of interconnects to serve such needs.
Computer interconnect • A functional picture
– Interconnectsystemislikeasortofmemorythrough which all active units communicate
Interconnection network
28/10/20 Architecture topics, EEE8087 2
Interconnect design affects real-time operations
• Multi-bit interconnects can suffer from skew – Importantforreal-timesystemdesign
– Partsofthedataarriveearlierthanotherparts
– Needstobecarefullyconsidered
during the design process
28/10/20 Architecture topics, EEE8087 3
Shared bus
• A number of wires shared between multiple units for data communication
– Atanytime,onlyapairoftheunitsusethesewires
– Arbitrationisusedto determine who gets to use the bus when
– Potentialbottleneck
– Verypopularincurrent systems
Architecture topics, EEE8087 4
Bus example: ARM AMBA
• Advanced microprocessor bus architecture – Dividedintotwoparts
– Fortwodifferenttypesofdevices
Adv. Peripheral Bus (APB)
Adv. High-performance Bus (AHB)
Timer Keypad PIO
Low Power Non-pipelined Simple Interface
Architecture topics, EEE8087
High Performance ARM processor
High Bandwidth External Memory Interface
High Performance Pipelined
Burst Support Multiple Bus Masters
APB Bridge
High-bandwidth on-chip RAM
DMA Bus Master
AHB pipelining
• AHB provides transaction pipelining – Increasesbusbandwidth
Separateaddressand data buses allows the address and data phases of write/read to be pipelined
Whenonetransaction is in the address phase, the previous one may be moving data
Architecture topics, EEE8087 6
Parallelism?
• No parallelism between multiple cores because they share the same multiplexes
28/10/20 Architecture topics, EEE8087 7
Improved version • AXI4 AMBA standard
– Multi-layeringallowsthewriteand read/address multiplexes to
be in different layers
– Canhaveoneactivemuxper layer at any one time
– Canhaveonereadingatthe same time as another
writing between two different masters and two different slaves
Architecture topics, EEE8087 8
Point to point
• Ideal situation
– Everyinterconnectsystemtriestofunctionallydothis – Actuallydoingthisisnotrealisticinmostsituations
– Veryhighcost(O(N2)numberofdirectlinks)
– Notfeasiblefor2Dchiplayout
28/10/20 Architecture topics, EEE8087
• Switches at the intersecting points programmably link pairs of communicating units
• Parallelism among non-conflicting pairs of units (those who do not share an intersection)
• High cost O(N2)
– NotscalabletolargeN
• Used in real examples (core-to-cache networks)
7 6 5 4 3 2 1 0
28/10/20 Architecture topics, EEE8087
Networks on chip (NoC)
• Imagine running a computer network on a single chip
– Packet-baseddatatransfer
– Networkprotocols
– Widelyused
– ScalableO(N)
– Complicatedsystemforrouting and arbitration, although simpler routing protocols than off-chip networks
– FIFObufferseverywhere
28/10/20 Architecture topics, EEE8087 11
Example: SpiNNaker
Architecture topics, EEE8087
Neuralmorphic computing based on the spiking neural network model
Brain simulation is the most prominent application
Million-core supercomputer based on a NoC interconnect fabric 12
• You are asked to design the interconnect for a 16-core system. The cores are organized in four groups (with 4 cores each), each with a shared L3 cache and main memory. What type of interconnect would suit such a system? Explain with appropriate reasoning.
– Thereisnoone‘best’answer,youhavetoconsider your use case scenarios.
– Whenfacedwithsuchaquestion,youranswerneeds to be convincingly argued with internal consistency
28/10/20 Architecture topics, EEE8087 13
程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com