1 Àà SRAM ½Ó¿Ú˵Ã÷
´óÈüÒªÇó myCPU ·âװΪ AXI ½Ó¿Ú£¬¾ßÌåʵÏÖÓÐÒÔÏÂÁ½ÖÖ·½·¨:
(1) ×Ô¶¨ÒåÄÚ²¿È¡Ö¸¡¢·Ã´æÓë AXI ½Ó¿ÚµÄ½»»¥Ðźţ¬È»ºó·âװΪ AXI ½Ó¿Ú¡£
(2) ×Ô¶¨ÒåÄÚ²¿È¡Ö¸¡¢·Ã´æÓëÆäËû½Ó¿ÚµÄ½»»¥ÐÁ¹þ£¬ÔÙʹÓÃת»»ÇÅת»»Îª AXI ½Ó¿Ú¡£±ÈÈçÄÚ²¿ÊµÏÖΪÀà SRAM ½Ó¿Ú£¬Ê¹Óùٷ½ÌṩµÄÀà SRAM ת AXI µÄÇÅÀ´×ª½Ó¡£
ÎÒÃÇÍƼö·½·¨Ò»£¬ÕâÑù¿ÉÒÔ×Ô¼º¶Ô½Ó¿Ú½øÐÐÉè¼Æ£¬ÒÔÌáÉý·Ã´æÐÔÄÜ¡£´óÈüÌṩµÄÀà SRAM ת AXI µÄÇÅ´úÂë²Î ¿¼±¾Ä¿Â¼Ï嵀 cpu_axi_interface.v£¬Ð§ÂÊÆ«µÍ£¬ÇÒ²»Ö§³Ö burst ´«Êä¡£
ÔÚ SoC_SRAM_Lite ÖУ¬myCPU ½Ó¿ÚÊÇ SRAM ½Ó¿Ú£¬Êý¾Ý·ÃÎʶ¼Êǵ¥ÖÜÆÚ·µ»ØµÄ¡£½Ó¿Ú¼òµ¥£¬È´Ò²ÏÞÖÆÁË myCPU µÄƵÂÊ¡£myCPU ƵÂʲ»Äܳ¬¹ý RAM µÄ¶ÁдƵÂÊ¡£
ʵ¼Ê CPU ƵÂÊÊÇÆÕ±é¸ßÓë´æ´¢Æ÷¶ÁдƵÂʵģ¬ËùÒԺܶàʱºò·ÃÎʶ¼ÊÇÐèÒª¶à¸ö CPU ÖÜÆÚ²ÅÄÜ·µ»ØµÄ¡£Îª´ËΪ SRAM ½Ó¿ÚÔö¼ÓµØÖ·´«ÊäÎÕÊÖÐźŠaddr_ok ºÍÊý¾Ý´«ÊäÎÕÊÖÐźŠdata_ok£¬ÕâÑù¾Í¿ÉÒÔʵÏÖÈÎÒâÖÜÆÚ·µ»ØÊý¾ÝÁË£¬ ³ÆΪÀà SRAM ½Ó¿Ú¡£Ï±íչʾÁËÀà SRAM µÄ½Ó¿ÚÐźţ¬Óë 2017 Äê´óÈüÌṩµÄÀà SRAM ½Ó¿Ú¶¨ÒåÉÔÓв»Í¬¡£
±í 1-1 Àà SRAM ½Ó¿ÚÐźÅ
ÐźÅ
λ¿í
·½Ïò
¹¦ÄÜ
clk
1
input
ʱÖÓ
req
1
master¡ª>slave
ÇëÇóÐźţ¬Îª 1 ʱÓжÁдÇëÇó£¬Îª 0 ʱÎÞ¶ÁдÇëÇó
wr
1
master¡ª>slave
¸Ã´ÎÇëÇóÊÇд
size
[1:0]
master¡ª>slave
¸Ã´ÎÇëÇó´«ÊäµÄ×Ö½ÚÊý£¬0: 1byte;1: 2bytes;2: 4bytes¡£
addr
[31:0]
master¡ª>slave
¸Ã´ÎÇëÇóµÄµØÖ·
wdata
[31:0]
master¡ª>slave
¸Ã´ÎÇëÇóµÄдÊý¾Ý
addr_ok
1
slave¡ª>master
¸Ã´ÎÇëÇóµÄµØÖ·´«Êä OK£¬¶Á:µØÖ·±»½ÓÊÕ;д:µØÖ·ºÍÊý¾Ý±»½Ó ÊÕ
data_ok
1
slave¡ª>master
¸Ã´ÎÇëÇóµÄÊý¾Ý´«Êä OK£¬¶Á:Êý¾Ý·µ»Ø;д:Êý¾ÝдÈëÍê³É¡£
rdata
[31:0]
slave¡ª>master
¸Ã´ÎÇëÇ󷵻صĶÁÊý¾Ý¡£
ÐèҪעÒ⣬²»Í¬ÓÚ SRAM ½Ó¿Ú£¬Àà SRAM µÄµØÖ·ÐźÅ(addr)ÊÇ×Ö½ÚÑ°Ö·µÄ£¬ÆäÖ¸Ïò¶ÁдÊý¾ÝµÄ ×îµÍÓÐЧλ¡£Òò¶ø addr ºÍ size ÐźÅÐèÅäºÏʹÓ㬲»Ö§³Ö 3 ×Ö½Ú¶Áд£¬ÓÐÇÒÖ»ÓÐÒÔÏÂÀàÐÍ×éºÏ¡£
1. addr[1:0]=2¡¯b00 ʱ£¬¿ÉÄܵÄ×éºÏ: size=2¡¯b00, size=2¡¯b01, size=4¡¯b10,
2. addr[1:0]=2¡¯b01 ʱ£¬¿ÉÄܵÄ×éºÏ: size=2¡¯b00
3. addr[1:0]=2¡¯b10 ʱ£¬¿ÉÄܵÄ×éºÏ: size=2¡¯b00, size=2¡¯b01
4. addr[1:0]=2¡¯b11 ʱ£¬¿ÉÄܵÄ×éºÏ:
size=2¡¯b00
wdata ºÍ rdata ÓÐЧÊý¾Ý×Ö½ÚÒ²Óë size Óë addr[1:0]ÐźŶÔÓ¦£¬Ð¡Î²¶ËÏ£¬ÅäºÏÈçÏÂ: 1
±í 1-2 Àà SRAM ½Ó¿ÚÊý¾ÝÓÐЧÇé¿ö
data[31:24]
data[23:16]
data[15:8]
data[7:0]
size=2¡¯b00,addr=2¡¯b00
–
–
–
valid
size=2¡¯b00,addr=2¡¯b01
–
–
valid
–
size=2¡¯b00,addr=2¡¯b10
–
valid
–
–
size=2¡¯b00,addr=2¡¯b11
valid
–
–
–
size=2¡¯b01,addr=2¡¯b00
–
–
valid
valid
size=2¡¯b01,addr=2¡¯b10
valid
valid
–
–
size=2¡¯b10,addr=2¡¯b00
valid
valid
valid
valid
Æä¶ÁÒ»¸ö°ë×ÖµÄʱÐòÂß¼ÈçÏÂ:
clk
req
wr size
addr
addr_ok data_ok
rdata
µØÖ·ÎÕÊֳɹ¦
Êý¾ÝÎÕÊֳɹ¦
2’b01
addr(A)
addr(A)µÍ2λΪ2’b10
rdata(A)µÄ[31:16]Ϊ ¶Á³ö µÄÓÐЧ Êý¾Ý
data(A)
µØÖ·ÎÕÊÖʧ°Üx1
Êý¾ÝÎÕÊÖʧ°Üx2
ͼ 1-1 Àà SRAM ½Ó¿ÚÒ»´Î¶ÁʱÐò Æäдһ¸ö×Ö½ÚµÄʱÐòÂß¼ÈçÏÂ:
2
clk
req
wr size
addr wdata addr_ok
data_ok
rdata
addr(B)µÍ2λΪ2’b01
wdata(B)µÄ[15:8]Ϊ ´ýд µÄÓÐЧ Êý¾Ý
µØÖ·ÎÕÊֳɹ¦
Êý¾ÝÎÕÊֳɹ¦
2’b00
addr(B)
data(B)
µØÖ·ÎÕÊÖʧ°Üx1
Êý¾ÝÎÕÊÖʧ°Üx2
ͼ 1-2 Àà SRAM ½Ó¿ÚÒ»´ÎдʱÐò ÆäÁ¬Ðøд¶ÁµÄµÄʱÐòÂß¼ÈçÏ¡£¿ÉÒÔ¿´µ½Á¬Ðøд¶Áʱ£¬slave ·µ»ØµÄ data_ok Ó¦¸Ã˳Ðò·µ»ØµÄ£¬
¾ÍÊÇÏÈдºó¶Á£¬±ØÐëÏÈ·µ»ØдµÄ data_ok£¬ÔÙ·µ»Ø¶ÁµÄ data_ok¡£ÁíÍ⣬ÔÚÒ»´Î´«Êä addr_ok ÎÕÊÖºó data_ok ÎÕÊÖÇ°£¬ÊÇÓпÉÄܳöÏֺü¸´ÎÆäËûÇëÇóµÄ addr_ok ÎÕÊֵģ¬Ò²¾ÍÊÇ¿ÉÄܳöÏÖÎÕÊÖÐòÁÐ addr_ok->addr_ok->addr_ok->addr_ok->…->data_ok£¬master ¶Ë±ÜÃâÕâÒ»Çé¿öµÄ³öÏÖ¿ÉÒÔͨ¹ýÀµÍ req Ðźţ¬slave ±ÜÃâÕâÒ»Çé¿öµÄ³öÏÖ¿ÉÒÔͨ¹ýÀµÍ addr_ok À´±ÜÃâ¡£
¶ÁµØÖ·ÎÕÊֳɹ¦ дµØÖ·ÎÕÊֳɹ¦
¶ÁÊý¾ÝÎÕÊֳɹ¦ дÊý¾ÝÎÕÊֳɹ¦
clk
req
wr size
addr
wdata addr_ok
data_ok rdata
2’b01
addr(A)
data(A)
2’b00
addr(B)
дÊý¾ÝÎÕÊÖʧ°Üx2
ͼ 1-3 Àà SRAM ½Ó¿ÚÁ¬Ðøд¶ÁʱÐò 3
data(B)
ÆäÁ¬Ðø¶ÁдµÄʱÐòÂß¼ÈçÏ¡£´ÓÏÂͼ¿ÉÒÔ¿´µ½£¬µ± addr_ok ºÍ data_ok ͬʱÓÐЧʱ£¬ÊÇÕë¶Ô²»Í¬ ÇëÇóµÄÎÕÊÖ:addr_ok Êǵ±Ç°´«ÊäµÄµØÖ·ÎÕÊֳɹ¦£¬data_ok ÊÇ֮ǰ´«ÊäµÄÊý¾ÝÎÕÊֳɹ¦¡£ÁíÍ⣬ͼ ÖжÁÊý¾ÝÎÕÊֳɹ¦ÊÇÓпÉÄÜÔÚдµØÖ·ÎÕÊֳɹ¦Ç°Íê³ÉµÄ¡£
¶ÁµØÖ·ÎÕÊֳɹ¦
2’b01
addr(A)
дµØÖ·ÎÕÊֳɹ¦ дÊý¾ÝÎÕÊֳɹ¦ ¶ÁÊý¾ÝÎÕÊֳɹ¦
clk
req
wr size
addr
wdata addr_ok
data_ok rdata
2’b00
addr(B)
data(B)
data(A)
¶ÁÊý¾ÝÎÕÊÖʧ°Üx2
ͼ 1-4 Àà SRAM ½Ó¿ÚÁ¬Ðø¶ÁдʱÐò
4