程序代写代做代考 chain prolog algorithm mips scheme data structure cache MIPS® Architecture For Programmers Volume III: The MIPS32® and microMIPS32TM Privileged Resource Architecture

程序代写 CS代考 / Algorithm算法代写代考, data structure, MIPS汇编代写代考, Prolog代写代考, Scheme代写代考

MIPS® Architecture For Programmers Volume III: The MIPS32® and microMIPS32TM Privileged Resource Architecture
Document Number: MD00090 Revision 3.12
April 28, 2011
MIPS Technologies, Inc.
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Contents
Chapter 1: About This Book …………………………………………………………………………………………………. 11
1.1: Typographical Conventions ……………………………………………………………………………………………………….. 11 1.1.1: Italic Text………………………………………………………………………………………………………………………… 11 1.1.2: Bold Text………………………………………………………………………………………………………………………… 12 1.1.3: Courier Text ……………………………………………………………………………………………………………………. 12
1.2: UNPREDICTABLE and UNDEFINED …………………………………………………………………………………………. 12 1.2.1: UNPREDICTABLE…………………………………………………………………………………………………………… 12 1.2.2: UNDEFINED …………………………………………………………………………………………………………………… 13 1.2.3: UNSTABLE …………………………………………………………………………………………………………………….. 13
1.3: Special Symbols in Pseudocode Notation ……………………………………………………………………………………. 13 1.4: For More Information ………………………………………………………………………………………………………………… 16
Chapter 2: The MIPS32 and microMIPS32 Privileged Resource Architecture ………………………….. 17
2.1: Introduction……………………………………………………………………………………………………………………………… 17 2.2: The MIPS Coprocessor Model …………………………………………………………………………………………………… 17 2.2.1: CP0 – The System Coprocessor ………………………………………………………………………………………… 17 2.2.2: CP0 Registers …………………………………………………………………………………………………………………. 17
Chapter 3: MIPS32 and microMIPS32 Operating Modes………………………………………………………….19
3.1: Debug Mode …………………………………………………………………………………………………………………………… 19 3.2: Kernel Mode ……………………………………………………………………………………………………………………………. 19 3.3: Supervisor Mode ……………………………………………………………………………………………………………………… 19 3.4: User Mode ………………………………………………………………………………………………………………………………. 20 3.5: Other Modes……………………………………………………………………………………………………………………………. 20
3.5.1: 64-bit Floating Point Operations Enable ……………………………………………………………………………… 20 3.5.2: 64-bit FPR Enable……………………………………………………………………………………………………………. 20 3.5.3: Coprocessor 0 Enable………………………………………………………………………………………………………. 21 3.5.4: ISA Mode ……………………………………………………………………………………………………………………….. 21
Chapter 4: Virtual Memory ……………………………………………………………………………………………………. 23
4.1: Differences between Releases of the Architecture………………………………………………………………………… 23 4.1.1: Virtual Memory ………………………………………………………………………………………………………………… 23 4.1.2: Protection of Virtual Memory Pages……………………………………………………………………………………. 23 4.1.3: Context Register ……………………………………………………………………………………………………………… 23
4.2: Terminology……………………………………………………………………………………………………………………………..24 4.2.1: Address Space………………………………………………………………………………………………………………… 24 4.2.2: Segment and Segment Size ……………………………………………………………………………………………… 24 4.2.3: Physical Address Size (PABITS) ……………………………………………………………………………………….. 24
4.3: Virtual Address Spaces …………………………………………………………………………………………………………….. 25 4.4: Compliance……………………………………………………………………………………………………………………………… 27 4.5: Access Control as a Function of Address and Operating Mode ………………………………………………………. 28 4.6: Address Translation and Cacheability & Coherency Attributes for the kseg0 and kseg1 Segments …….. 28 4.7: Address Translation for the kuseg Segment when StatusERL = 1 ……………………………………………………. 29 4.8: Special Behavior for the kseg3 Segment when DebugDM = 1…………………………………………………………. 29 4.9: TLB-Based Virtual Address Translation ………………………………………………………………………………………. 29
4.9.1: Address Space Identifiers (ASID) ………………………………………………………………………………………. 30
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4.9.2: TLB Organization …………………………………………………………………………………………………………….. 30 4.9.3: TLB Initialization………………………………………………………………………………………………………………. 31 4.9.4: Address Translation …………………………………………………………………………………………………………. 32
Chapter 5: Common Device Memory Map………………………………………………………………………………39
5.1: CDMMBase Register ………………………………………………………………………………………………………………… 39 5.2: CDMM – Access Control and Device Register Blocks ……………………………………………………………………. 40 5.2.1: Access Control and Status Registers………………………………………………………………………………….. 41
Chapter 6: Interrupts and Exceptions……………………………………………………………………………………. 43
6.1: Interrupts ………………………………………………………………………………………………………………………………… 43 6.1.1: Interrupt Modes ……………………………………………………………………………………………………………….. 44 6.1.2: Generation of Exception Vector Offsets for Vectored Interrupts ……………………………………………… 53
6.2: Exceptions ………………………………………………………………………………………………………………………………. 55
6.2.1: Exception Priority …………………………………………………………………………………………………………….. 55
6.2.2: Exception Vector Locations……………………………………………………………………………………………….. 57
6.2.3: General Exception Processing…………………………………………………………………………………………… 59
6.2.4: EJTAG Debug Exception ………………………………………………………………………………………………….. 61
6.2.5: Reset Exception ………………………………………………………………………………………………………………. 62
6.2.6: Soft Reset Exception………………………………………………………………………………………………………… 63
6.2.7: Non Maskable Interrupt (NMI) Exception ……………………………………………………………………………. 64
6.2.8: Machine Check Exception…………………………………………………………………………………………………. 65
6.2.9: Address Error Exception …………………………………………………………………………………………………… 65
6.2.10: TLB Refill Exception……………………………………………………………………………………………………….. 66 6.2.11: Execute-Inhibit Exception………………………………………………………………………………………………… 67 6.2.12: Read-Inhibit Exception ……………………………………………………………………………………………………. 67 6.2.13: TLB Invalid Exception …………………………………………………………………………………………………….. 68 6.2.14: TLB Modified Exception ………………………………………………………………………………………………….. 69 6.2.15: Cache Error Exception ……………………………………………………………………………………………………. 69 6.2.16: Bus Error Exception ……………………………………………………………………………………………………….. 70 6.2.17: Integer Overflow Exception ……………………………………………………………………………………………… 70 6.2.18: Trap Exception ………………………………………………………………………………………………………………. 71 6.2.19: System Call Exception ……………………………………………………………………………………………………. 71 6.2.20: Breakpoint Exception ……………………………………………………………………………………………………… 71 6.2.21: Reserved Instruction Exception ……………………………………………………………………………………….. 72 6.2.22: Coprocessor Unusable Exception…………………………………………………………………………………….. 72 6.2.23: Floating Point Exception …………………………………………………………………………………………………. 73 6.2.24: Coprocessor 2 Exception ………………………………………………………………………………………………… 73 6.2.25: Watch Exception ……………………………………………………………………………………………………………. 74 6.2.26: Interrupt Exception …………………………………………………………………………………………………………. 74
Chapter 7: GPR Shadow Registers ……………………………………………………………………………………….. 77
7.1: Introduction to Shadow Sets………………………………………………………………………………………………………. 77 7.2: Support Instructions………………………………………………………………………………………………………………….. 78
Chapter 8: CP0 Hazards ……………………………………………………………………………………………………….. 79
8.1: Introduction……………………………………………………………………………………………………………………………… 79 8.2: Types of Hazards …………………………………………………………………………………………………………………….. 79 8.2.1: Possible Execution Hazards ……………………………………………………………………………………………… 79 8.2.2: Possible Instruction Hazards……………………………………………………………………………………………… 81 8.3: Hazard Clearing Instructions and Events …………………………………………………………………………………….. 82 8.3.1: MIPS32 Instruction Encoding…………………………………………………………………………………………….. 82
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8.3.2: microMIPS32 Instruction Encoding …………………………………………………………………………………….. 83
Chapter 9: Coprocessor 0 Registers …………………………………………………………………………………….. 85
9.1: Coprocessor 0 Register Summary ……………………………………………………………………………………………… 85 9.2: Notation ………………………………………………………………………………………………………………………………….. 90 9.3: Writing CPU Registers………………………………………………………………………………………………………………. 91 9.4: Index Register (CP0 Register 0, Select 0)……………………………………………………………………………………. 92 9.5: Random Register (CP0 Register 1, Select 0) ……………………………………………………………………………….. 93 9.6: EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0) ………………………………………………………………….. 94 9.7: Context Register (CP0 Register 4, Select 0) ………………………………………………………………………………… 99 9.8: ContextConfig Register (CP0 Register 4, Select 1)……………………………………………………………………… 103 9.9: UserLocal Register (CP0 Register 4, Select 2) …………………………………………………………………………… 105 9.10: PageMask Register (CP0 Register 5, Select 0) ………………………………………………………………………… 106 9.11: PageGrain Register (CP0 Register 5, Select 1) ………………………………………………………………………… 108 9.12: Wired Register (CP0 Register 6, Select 0) ……………………………………………………………………………….. 111 9.13: HWREna Register (CP0 Register 7, Select 0) ………………………………………………………………………….. 113 9.14: BadVAddr Register (CP0 Register 8, Select 0) …………………………………………………………………………. 115 9.15: Count Register (CP0 Register 9, Select 0) ……………………………………………………………………………….. 116 9.16: Reserved for Implementations (CP0 Register 9, Selects 6 and 7) ……………………………………………….. 116 9.17: EntryHi Register (CP0 Register 10, Select 0)……………………………………………………………………………. 117 9.18: Compare Register (CP0 Register 11, Select 0)…………………………………………………………………………. 119 9.19: Reserved for Implementations (CP0 Register 11, Selects 6 and 7) ……………………………………………… 119 9.20: Status Register (CP Register 12, Select 0) ………………………………………………………………………………. 120 9.21: IntCtl Register (CP0 Register 12, Select 1) ………………………………………………………………………………. 127 9.22: SRSCtl Register (CP0 Register 12, Select 2)……………………………………………………………………………. 130 9.23: SRSMap Register (CP0 Register 12, Select 3) …………………………………………………………………………. 133 9.24: Cause Register (CP0 Register 13, Select 0) …………………………………………………………………………….. 134 9.25: Exception Program Counter (CP0 Register 14, Select 0) …………………………………………………………… 140
9.25.1: Special Handling of the EPC Register in Processors That Implement the MIPS16e ASE or the
microMIPS32 Base Architectures ……………………………………………………………………………………………… 140 9.26: Processor Identification (CP0 Register 15, Select 0) …………………………………………………………………. 142 9.27: EBase Register (CP0 Register 15, Select 1) …………………………………………………………………………….. 144 9.28: CDMMBase Register (CP0 Register 15, Select 2) …………………………………………………………………….. 146 9.29: CMGCRBase Register (CP0 Register 15, Select 3)…………………………………………………………………… 148 9.30: Configuration Register (CP0 Register 16, Select 0) …………………………………………………………………… 149 9.31: Configuration Register 1 (CP0 Register 16, Select 1) ………………………………………………………………… 152 9.32: Configuration Register 2 (CP0 Register 16, Select 2) ………………………………………………………………… 156 9.33: Configuration Register 3 (CP0 Register 16, Select 3) ………………………………………………………………… 159 9.34: Configuration Register 4 (CP0 Register 16, Select 4) ………………………………………………………………… 165 9.35: Reserved for Implementations (CP0 Register 16, Selects 6 and 7) ……………………………………………… 169 9.36: Load Linked Address (CP0 Register 17, Select 0) …………………………………………………………………….. 170 9.37: WatchLo Register (CP0 Register 18) ………………………………………………………………………………………. 171 9.38: WatchHi Register (CP0 Register 19) ……………………………………………………………………………………….. 173 9.39: Reserved for Implementations (CP0 Register 22, all Select values) …………………………………………….. 175 9.40: Debug Register (CP0 Register 23, Select 0 ) ……………………………………………………………………………. 176 9.41: Debug2 Register (CP0 Register 23, Select 6) …………………………………………………………………………… 178 9.42: DEPC Register (CP0 Register 24) ………………………………………………………………………………………….. 179
9.42.1: Special Handling of the DEPC Register in Processors That Implement the MIPS16e ASE or
microMIPS32 Base Architecture ……………………………………………………………………………………………….. 179 9.43: Performance Counter Register (CP0 Register 25) …………………………………………………………………….. 180 9.44: ErrCtl Register (CP0 Register 26, Select 0) ……………………………………………………………………………… 184 9.45: CacheErr Register (CP0 Register 27, Select 0) ………………………………………………………………………… 185 9.46: TagLo Register (CP0 Register 28, Select 0, 2) …………………………………………………………………………. 186
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9.47: DataLo Register (CP0 Register 28, Select 1, 3) ………………………………………………………………………… 187 9.48: TagHi Register (CP0 Register 29, Select 0, 2)………………………………………………………………………….. 188 9.49: DataHi Register (CP0 Register 29, Select 1, 3) ………………………………………………………………………… 189 9.50: ErrorEPC (CP0 Register 30, Select 0) …………………………………………………………………………………….. 190
9.50.1: Special Handling of the ErrorEPC Register in Processors That Implement the MIPS16e ASE or
microMIPS32 Base Architecture ……………………………………………………………………………………………….. 190 9.51: DESAVE Register (CP0 Register 31)………………………………………………………………………………………. 192 9.52: KScratchn Registers (CP0 Register 31, Selects 2 to 7) ……………………………………………………………… 194
Appendix A: Alternative MMU Organizations ………………………………………………………………………. 195
A.1: Fixed A.1.1: A.1.2: A.1.3: A.2: Block A.2.1: A.2.2: A.2.3:
Appendix B: Revision History …………………………………………………………………………………………….. 209
Mapping MMU ………………………………………………………………………………………………………………. 195 Fixed Address Translation ………………………………………………………………………………………………. 195 Cacheability Attributes ……………………………………………………………………………………………………. 198 Changes to the CP0 Register Interface …………………………………………………………………………….. 199 Address Translation ………………………………………………………………………………………………………. 199 BAT Organization ………………………………………………………………………………………………………….. 199 Address Translation……………………………………………………………………………………………………….. 200
Changes to the CP0 Register Interface ……………………………………………………………………………. 201 A.3: Dual Variable-Page-Size and Fixed-Page-Size TLBs ………………………………………………………………….. 202 A.3.1: MMU Organization…………………………………………………………………………………………………………. 202 A.3.2: Programming Interface …………………………………………………………………………………………………… 203 A.3.3: Changes to the TLB Instructions ……………………………………………………………………………………… 205 A.3.4: Changes to the COP0 Registers ……………………………………………………………………………………… 206 A.3.5: Software Compatibility ……………………………………………………………………………………………………. 208
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Figures
Figure 4-1:
Figure 4-2:
Figure 4.3:
Figure 5.1:
Figure 5.2:
Figure 6-1:
Figure 6-2:
Figure 9-1:
Figure 9-2:
Figure 9-3:
Figure 9-4:
Figure 9-5:
Figure 9-6:
Figure 9-7:
Figure 9.8:
Figure 9-9:
Figure 9-10: PageMask Register Format ………………………………………………………………………………………………. 106 Figure 9-11: PageGrain Register Format……………………………………………………………………………………………….. 108 Figure 9-12: Wired And Random Entries In The TLB ………………………………………………………………………………. 111 Figure 9-13: Wired Register Format………………………………………………………………………………………………………. 111 Figure 9-14: HWREna Register Format …………………………………………………………………………………………………. 113 Figure 9-15: BadVAddr Register Format………………………………………………………………………………………………… 115 Figure 9-16: Count Register Format ……………………………………………………………………………………………………… 116 Figure 9-17: EntryHi Register Format ……………………………………………………………………………………………………. 117 Figure 9-18: Compare Register Format …………………………………………………………………………………………………. 119 Figure 9-19: Status Register Format……………………………………………………………………………………………………… 120 Figure 9-20: IntCtl Register Format……………………………………………………………………………………………………….. 127 Figure 9-21: SRSCtl Register Format ……………………………………………………………………………………………………. 130 Figure 9-22: SRSMap Register Format………………………………………………………………………………………………….. 133 Figure 9-23: Cause Register Format……………………………………………………………………………………………………… 134 Figure 9-24: EPC Register Format………………………………………………………………………………………………………… 140 Figure 9-25: PRId Register Format ……………………………………………………………………………………………………….. 142 Figure 9-26: EBase Register Format …………………………………………………………………………………………………….. 144 Figure 9.27: CDMMBase Register ………………………………………………………………………………………………………… 146 Figure 9.28: CMGCRBase Register………………………………………………………………………………………………………. 148 Figure 9-29: Config Register Format……………………………………………………………………………………………………… 149 Figure 9-1: Config1 Register Format……………………………………………………………………………………………………… 152 Figure 9-30: Config2 Register Format……………………………………………………………………………………………………. 156 Figure 9-31: Config3 Register Format……………………………………………………………………………………………………. 159 Figure 9-32: Config4 Register Format……………………………………………………………………………………………………. 165 Figure 9-33: LLAddr Register Format ……………………………………………………………………………………………………. 170 Figure 9-34: WatchLo Register Format………………………………………………………………………………………………….. 171 Figure 9-35: WatchHi Register Format ………………………………………………………………………………………………….. 173 Figure 9-36: Performance Counter Control Register Format …………………………………………………………………….. 180 Figure 9-37: Performance Counter Counter Register Format……………………………………………………………………. 183 Figure 9-38: ErrorEPC Register Format…………………………………………………………………………………………………. 190 Figure 9-39: KScratchn Register Format ……………………………………………………………………………………………….. 194
Virtual Address Space ………………………………………………………………………………………………………….. 25 References as a Function of Operating Mode ………………………………………………………………………….. 27 Contents of a TLB Entry ……………………………………………………………………………………………………….. 30 Example Organization of the CDMM ………………………………………………………………………………………. 41 Access Control and Status Register ……………………………………………………………………………………….. 41 Interrupt Generation for Vectored Interrupt Mode……………………………………………………………………… 49 Interrupt Generation for External Interrupt Controller Interrupt Mode…………………………………………… 52 Index Register Format ………………………………………………………………………………………………………….. 92 Random Register Format ……………………………………………………………………………………………………… 93 EntryLo0, EntryLo1 Register Format in Release 1 of the Architecture …………………………………………. 94 EntryLo0, EntryLo1 Register Format in Release 2 of the Architecture …………………………………………. 95 EntryLo0, EntryLo1 Register Format in Release 3 of the Architecture …………………………………………. 96 Context Register Format when Config3CTXTC=0 and Config3SM=0………………………………………….. 99 Context Register Format when Config3CTXTC=1 or Config3SM=1 ………………………………………….. 100
ContextConfig Register Format …………………………………………………………………………………………… 103 UserLocal Register Format………………………………………………………………………………………………….. 105
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Figure A-1: Memory Mapping when ERL = 0………………………………………………………………………………………….. 197 Figure A-2: Memory Mapping when ERL = 1………………………………………………………………………………………….. 198 Figure A-3: Config Register Additions……………………………………………………………………………………………………. 199 Figure A-4: Contents of a BAT Entry …………………………………………………………………………………………………….. 200
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Tables
Table 1.1: Symbols Used in Instruction Operation Statements……………………………………………………………………. 13 Table 4.1: Virtual Memory Address Spaces……………………………………………………………………………………………… 26 Table 4.2: Address Space Access as a Function of Operating Mode…………………………………………………………… 28 Table 4.3: Address Translation and Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments . 29 Table 4.4: Physical Address Generation………………………………………………………………………………………………….. 36 Table 5.1: Access Control and Status Register Field Descriptions………………………………………………………………. 41 Table 6.1: Interrupt Modes…………………………………………………………………………………………………………………….. 44 Table 6.2: Request for Interrupt Service in Interrupt Compatibility Mode ……………………………………………………… 45 Table 6.3: Relative Interrupt Priority for Vectored Interrupt Mode………………………………………………………………… 48 Table 6.4: Exception Vector Offsets for Vectored Interrupts……………………………………………………………………….. 53 Table 6.5: Interrupt State Changes Made Visible by EHB ………………………………………………………………………….. 54 Table 6.6: Priority of Exceptions …………………………………………………………………………………………………………….. 55 Table 6.7: Exception Type Characteristics……………………………………………………………………………………………….. 57 Table 6.8: Exception Vector Base Addresses…………………………………………………………………………………………… 58 Table 6.9: Exception Vector Offsets ……………………………………………………………………………………………………….. 58 Table 6.10: Exception Vectors ……………………………………………………………………………………………………………….. 59 Table 6.11: Value Stored in EPC, ErrorEPC, or DEPC on an Exception………………………………………………………. 60 Table 7.1: Instructions Supporting Shadow Sets ………………………………………………………………………………………. 78 Table 8.1: Possible Execution Hazards …………………………………………………………………………………………………… 79 Table 8.2: Possible Instruction Hazards…………………………………………………………………………………………………… 81 Table 8.3: Hazard Clearing Instructions…………………………………………………………………………………………………… 82 Table 9.1: Coprocessor 0 Registers in Numerical Order ……………………………………………………………………………. 85 Table 9.2: Read/Write Bit Field Notation………………………………………………………………………………………………….. 90 Table 9.3: Index Register Field Descriptions ……………………………………………………………………………………………. 92 Table 9.4: Random Register Field Descriptions………………………………………………………………………………………… 93 Table 9.5: EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture ………………………….. 94 Table 9.6: EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture ………………………….. 95 Table 9.7: EntryLo Field Widths as a Function of PABITS………………………………………………………………………….. 96 Table 9.8: EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture ………………………….. 97 Table 9.9: Cacheability and Coherency Attributes …………………………………………………………………………………….. 98 Table 9.10: Context Register Field Descriptions when Config3CTXTC=0 and Config3SM=0………………………….. 99 Table 9.11: Context Register Field Descriptions when Config3CTXTC=1 or Config3SM=1………………………….. 100 Table 9.13: Recommended ContextConfig Values………………………………………………………………………………….. 104 Table 9.12: ContextConfig Register Field Descriptions …………………………………………………………………………… 104 Table 9.14: UserLocal Register Field Descriptions………………………………………………………………………………….. 105 Table 9.15: PageMask Register Field Descriptions …………………………………………………………………………………. 106 Table 9.16: Values for the Mask and MaskX1 Fields of the PageMask Register …………………………………………. 107 Table 9.17: PageGrain Register Field Descriptions…………………………………………………………………………………. 108 Table 9.18: Wired Register Field Descriptions………………………………………………………………………………………… 112 Table 9.19: HWREna Register Field Descriptions …………………………………………………………………………………… 113 Table 9.20: RDHWR Register Numbers ………………………………………………………………………………………………… 114 Table 9.21: BadVAddr Register Field Descriptions………………………………………………………………………………….. 115 Table 9.22: Count Register Field Descriptions………………………………………………………………………………………… 116 Table 9.23: EntryHi Register Field Descriptions ……………………………………………………………………………………… 117 Table 9.24: Compare Register Field Descriptions …………………………………………………………………………………… 119 Table 9.25: Status Register Field Descriptions……………………………………………………………………………………….. 120 Table 9.26: IntCtl Register Field Descriptions…………………………………………………………………………………………. 127
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Table 9.27: SRSCtl Register Field Descriptions ……………………………………………………………………………………… 130 Table 9.28: Sources for new SRSCtlCSS on an Exception or Interrupt………………………………………………………..131 Table 9.29: SRSMap Register Field Descriptions……………………………………………………………………………………. 133 Table 9.30: Cause Register Field Descriptions……………………………………………………………………………………….. 134 Table 9.31: Cause Register ExcCode Field……………………………………………………………………………………………. 138 Table 9.32: EPC Register Field Descriptions………………………………………………………………………………………….. 140 Table 9.33: PRId Register Field Descriptions …………………………………………………………………………………………. 142 Table 9.34: EBase Register Field Descriptions……………………………………………………………………………………….. 144 Table 9.35: Conditions Under Which EBase15..12 Must Be Zero ……………………………………………………………… 145 Table 9.36: CDMMBase Register Field Descriptions……………………………………………………………………………….. 146 Table 9.37: CMGCRBase Register Field Descriptions …………………………………………………………………………….. 148 Table 9.38: Config Register Field Descriptions……………………………………………………………………………………….. 149 Table 9-1: Config1 Register Field Descriptions……………………………………………………………………………………….. 152 Table 9.39: Config2 Register Field Descriptions……………………………………………………………………………………… 156 Table 9.40: Config3 Register Field Descriptions……………………………………………………………………………………… 159 Table 9.41: Config4 Register Field Descriptions……………………………………………………………………………………… 165 Table 9.42: LLAddr Register Field Descriptions………………………………………………………………………………………. 170 Table 9.43: WatchLo Register Field Descriptions……………………………………………………………………………………. 171 Table 9.44: WatchHi Register Field Descriptions…………………………………………………………………………………….. 173 Table 9.45: Example Performance Counter Usage of the PerfCnt CP0 Register…………………………………………. 180 Table 9.46: Performance Counter Control Register Field Descriptions ………………………………………………………. 181 Table 9.47: Performance Counter Counter Register Field Descriptions……………………………………………………… 183 Table 9.48: ErrorEPC Register Field Descriptions…………………………………………………………………………………… 190 Table 9.49: KScratchn Register Field Descriptions………………………………………………………………………………….. 194 Table A.1: Physical Address Generation from Virtual Addresses ………………………………………………………………. 195 Table A.2: Config Register Field Descriptions ………………………………………………………………………………………… 199 Table A.3: BAT Entry Assignments……………………………………………………………………………………………………….. 200
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Chapter 1
About This Book
The MIPS® Architecture For Programmers Volume III: The MIPS32® and microMIPS32TM Privileged Resource Architecture comes as part of a multi-volume set.
• Volume I-A describes conventions used throughout the document set, and provides an introduction to the MIPS32® Architecture
• Volume I-B describes conventions used throughout the document set, and provides an introduction to the microMIPS32TM Architecture
• Volume II-A provides detailed descriptions of each instruction in the MIPS32® instruction set
• Volume II-B provides detailed descriptions of each instruction in the microMIPS32TM instruction set
• Volume III describes the MIPS32® and microMIPS32TM Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS® processor implementation
• Volume IV-a describes the MIPS16eTM Application-Specific Extension to the MIPS32® Architecture. Beginning with Release 3 of the Architecture, microMIPS is the preferred solution for smaller code size.
• Volume IV-b describes the MDMXTM Application-Specific Extension to the MIPS64® Architecture and microMIPS64TM. It is not applicable to the MIPS32® document set nor the microMIPS32TM document set
• Volume IV-c describes the MIPS-3D® Application-Specific Extension to the MIPS® Architecture
• Volume IV-d describes the SmartMIPS®Application-Specific Extension to the MIPS32® Architecture and the microMIPS32TM Architecture
• Volume IV-e describes the MIPS® DSP Application-Specific Extension to the MIPS® Architecture
• Volume IV-f describes the MIPS® MT Application-Specific Extension to the MIPS® Architecture
• Volume IV-h describes the MIPS® MCU Application-Specific Extension to the MIPS® Architecture
1.1 Typographical Conventions
This section describes the use of italic, bold and courier fonts in this book. 1.1.1 Italic Text
• is used for emphasis
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• is used for bits, fields, registers, that are important from a software perspective (for instance, address bits used by software, and programmable fields and registers), and various floating point instruction formats, such as S, D, and PS
• is used for the memory access types, such as cached and uncached 1.1.2 Bold Text
• represents a term that is being defined
• is used for bits and fields that are important from a hardware perspective (for instance, register bits, which are
not programmable but accessible only to hardware)
• is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through 1
• is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below. 1.1.3 Courier Text
Courier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.
1.2 UNPREDICTABLE and UNDEFINED
The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations.
1.2.1 UNPREDICTABLE
UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is gener- ated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.
UNPREDICTABLE results or operations have several implementation restrictions:
• Implementations of operations generating UNPREDICTABLE results must not depend on any data source
(memory or internal state) which is inaccessible in the current processor mode
• UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process
• UNPREDICTABLE operations must not halt or hang the processor
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1.2.2 UNDEFINED
UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED opera- tions or behavior may cause data loss.
UNDEFINED operations or behavior has one implementation restriction:
• UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which there is no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state
1.2.3 UNSTABLE
UNSTABLE results or values may vary as a function of time on the same implementation or instruction. Unlike UNPREDICTABLE values, software may depend on the fact that a sampling of an UNSTABLE value results in a legal transient value that was correct at some point in time prior to the sampling.
UNSTABLE values have one implementation restriction:
• Implementations of operations generating UNSTABLE results must not depend on any data source (memory or
internal state) which is inaccessible in the current processor mode
1.3 Special Symbols in Pseudocode Notation
In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1.1.
Table 1.1 Symbols Used in Instruction Operation Statements
1.3 Special Symbols in Pseudocode Notation
Symbol
Meaning
←
Assignment
=, ≠
Tests for equality and inequality
||
Bit string concatenation
xy
A y-bit string formed by y copies of the single-bit value x
b#n
A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the “b#” prefix is omitted, the default base is 10.
0bn
A constant value n in base 2. For instance 0b100 represents the binary value 100 (decimal 4).
0xn
A constant value n in base 16. For instance 0x100 represents the hexadecimal value 100 (decimal 256).
xy..z
Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is less than z, this expression is an empty (zero length) bit string.
+, −
2’s complement or floating point arithmetic: addition, subtraction
*, ×
2’s complement or floating point multiplication (both used for either)
div
2’s complement integer division
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Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
Symbol
Meaning
mod
2’s complement modulo
/
Floating point division
< 2’s complement less-than comparison >
2’s complement greater-than comparison
≤
2’s complement less-than or equal comparison
≥
2’s complement greater-than or equal comparison
nor
Bitwise logical NOR
xor
Bitwise logical XOR
and
Bitwise logical AND
or
Bitwise logical OR
GPRLEN
The length in bits (32 or 64) of the CPU general-purpose registers
GPR[x]
CPU general-purpose register x. The content of GPR[0] is always zero. In Release 2 of the Architecture, GPR[x] is a short-hand notation for SGPR[ SRSCtlCSS, x].
SGPR[s,x]
In Release 2 of the Architecture and subsequent releases, multiple copies of the CPU general-purpose regis- ters may be implemented. SGPR[s,x] refers to GPR set s, register x.
FPR[x]
Floating Point operand register x
FCC[CC]
Floating Point condition code CC. FCC[0] has the same value as COC[1].
FPR[x]
Floating Point (Coprocessor unit 1), general register x
CPR[z,x,s]
Coprocessor unit z, general register x, select s
CP2CPR[x]
Coprocessor unit 2, general register x
CCR[z,x]
Coprocessor unit z, control register x
CP2CCR[x]
Coprocessor unit 2, control register x
COC[z]
Coprocessor unit z condition signal
Xlat[x]
Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number
BigEndianMem
Endian mode as configured at chip reset (0 →Little-Endian, 1 → Big-Endian). Specifies the endianness of the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endi- anness of Kernel and Supervisor mode execution.
BigEndianCPU
The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com- puted as (BigEndianMem XOR ReverseEndian).
ReverseEndian
Signal to reverse the endianness of load and store instructions. This feature is available in User mode only, and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as (SRRE and User mode).
LLbit
Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation, when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc- tions.
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Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
1.3 Special Symbols in Pseudocode Notation
Symbol
Meaning
I:, I+n:, I-n:
This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the instruction time of another instruction. When this happens, the instruction operation is written in sections labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode appears to occur. For example, an instruction may have a result that is not available until after the next instruction. Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I+1.
The effect of pseudocode statements for the current instruction labelled I+1 appears to occur “at the same time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode sequence, the effects of the statements take place in order. However, between sequences of statements for different instructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.
PC
The Program Counter value. During the instruction time of an instruction, this is the address of the instruc- tion word. The address of the instruction that occurs during the next instruction time is determined by assign- ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc- tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.
In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the restart address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an exception. The PC value contains a full 32-bit address all of which are significant during a memory ref- erence.
ISA Mode
In processors that implement the MIPS16e Application Specific Extension or the microMIPS base architec- tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol- lows:
In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an exception.
Encoding
Meaning
0
The processor is executing 32-bit MIPS instructions
1
The processor is executing MIIPS16e instructions
PABITS
The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.
FP32RegistersMode
Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). the FPU has 32 64-bit FPRs in which 64-bit data types are stored in any FPR.
MIPS64 implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a case FP32RegisterMode is computed from the FR bit in the Status reg- ister. If this bit is a 0, the processor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor oper- ates with 32 64-bit FPRs.
The value of FP32RegistersMode is computed from the FR bit in the Status register.
InstructionInBranchDe- laySlot
Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.
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Table 1.1 Symbols Used in Instruction Operation Statements (Continued)
Symbol
Meaning
SignalException(excep- tion, argument)
Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function—the exception is signaled at the point of the call.
1.4 For More Information
Various MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS URL: http://www.mips.com
For comments or questions on the MIPS32® Architecture or this document, send Email to support@mips.com.
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Chapter 2
The MIPS32 and microMIPS32 Privileged Resource Architecture
2.1 Introduction
The MIPS32 and microMIPS32 Privileged Resource Architecture (PRA) is a set of environments and capabilities on which the Instruction Set Architectures operate. The effects of some components of the PRA are user-visible, for instance, the virtual memory layout. Many other components are visible only to the operating system kernel and to systems programmers. The PRA provides the mechanisms necessary to manage the resources of the CPU: virtual memory, caches, exceptions and user contexts. This chapter describes these mechanisms.
2.2 The MIPS Coprocessor Model
The MIPS ISA provides for up to 4 coprocessors. A coprocessor extends the functionality of the MIPS ISA, while sharing the instruction fetch and execution control logic of the CPU. Some coprocessors, such as the system copro- cessor and the floating point unit are standard parts of the ISA, and are specified as such in the architecture docu- ments. Coprocessors are generally optional, with one exception: CP0, the system coprocessor, is required. CP0 is the ISA interface to the Privileged Resource Architecture and provides full control of the processor state and modes.
2.2.1 CP0 – The System Coprocessor
CP0 provides an abstraction of the functions necessary to support an operating system: exception handling, memory management, scheduling, and control of critical resources. The interface to CP0 is through various instructions encoded with the COP0 opcode, including the ability to move data to and from the CP0 registers, and specific func- tions that modify CP0 state. The CP0 registers and the interaction with them make up much of the Privileged Resource Architecture.
2.2.2 CP0 Registers
The CP0 registers provide the interface between the ISA and the PRA. The CP0 registers are described in Chapter 9.
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The MIPS32 and microMIPS32 Privileged Resource Architecture
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Chapter 3
MIPS32 and microMIPS32 Operating Modes
The MIPS32 and microMIPS32 PRA requires two operating mode: User Mode and Kernel Mode. When operating in User Mode, the programmer has access to the CPU and FPU registers that are provided by the ISA and to a flat, uni- form virtual memory address space. When operating in Kernel Mode, the system programmer has access to the full capabilities of the processor, including the ability to change virtual memory mapping, control the system environ- ment, and context switch between processes.
In addition, the MIPS PRA supports the implementation of two additional modes: Supervisor Mode and EJTAG Debug Mode. Refer to the EJTAG specification for a description of Debug Mode.
In Release 2 of the MIPS32 Architecture, support was added for 64-bit coprocessors (and, in particular, 64-bit float- ing point units) with 32-bit CPUs. As such, certain floating point instructions which were previously enabled by 64-bit operations on a MIPS64 processor are now enabled by a new 64-bit floating point operations enabled. Release 3 (e.g. MIPSr3) introduced the microMIPS instruction set, so all microMIPS processors may implement a 64-bit floating point unit.
3.1 Debug Mode
For processors that implement EJTAG, the processor is operating in Debug Mode if the DM bit in the CP0 Debug register is a one. If the processor is running in Debug Mode, it has full access to all resources that are available to Ker- nel Mode operation.
3.2 Kernel Mode
The processor is operating in Kernel Mode when the DM bit in the Debug register is a zero (if the processor imple- ments Debug Mode), and any of the following three conditions is true:
• The KSU field in the CP0 Status register contains 0b00
• The EXL bit in the Status register is one
• The ERL bit in the Status register is one
The processor enters Kernel Mode at power-up, or as the result of an interrupt, exception, or error. The processor leaves Kernel Mode and enters User Mode or Supervisor Mode when all of the previous three conditions are false, usually as the result of an ERET instruction.
3.3 Supervisor Mode
The processor is operating in Supervisor Mode (if that optional mode is implemented by the processor) when all of the following conditions are true:
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MIPS32 and microMIPS32 Operating Modes
• The DM bit in the Debug register is a zero (if the processor implements Debug Mode)
• The KSU field in the Status register contains 0b01
• The EXL and ERL bits in the Status register are both zero
3.4 User Mode
The processor is operating in User Mode when all of the following conditions are true:
• The DM bit in the Debug register is a zero (if the processor implements Debug Mode)
• The KSU field in the Status register contains 0b10
• The EXL and ERL bits in the Status register are both zero
3.5 Other Modes
3.5.1 64-bit Floating Point Operations Enable
Instructions that are implemented by a 64-bit floating point unit are legal under any of the following conditions:
• In an implementation of Release 1 of the Architecture, 64-bit floating point operations are never enabled in a MIPS32 processor.
• In an implementation of Release 2 (and subsequent releases) of the Architecture, 64-bit floating point operations are enabled if the F64 bit in the FIR register is a one. The processor must also implement the floating point data type. Release 3 (e.g. MIPSr3) introduced the microMIPS instruction set. So on all microMIPS processors, 64-bit floating point operations are enabled if the F64 bit in the FIR register is a one .
3.5.2 64-bit FPR Enable
Access to 64-bit FPRs is controlled by the FR bit in the Status register. If the FR bit is one, the FPRs are interpreted as 32 64-bit registers that may contain any data type. If the FR bit is zero, the FPRs are interpreted as 32 32-bit registers, any of which may contain a 32-bit data type (W, S). In this case, 64-bit data types are contained in even-odd pairs of registers.
64-bit FPRs are supported in a MIPS64 processor in Release 1 of the Architecture, or in a 64-bit floating point unit, for both MIPS32 and MIPS64 processors, in Release 2 of the Architecture. 64-bit FPRs are supported for all proces- sors using Architecture releases subsequent to Release 2, including all microMIPS processors.
The operation of the processor is UNPREDICTABLE under the following conditions:
• The FR bit is a zero, 64-bit operations are enabled, and a floating point instruction is executed whose datatype is
L or PS.
• The FR bit is a zero and an odd register is referenced by an instruction whose datatype is 64-bits
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3.5.3 Coprocessor 0 Enable
Access to Coprocessor 0 registers are enabled under any of the following conditions:
• The processor is running in Kernel Mode or Debug Mode, as defined above
• The CU0 bit in the Status register is one.
3.5.4 ISA Mode
Release 3 of the Architecture (e.g. MIPSr3TM) introduced a second branch of the instruction set family, microMIPS32. Devices can implement both ISA branches (MIPS32 and microMIPS32) or only one branch.
The ISA Mode bit is used to denote which ISA branch to use when decoding instructions. This bit is normally not vis- ible to software. It’s value is saved to any GPR that would be used as a jump target address, such as GPR31 when written by a JAL instruction or the source register for a JR instruction.
For processors that implement the MIPS32 ISA, the ISA Mode bit value of zero selects MIPS32. For processors that implement the microMIPS32 ISA, the ISA Mode bit value of one selects microMIPS32. For processors that imple-
ment the MIPS16eTM ASE, the ISA Mode bit value of one selects MIPS16e. A processor is not allowed to implement both MIPS16e and microMIPS.
Please read Volume II-B: Introduction to the microMIPS32 Instruction Set, Section 5.3, “ISA Mode Switch” for a more in-depth description of ISA mode switching between the ISA branches and the ISA Mode bit.
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3.5 Other Modes
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MIPS32 and microMIPS32 Operating Modes
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Chapter 4
Virtual Memory
4.1 Differences between Releases of the Architecture 4.1.1 Virtual Memory
In Release 1 of the Architecture, the minimum page size was 4KB, with optional support for pages as large as 256MB. In Release 2 of the Architecture (and subsequent releases), optional support for 1KB pages was added for use in specific embedded applications that require access to pages smaller than 4KB. Such usage is expected to be in conjunction with a default page size of 4KB and is not intended or suggested to replace the default 4KB page size but, rather, to augment it.
Support for 1KB pages involves the following changes:
• Addition of the PageGrain register. This register is also used by the SmartMIPSTM ASE specification, but bits used by Release 2 of the Architecture and the SmartMIPS ASE specification do not overlap.
• Modification of the EntryHi register to enable writes to, and use of, bits 12..11 (VPN2X).
• Modification of the PageMask register to enable writes to, and use of, bits 12..11 (MaskX).
• Modification of the EntryLo0 and EntryLo1 registers to shift the PFN field to the left by 2 bits, when 1KB page support is enabled, to create space for two lower-order physical address bits.
Support for 1KB pages is denoted by the Config3SP bit and enabled by the PageGrainESP bit.
4.1.2 Protection of Virtual Memory Pages
In Release 3 of the Architecture, e.g. MIPSr3, two optional control bits are added to each TLB entry. These bits, RI (Read Inhibit) and XI (Execute Inhibit), allows more types of protection to be used for virtual pages – including write-only pages, non-executable pages.
This feature originated in the SmartMIPS ASE but has been modified from the original SmartMIPS definition. For the Release 3 version of this feature, each of the RI and XI bits can be separately implemented. For the Release 3 version of this feature, new exception codes are used when a TLB access does not obey the RI/XI bits.
4.1.3 Context Register
In Release 3 of the Architecture, e.g. MIPSr3, the Context register is a read/write register containing a address pointer that can point to an arbitrary power-of-two aligned data structure in memory, such as an entry in the page table entry (PTE) array. In Releases 1 & 2, this pointer was defined to reference a fixed-sized 16-byte structure in memory within a linear array containing an entry for each even/odd virtual page pair. The Release 3 version of the Context register can be used far more generally.
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Virtual Memory
This feature originated in the SmartMIPS ASE. This feature is optional in the Release 3 version of the base architec- ture.
4.2 Terminology 4.2.1 Address Space
An Address Space is the range of all possible addresses that can be generated. There is one 32-bit Address Space in the MIPS32 Architecture.
4.2.2 Segment and Segment Size
A Segment is a defined subset of an Address Space that has self-consistent reference and access behavior. Segments are either 229 or 231 bytes in size, depending on the specific Segment.
4.2.3 Physical Address Size (PABITS)
The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 physical
address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes. The format of the
EntryLo0 and EntryLo1 registers implicitly limits the physical address size to 236 bytes. Software may determine the value of PABITS by writing all ones to the EntryLo0 or EntryLo1 registers and reading the value back. Bits read as “1” from the PFN field allow software to determine the boundary between the PFN and 0 fields to calculate the value of PABITS.
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4.3 Virtual Address Spaces
The MIPS32/microMIPS32 virtual address space is divided into five segments as shown in Figure 4-1.
Figure 4-1 Virtual Address Space
0xFFFF FFFF
kseg3
0xE000 0000 0xDFFF FFFF
ksseg
0xC000 0000 0xBFFF FFFF
kseg1
0xA000 0000 0x9FFF FFFF
kseg0
0x8000 0000 0x7FFF FFFF
useg
0x0000 0000
Each Segment of an Address Space is classified as “Mapped” or “Unmapped”. A “Mapped” address is one that is translated through the TLB or other address translation unit. An “Unmapped” address is one which is not translated through the TLB and which provides a window into the lowest portion of the physical address space, starting at phys- ical address zero, and with a size corresponding to the size of the unmapped Segment.
Additionally, the kseg1 Segment is classified as “Uncached”. References to this Segment bypass all levels of the cache hierarchy and allow direct access to memory without any interference from the caches.
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4.3 Virtual Address Spaces
Kernel Mapped
Supervisor Mapped
Kernel Unmapped Uncached
Kernel Unmapped
User Mapped
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Virtual Memory
Table 4.1 lists the same information in tabular form. Each Segment of an Address Space is associated with one of the Table 4.1 Virtual Memory Address Spaces
VA31..29
Segment Name(s)
Address Range
Associated with Mode
Reference Legal from Mode(s)
Actual Segment Size
0b111
kseg3
0xFFFF FFFF
through
0xE000 0000
Kernel
Kernel
229 bytes
0b110
sseg ksseg
0xDFFF FFFF
through
0xC000 0000
Supervisor
Supervisor Kernel
229 bytes
0b101
kseg1
0xBFFF FFFF
through
0xA000 0000
Kernel
Kernel
229 bytes
0b100
kseg0
0x9FFF FFFF
through 0x8000 0000
Kernel
Kernel
229 bytes
0b0xx
useg suseg kuseg
0x7FFF FFFF
through
0x0000 0000
User
User Supervisor Kernel
231 bytes
three processor operating modes (User, Supervisor, or Kernel). A Segment that is associated with a particular mode is accessible if the processor is running in that or a more privileged mode. For example, a Segment associated with User Mode is accessible when the processor is running in User, Supervisor, or Kernel Modes. A Segment is not accessible if the processor is running in a less privileged mode than that associated with the Segment. For example, a Segment associated with Supervisor Mode is not accessible when the processor is running in User Mode and such a reference results in an Address Error Exception. The “Reference Legal from Mode(s)” column in Table 4-2 lists the modes from which each Segment may be legally referenced.
If a Segment has more than one name, each name denotes the mode from which the Segment is referenced. For exam- ple, the Segment name “useg” denotes a reference from user mode, while the Segment name “kuseg” denotes a refer- ence to the same Segment from kernel mode.
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Figure 4-6 shows the Address Space as seen when the processor is operating in each of the operating modes. Figure 4-2 References as a Function of Operating Mode
User Mode References
0xFFFF FFFF
Supervisor Mode References
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
sseg
0xC000 0000 0xBFFF FFFF
0x8000 0000 0x7FFF FFFF
suseg
0x0000 0000
Kernel Mode References
0xFFFF FFFF
kseg3
0xE000 0000 0xDFFF FFFF
ksseg
0xC000 0000 0xBFFF FFFF
kseg1
0xA000 0000 0x9FFF FFFF
kseg0
0x8000 0000 0x7FFF FFFF
kuseg
0x0000 0000
4.4 Compliance
Address Error
User Mapped
Address Error
Supervisor Mapped
Address Error
User Mapped
Kernel Mapped
Supervisor Mapped
Kernel Unmapped Uncached
Kernel Unmapped
User Mapped
0x8000 0000 0x7FFF FFFF
suseg
0x0000 0000
4.4 Compliance
A MIPS32/microMIPS32 compliant processor must implement the following Segments:
• useg/kuseg
• kseg0
• kseg1
In addition, a MIPS32/microMIPS32 compliant processor using the TLB-based address translation mechanism must also implement the kseg3 Segment.
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Virtual Memory
4.5 Access Control as a Function of Address and Operating Mode
Table 4.2 enumerates the action taken by the processor for each section of the 32-bit Address Space as a function of the operating mode of the processor. The selection of TLB Refill vector and other special-cased behavior is also listed for each reference.
Table 4.2 Address Space Access as a Function of Operating Mode
Virtual Address Range
Segment Name(s)
Action when Referenced from Operating Mode
User Mode
Supervisor Mode
Kernel Mode
0xFFFF FFFF
through
0xE000 0000
kseg3
Address Error
Address Error
Mapped
See Section 4.8 for special behavior when DebugDM = 1
0xDFFF FFFF
through
0xC000 0000
sseg ksseg
Address Error
Mapped
Mapped
0xBFFF FFFF
through
0xA000 0000
kseg1
Address Error
Address Error
Unmapped, Uncached See Section 4.6
0x9FFF FFFF
through
0x8000 0000
kseg0
Address Error
Address Error
Unmapped See Section 4.6
0x7FFF FFFF
through
0x0000 0000
useg suseg kuseg
Mapped
Mapped
Unmapped if StatusERL=1 See Section 4.7 Mapped if StatusERL=0
4.6 Address Translation and Cacheability & Coherency Attributes for the kseg0 and kseg1 Segments
The kseg0 and kseg1 Unmapped Segments provide a window into the least significant 229 bytes of physical memory, and, as such, are not translated using the TLB or other address translation unit. The cacheability and coherency attribute of the kseg0 Segment is supplied by the K0 field of the CP0 Config register. The cacheability and coherency
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4.7 Address Translation for the kuseg Segment when StatusERL = 1
attribute for the kseg1 Segment is always Uncached. Table 4.3 describes how this transformation is done, and the source of the cacheability and coherency attributes for each Segment.
Table 4.3 Address Translation and Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments
Segment Name
Virtual Address Range
Generates Physical Address
Cache Attribute
kseg1
0xBFFF FFFF
through
0xA000 0000
0x1FFF FFFF
through
0x0000 0000
Uncached
kseg0
0x9FFF FFFF
through
0x8000 0000
0x1FFF FFFF
through
0x0000 0000
From K0 field of Config Register
4.7 Address Translation for the kuseg Segment when StatusERL = 1
To provide support for the cache error handler, the kuseg Segment becomes an unmapped, uncached Segment, similar to the kseg1 Segment, if the ERL bit is set in the Status register. This allows the cache error exception code to oper- ate uncached using GPR R0 as a base register to save other GPRs before use.
4.8 Special Behavior for the kseg3 Segment when DebugDM = 1
If EJTAG is implemented on the processor, the EJTAG block must treat the virtual address range 0xFF20 0000 through 0xFF3F FFFF, inclusive, as a special memory-mapped region in Debug Mode. A MIPS32/microMIPS32 compliant implementation that also implements EJTAG must:
• explicitly range check the address range as given and not assume that the entire region between 0xFF20 0000 and 0xFFFF FFFF is included in the special memory-mapped region.
• not enable the special EJTAG mapping for this region in any mode other than in EJTAG Debug mode.
Even in Debug mode, normal memory rules may apply in some cases. Refer to the EJTAG specification for details on this mapping.
4.9 TLB-Based Virtual Address Translation1
This section describes the TLB-based virtual address translation mechanism. Note that sufficient TLB entries must be implemented to avoid a TLB exception loop on load and store instructions.
1 Refer to A.1 “Fixed Mapping MMU” on page 195 and A.2 “Block Address Translation” on page 199 for descriptions of alternative MMU organizations
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Virtual Memory
4.9.1 Address Space Identifiers (ASID)
The TLB-based translation mechanism supports Address Space Identifiers to uniquely identify the same virtual address across different processes. The operating system assigns ASIDs to each process and the TLB keeps track of the ASID when doing address translation. In certain circumstances, the operating system may wish to associate the same virtual address with all processes. To address this need, the TLB includes a global (G) bit which over-rides the ASID comparison during translation.
4.9.2 TLB Organization
The TLB is a fully-associative structure which is used to translate virtual addresses. Each entry contains two logical components: a comparison section and a physical translation section. The comparison section includes the virtual page number (VPN2 and, in Release 2 and subsequent releases, VPNX) (actually, the virtual page number/2 since each entry maps two physical pages) of the entry, the ASID, the G(lobal) bit and a recommended mask field which provides the ability to map different page sizes with a single entry. The physical translation section contains a pair of entries, each of which contains the physical page frame number (PFN), a valid (V) bit, a dirty (D) bit, optionally read-inhibit and execute-inhibit (RI & XI) bits and a cache coherency field (C), whose valid encodings are given in Table 9.9. There are two entries in the translation section for each TLB entry because each TLB entry maps an aligned pair of virtual pages and the pair of physical translation entries corresponds to the even and odd pages of the pair.
In Revision 3 of the architecture, the RI and XI bits were added to the TLB to enable more secure access of memory pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, no-execute access pol- icies for mapped pages.
Figure 4.3 shows the logical arrangement of a TLB entry, including the optional support added in Release 2 of the Architecture for 1KB page sizes. Light grey fields denote extensions to the right that are required to support 1KB page sizes. This extension is not present in an implementation of Release 1 of the Architecture.
Figure 4.3 Contents of a TLB Entry
Mask
Maskx
R
VPN2
VPN2X
G
ASID
PFNX
PFN0
C0
RI0
XI0
D0
V0
PFNX
PFN1
C1
RI1
XI1
D1
V1
Fields marked with this color are optional Release 2 features required to support 1KB pages Fields marked with this color are optional Release 3 features added for additional security.
Fields marked with this color are optional Release 2 features required to support larger physical addresses
The fields of the TLB entry correspond exactly to the fields in the CP0 PageMask, EntryHi, EntryLo0 and EntryLo1 registers. The even page entries in the TLB (e.g., PFN0) come from EntryLo0. Similarly, odd page entries come from EntryLo1.
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4.9.3 TLB Initialization
In many processor implementations, software must initialize the TLB during the power-up process. In processors that detect multiple TLB matches and signal this via a machine check assumption, software must be prepared to handle such an exception or use a TLB initialization algorithm that minimizes or eliminates the possibility of the exception.
In Release 1 of the Architecture, processor implementations could detect and report multiple TLB matches either on a TLB write (TLBWI or TLBWR instructions) or a TLB read (TLB access or TLBR or TLBP instructions). In Release 2 of the Architecture (and subsequent releases), processor implentations are limited to reporting multiple TLB matches only on TLB write, and this is also true of most implementations of Release 1 of the Architecture.
The following code example shows a TLB initialization routine which, on implementations of Release 2 of the Archi- tecture (and subsequent releases), eliminates the possibility of reporting a machine check during TLB initialization. This example has equivalent effect on implementations of Release 1 of the Architecture which report multiple TLB exceptions only on a TLB write, and minimizes the probability of such an exception occuring on other implementa- tions.
/*
* InitTLB
*
* Initialize the TLB to a power-up state, guaranteeing that all entries * are unique and invalid.
*
* Arguments:
* a0 = Maximum TLB index (from MMUSize field of C0_Config1)
*
* Returns:
* No value
*
* Restrictions:
* This routine must be called in unmapped space
*
* Algorithm:
*
*
*
* *}
* *} *
* Notes: * – *
*
*
*
*/
InitTLB: /*
TLB_Write(entry, va, 0, 0, 0);
The Hazard macros used in the code below expand to the appropriate
number of SSNOPs in an implementation of Release 1 of the
Architecture, and to an ehb in an implementation of Release 2 of
the Architecture. See , “CP0 Hazards,” on page 79 for
more additional information.
va = kseg0_base;
for (entry = max_TLB_index; entry >= 0, entry–) {
while (TLB_Probe_Hit(va)) {
va += Page_Size;
* Clear PageMask, EntryLo0 and EntryLo1 so that valid bits are off, PFN values
* are zero, and the default page size is used.
*/
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4.9 TLB-Based Virtual Address Translation
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Virtual Memory
mtc0 zero, C0_EntryLo0 /* Clear out PFN and valid bits */ mtc0 zero, C0_EntryLo1
mtc0 zero, C0_PageMask /* Clear out mask register *
/* Start with the base address of kseg0 for the VA part of the TLB */ la t0, A_K0BASE /* A_K0BASE == 0x8000.0000 */
/*
* Write the VA candidate to EntryHi and probe the TLB to see if if is
* already there. If it is, a write to the TLB may cause a machine
* check, so just increment the VA candidate by one page and try again.
*/
10:
/* Write VA candidate */
/* Clear EntryHi hazard (ssnop/ehb in R1/2) */
/* Probe the TLB to check for a match */
/* Clear Index hazard (ssnop/ehb in R1/2) */
/* Read back flag to check for match */
/* Branch if about to duplicate an entry */
/* Add 1 to VPN index in va */
/*
* A write of the VPN candidate will be unique, so write this entry
* into the next index, decrement the index, and continue until the
* index goes negative (thereby writing all TLB entries)
*/
mtc0 t0, C0_EntryHi TLBP_Write_Hazard() tlbp TLBP_Read_Hazard() mfc0 t1, C0_Index bgez t1, 10b
addiu t0, (1< 7..0 */
/* Shift to emulate software IntCtlVS */
/* Get base of 8 interrupt vectors */
/* Compute target from base and offset */
/* Jump to specific exception routine */
here)
/*
* Each interrupt processing routine processes a specific interrupt, analogous
* to those reached in VI or EIC interrupt mode. Since each processing routine
* is dedicated to a particular interrupt line, it has the context to know
* which line was asserted. Each processing routine may need to look further
* to determine the actual source of the interrupt if multiple interrupt requests
* are ORed together on a single IP line. Once that task is performed, the
* interrupt may be processed in one of two ways:
*
* – Completely at interrupt level (e.g., a simply UART interrupt). The
* SimpleInterrupt routine below is an example of this type.
* – By saving sufficient state and re-enabling other interrupts. In this
* case the software model determines which interrupts are disabled during
* the processing of this interrupt. Typically, this is either the single
* StatusIM bit that corresponds to the interrupt being processed, or some
* collection of other StatusIM bits so that “lower” priority interrupts are
* also disabled. The NestedInterrupt routine below is an example of this type. */
SimpleInterrupt:
/*
* Process the device interrupt here and clear the interupt request
* at the device. In order to do this, some registers may need to be
* saved and restored. The coprocessor 0 state is such that an ERET
* will simply return to the interrupted code.
*/
eret /* Return to interrupted code */
NestedException:
/*
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* Nested exceptions typically require saving the EPC and Status registers,
* any GPRs that may be modified by the nested exception routine, disabling
* the appropriate IM bits in Status to prevent an interrupt loop, putting
* the processor in kernel mode, and re-enabling interrupts. The sample code
* below can not cover all nuances of this processing and is intended only
* to demonstrate the concepts.
*/
/* Save GPRs here, and setup software context */
mfc0 k0, C0_EPC
sw k0, EPCSave
mfc0 k0, C0_Status
sw k0, StatusSave
li k1, ~IMbitsToClear
/* Get restart address */
/* Save in memory */
/* Get Status value */
/* Save in memory */
/* Get Im bits to clear for this interrupt */
/* this must include at least the IM bit */
/* for the current interrupt, and may include */
/* others */
and k0, k0, k1
ins k0, zero, S_StatusEXL,
mtc0 k0, C0_Status
/* Clear bits in copy of Status */
(W_StatusKSU+W_StatusERL+W_StatusEXL)
/* Clear KSU, ERL, EXL bits in k0 */
/* Modify mask, switch to kernel mode, */
/* re-enable interrupts */
/*
* Process interrupt here, including clearing device interrupt.
* In some environments this may be done with a thread running in
* kernel or user mode. Such an environment is well beyond the scope of
* this example.
*/
/*
* To complete interrupt processing, the saved values must be restored
* and the original interrupted code restarted.
*/
di
lw k0, StatusSave
lw k1, EPCSave
mtc0 k0, C0_Status
mtc0 k1, C0_EPC
/* Restore GPRs and software state */
eret /* Dismiss the interrupt */
/* Disable interrupts – may not be required */
/* Get saved Status (including EXL set) */
/* and EPC */
/* Restore the original value */
/* and EPC */
6.1.1.2 Vectored Interrupt Mode
Vectored Interrupt mode builds on the interrupt compatibility mode by adding a priority encoder to prioritize pending interrupts and to generate a vector with which each interrupt can be directed to a dedicated handler routine. This mode also allows each interrupt to be mapped to a GPR shadow set for use by the interrupt handler. Vectored Interrupt mode is in effect if all of the following conditions are true:
• Config3VInt = 1
• Config3VEIC = 0
• IntCtlVS ≠ 0
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Interrupts and Exceptions
• CauseIV = 1
• StatusBEV = 0
In VI interrupt mode, the six hardware interrupts are interpreted as individual hardware interrupt requests. The timer and performance counter interrupts are combined in an implementation-dependent way with the hardware interrupts (with the interrupt with which they are combined indicated by IntCtlIPTI and IntCtlIPPCI, respectively) to provide the appropriate relative priority of these interrupts with that of the hardware interrupts. The processor interrupt logic ANDs each of the CauseIP bits with the corresponding StatusIM bits. If any of these values is 1, and if interrupts are enabled (StatusIE = 1, StatusEXL = 0, and StatusERL = 0), an interrupt is signaled and a priority encoder scans the val- ues in the order shown in Table 6.3.
Table 6.3 Relative Interrupt Priority for Vectored Interrupt Mode
Relative Priority
Interrupt Type
Interrupt Source
Interrupt Request Calculated From
Vector Number Generated by Priority Encoder
Highest Priority
Lowest Priority
Hardware
HW5
CauseIP7 and StatusIM7
7
HW4
CauseIP6 and StatusIM6
6
HW3
CauseIP5 and StatusIM5
5
HW2
CauseIP4 and StatusIM4
4
HW1
CauseIP3 and StatusIM3
3
HW0
CauseIP2 and StatusIM2
2
Software
SW1
CauseIP1 and StatusIM1
1
SW0
CauseIP0 and StatusIM0
0
The priority order places a relative priority on each hardware interrupt and places the software interrupts at a priority lower than all hardware interrupts. When the priority encoder finds the highest priority pending interrupt, it outputs an encoded vector number that is used in the calculation of the handler for that interrupt, as described below. This is shown pictorially in Figure 6-1.
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Figure 6-1 Interrupt Generation for Vectored Interrupt Mode
Latch
Mask IntCtlIPPCI
IntCtlIPTI
Encode
Any Request
StatusIE IntCtlVS
Vector Number
Generate
6.1 Interrupts
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
HW5 HW4 HW3 HW2 HW1 HW0
Interrupt Request
Exception Vector Offset
Shadow Set Number
CauseTI CausePCI
Note that an interrupt request may be deasserted between the time the processor detects the interrupt request and the time that the software interrupt handler runs. The software interrupt handler must be prepared to handle this condition by simply returning from the interrupt via ERET.
A typical software handler for vectored interrupt mode bypasses the entire sequence of code following the IVexcep- tion label shown for the compatibility mode handler above. Instead, the hardware performs the prioritization, dis- patching directly to the interrupt processing routine. Unlike the compatibility mode examples, a vectored interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers. As such, the SimpleInter- rupt code shown above need not save the GPRs.
A nested interrupt is similar to that shown for compatibility mode, but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set. Such a routine might look as follows:
NestedException:
/*
* Nested exceptions typically require saving the EPC, Status and SRSCtl registers,
* setting up the appropriate GPR shadow set for the routine, disabling
* the appropriate IM bits in Status to prevent an interrupt loop, putting
* the processor in kernel mode, and re-enabling interrupts. The sample code
* below can not cover all nuances of this processing and is intended only
* to demonstrate the concepts.
*/
/* Use the current GPR shadow set, and setup software context */
mfc0 k0, C0_EPC sw k0, EPCSave mfc0 k0, C0_Status
/* Get restart address */
/* Save in memory */
/* Get Status value */
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SRSMap
49
Offset Genera- tor
Combine
Priority Encode

Interrupts and Exceptions
sw k0, StatusSave mfc0 k0, C0_SRSCtl
sw k0, SRSCtlSave
li k1, ~IMbitsToClear
and k0, k0, k1
/* If switching shadow sets, write new value to SRSCtlPSS here */ ins k0, zero, S_StatusEXL, (W_StatusKSU+W_StatusERL+W_StatusEXL)
/* Clear KSU, ERL, EXL bits in k0 */
mtc0 k0, C0_Status /* Modify mask, switch to kernel mode, */
/* re-enable interrupts */
/*
* If switching shadow sets, clear only KSU above, write target
* address to EPC, and do execute an eret to clear EXL, switch
* shadow sets, and jump to routine
*/
/* Process interrupt here, including clearing device interrupt */
/*
* To complete interrupt processing, the saved values must be restored
* and the original interrupted code restarted.
*/
di
lw k0, StatusSave lw k1, EPCSave mtc0 k0, C0_Status lw k0, SRSCtlSave mtc0 k1, C0_EPC mtc0 k0, C0_SRSCtl ehb
eret
/* Disable interrupts – may not be required */
/* Get saved Status (including EXL set) */
/* and EPC */
/* Restore the original value */
/* Get saved SRSCtl */
/* and EPC */
/* Restore shadow sets */
/* Clear hazard */
/* Dismiss the interrupt */
/* Save in memory */
/* Save SRSCtl if changing shadow sets */
/* Get Im bits to clear for this interrupt */
/* this must include at least the IM bit */
/* for the current interrupt, and may include */
/* others */
/* Clear bits in copy of Status */
6.1.1.3 External Interrupt Controller Mode
External Interrupt Controller Mode redefines the way that the processor interrupt logic is configured to provide sup- port for an external interrupt controller. The interrupt controller is responsible for prioritizing all interrupts, including hardware, software, timer, and performance counter interrupts, and directly supplying to the processor the vector number (and optionally the priority level) of the highest priority interrupt. EIC interrupt mode is in effect if all of the following conditions are true:
• Config3VEIC = 1
• IntCtlVS ≠ 0
• CauseIV = 1
• StatusBEV = 0
In EIC interrupt mode, the processor sends the state of the software interrupt requests (CauseIP1..IP0), the timer inter- rupt request (CauseTI), and the performance counter interrupt request (CausePCI) to the external interrupt controller, where it prioritizes these interrupts in a system-dependent way with other hardware interrupts. The interrupt control-
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ler can be a hard-wired logic block, or it can be configurable based on control and status registers. This allows the interrupt controller to be more specific or more general as a function of the system environment and needs.
The external interrupt controller prioritizes its interrupt requests and produces the priority level and the vector number of the highest priority interrupt to be serviced. The priority level, called the Requested Interrupt Priority Level (RIPL), is a 6-bit encoded value in the range 0..63, inclusive. A value of 0 indicates that no interrupt requests are pending. The values 1..63 represent the lowest (1) to highest (63) RIPL for the interrupt to be serviced. The interrupt controller passes this value on the 6 hardware interrupt lines, which are treated as an encoded value in EIC interrupt mode. There are several implementation options available for the vector offset:
1. The first option is to treat the RIPL value as the vector number for the processor.
2. The second option is to send a separate vector number along with the RIPL to the processor.
3. A third option is to send an entire vector offset along with the RIPL to the processor.
StatusIPL (which overlays StatusIM7..IM2) is interpreted as the Interrupt Priority Level (IPL) at which the processor is currently operating (with a value of zero indicating that no interrupt is currently being serviced). When the interrupt controller requests service for an interrupt, the processor compares RIPL with StatusIPL to determine if the requested interrupt has higher priority than the current IPL. If RIPL is strictly greater than StatusIPL, and interrupts are enabled (StatusIE = 1, StatusEXL = 0, and StatusERL = 0) an interrupt request is signaled to the pipeline. When the processor starts the interrupt exception, it loads RIPL into CauseRIPL (which overlays CauseIP7..IP2) and signals the external interrupt controller to notify it that the request is being serviced. Because CauseRIPL is only loaded by the processor when an interrupt exception is signaled, it is available to software during interrupt processing. The vector number that the EIC passes into the core is combined with the IntCtlVS to determine where the interrupt service routines is located. The vector number is not stored in any software visible register. Some implementations may choose to use the RIPL as the vector number, but this is not a requirement.
In EIC interrupt mode, the external interrupt controller is also responsible for supplying the GPR shadow set number to use when servicing the interrupt. As such, the SRSMap register is not used in this mode, and the mapping of the vectored interrupt to a GPR shadow set is done by programming (or designing) the interrupt controller to provide the correct GPR shadow set number when an interrupt is requested. When the processor loads an interrupt request into CauseRIPL, it also loads the GPR shadow set number into SRSCtlEICSS, which is copied to SRSCtlCSS when the inter- rupt is serviced.
The operation of EIC interrupt mode is shown pictorially in Figure 6-2.
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6.1 Interrupts
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Interrupts and Exceptions
Figure 6-2 Interrupt Generation for External Interrupt Controller Interrupt Mode
Encode
Latch
Compare
Generate
Cause TI
CausePCI CauseIP1 CauseIP0
Interrupt Service Started
Requested IPL
Any Request
StatusIE
IntCtlVS
Interrupt Request
Interrupt Exception
Load Fields
Option 1 & 2 – Exception Vector Offset
Shadow Set Number
Option2- Explicit Vector Number
Option1 – RIPL as Vector Number
Option3 – Explicit Vector Offset
A typical software handler for EIC interrupt mode bypasses the entire sequence of code following the IVexception label shown for the compatibility mode handler above. Instead, the hardware performs the prioritization, dispatching directly to the interrupt processing routine. Unlike the compatibility mode examples, an EIC interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers. As such, the SimpleInterrupt code shown above need not save the GPRs.
A nested interrupt is similar to that shown for compatibility mode, but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set. It also need only copy CauseRIPL to StatusIPL to prevent lower priority interrupts from interrupting the handler. Such a routine might look as follows:
NestedException:
/*
* Nested exceptions typically require saving the EPC, Status,and SRSCtl registers,
* setting up the appropriate GPR shadow set for the routine, disabling
* the appropriate IM bits in Status to prevent an interrupt loop, putting
* the processor in kernel mode, and re-enabling interrupts. The sample code
* below can not cover all nuances of this processing and is intended only
* to demonstrate the concepts.
*/
/* Use the current GPR shadow set, and setup software context */
mfc0 k1, C0_Cause
mfc0 k0, C0_EPC
srl k1, k1, S_CauseRIPL sw k0, EPCSave
mfc0 k0, C0_Status
/* Read Cause to get RIPL value */
/* Get restart address */
/* Right justify RIPL field */
/* Save in memory */
/* Get Status value */
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RIPL
>
IPL?
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Shadow Set Mapping
SRSCtlEICSS
CauseRIPL
Interrupt Sources
External Interrupt Controller
Offset Genera- tor
StatusIPL

sw k0, StatusSave /* Save in memory */
ins k0, k1, S_StatusIPL, 6 /* Set IPL to RIPL in copy of Status */ mfc0 k1, C0_SRSCtl /* Save SRSCtl if changing shadow sets */ sw k1, SRSCtlSave
/* If switching shadow sets, write new value to SRSCtlPSS here */
ins k0, zero, S_StatusEXL, (W_StatusKSU+W_StatusERL+W_StatusEXL)
/* Clear KSU, ERL, EXL bits in k0 */ mtc0 k0, C0_Status /* Modify IPL, switch to kernel mode, */
/* re-enable interrupts */
/*
* If switching shadow sets, clear only KSU above, write target
* address to EPC, and do execute an eret to clear EXL, switch
* shadow sets, and jump to routine
*/
/* Process interrupt here, including clearing device interrupt */
/*
* The interrupt completion code is identical to that shown for VI mode above.
*/
6.1.2 Generation of Exception Vector Offsets for Vectored Interrupts
For vectored interrupts (in either VI or EIC interrupt mode – options 1 & 2), a vector number is produced by the inter- rupt control logic. This number is combined with IntCtlVS to create the interrupt offset, which is added to 0x200 to create the exception vector offset. For VI interrupt mode, the vector number is in the range 0..7, inclusive. For EIC interrupt mode, the vector number is in the range 1..63, inclusive (0 being the encoding for “no interrupt”). The IntCtlVS field specifies the spacing between vector locations. If this value is zero (the default reset state), the vector spacing is zero and the processor reverts to Interrupt Compatibility Mode. A non-zero value enables vectored inter- rupts, and Table 6.4 shows the exception vector offset for a representative subset of the vector numbers and values of the IntCtlVS field.
Table 6.4 Exception Vector Offsets for Vectored Interrupts
6.1 Interrupts
Vector Number
Value of IntCtlVS Field
0b00001
0b00010
0b00100
0b01000
0b10000
0
0x0200
0x0200
0x0200
0x0200
0x0200
1
0x0220
0x0240
0x0280
0x0300
0x0400
2
0x0240
0x0280
0x0300
0x0400
0x0600
3
0x0260
0x02C0
0x0380
0x0500
0x0800
4
0x0280
0x0300
0x0400
0x0600
0x0A00
5
0x02A0
0x0340
0x0480
0x0700
0x0C00
6
0x02C0
0x0380
0x0500
0x0800
0x0E00
7
0x02E0
0x03C0
0x0580
0x0900
0x1000
• • •
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Table 6.4 Exception Vector Offsets for Vectored Interrupts
Vector Number
Value of IntCtlVS Field
0b00001
0b00010
0b00100
0b01000
0b10000
61
0x09A0
0x1140
0x2080
0x3F00
0x7C00
62
0x09C0
0x1180
0x2100
0x4000
0x7E00
63
0x09E0
0x11C0
0x2180
0x4100
0x8000
The general equation for the exception vector offset for a vectored interrupt is:
vectorOffset ← 0x200 + (vectorNumber × (IntCtlVS || 0b00000)) 6.1.2.1 Software Hazards and the Interrupt System
Software writes to certain coprocessor 0 register fields may change the conditions under which an interrupt is taken. This creates a coprocessor 0 (CP0) hazard, as described in the chapter “CP0 Hazards” on page 79. In Release 1 of the Architecture, there was no architecturally-defined method for bounding the number of instructions which would be executed after the instruction which caused the interrupt state change and before the change to the interrupt state was seen. In Release 2 of the Architecture, the EHB instruction was added, and this instruction can be used by software to clear the hazard.
Table 6.5 lists the CP0 register fields which can cause a change to the interrupt state (either enabling interrupts which were previously disabled or disabling interrupts which were previously enabled).
Table 6.5 Interrupt State Changes Made Visible by EHB
Instruction(s)
CP0 Register Written
CP0 Register Field(s) Modified
MTC0
Status
IM, IPL, ERL, EXL, IE
EI, DI
Status
IE
MTC0
Cause
IP1..0
MTC0
PerfCnt Control
IE
MTC0
PerfCnt Counter
Event Count
An EHB, executed after one of these fields is modified by the listed instruction, makes the change to the interrupt state visible no later than the instruction following the EHB.
In the following example, a change to the CauseIM field is made visible by an EHB:
mfc0 k0, C0_Status
ins k0, zero, S_StatusIM4, 1
mtc0 k0, C0_Status
ehb
/* Change to the interrupt state is seen no later than this instruction */
/* Clear bit 4 of the IM field */
/* Re-write the register */
/* Clear the hazard */
Similarly, the effects of an DI instruction are made visible by an EHB:
di /* Disable interrupts */
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ehb /* Clear the hazard */
/* Change to the interrupt state is seen no later than this instruction */
6.2 Exceptions
Normal execution of instructions may be interrupted when an exception occurs. Such events can be generated as a by-product of instruction execution (e.g., an integer overflow caused by an add instruction or a TLB miss caused by a load instruction), or by an event not directly related to instruction execution (e.g., an external interrupt). When an exception occurs, the processor stops processing instructions, saves sufficient state to resume the interrupted instruc- tion stream, enters Kernel Mode, and starts a software exception handler. The saved state and the address of the soft- ware exception handler are a function of both the type of exception, and the current state of the processor.
6.2.1 Exception Priority
Table 6.6 lists all possible exceptions, and the relative priority of each, highest to lowest. Table 6.6 Priority of Exceptions
6.2 Exceptions
Exception
Description
Type
Reset
The Cold Reset signal was asserted to the processor
Asynchronous Reset
Soft Reset
The Reset signal was asserted to the processor
Debug Single Step
An EJTAG Single Step occurred. Prioritized above other excep- tions, including asynchronous exceptions, so that one can sin- gle-step into interrupt (or other asynchronous) handlers.
Synchronous Debug
Debug Interrupt
An EJTAG interrupt (EjtagBrk or DINT) was asserted.
Asynchronous Debug
Imprecise Debug Data Break
An imprecise EJTAG data break condition was asserted.
Nonmaskable Interrupt (NMI)
The NMI signal was asserted to the processor.
Asynchronous
Machine Check
An internal inconsistency was detected by the processor.
Interrupt
An enabled interrupt occurred.
Deferred Watch
A watch exception, deferred because EXL was one when the exception was detected, was asserted after EXL went to zero.
Debug Instruction Break
An EJTAG instruction break condition was asserted. Prioritized above instruction fetch exceptions to allow break on illegal instruc- tion addresses.
Synchronous Debug
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Table 6.6 Priority of Exceptions
Exception
Description
Type
Watch – Instruction fetch
A watch address match was detected on an instruction fetch. Prior- itized above instruction fetch exceptions to allow watch on illegal instruction addresses.
Synchronous
Address Error – Instruction fetch
A non-word-aligned address was loaded into PC.
TLB Refill – Instruction fetch
A TLB miss occurred on an instruction fetch.
TLB Invalid – Instruction fetch
The valid bit was zero in the TLB entry mapping the address refer- enced by an instruction fetch.
TLB Execute-Inhibit
An instruction fetch matched a valid TLB entry which had the XI bit set.
Cache Error – Instruction fetch
A cache error occurred on an instruction fetch.
Bus Error – Instruction fetch
A bus error occurred on an instruction fetch.
SDBBP
An EJTAG SDBBP instruction was executed.
Synchronous Debug
Instruction Validity Exceptions
An instruction could not be completed because it was not allowed access to the required resources, or was illegal: Coprocessor Unus- able, Reserved Instruction. If both exceptions occur on the same instruction, the Coprocessor Unusable Exception takes priority over the Reserved Instruction Exception.
Synchronous
Execution Exception
An instruction-based exception occurred: Integer overflow, trap, system call, breakpoint, floating point, coprocessor 2 exception.
Precise Debug Data Break
A precise EJTAG data break on load/store (address match only) or a data break on store (address+data match) condition was asserted. Prioritized above data fetch exceptions to allow break on illegal data addresses.
Synchronous Debug
Watch – Data access
A watch address match was detected on the address referenced by a load or store. Prioritized above data fetch exceptions to allow watch on illegal data addresses.
Synchronous
Address error – Data access
An unaligned address, or an address that was inaccessible in the current processor mode was referenced, by a load or store instruc- tion
TLB Refill – Data access
A TLB miss occurred on a data access
TLB Invalid – Data access
The valid bit was zero in the TLB entry mapping the address refer- enced by a load or store instruction
TLB Read-Inhibit
A data read access matched a valid TLB entry whose RI bit is set.
TLB Modified – Data access
The dirty bit was zero in the TLB entry mapping the address refer- enced by a store instruction
Cache Error – Data access
A cache error occurred on a load or store data reference
Synchronous or Asynchronous
Bus Error – Data access
A bus error occurred on a load or store data reference
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Table 6.6 Priority of Exceptions
The “Type” column of Table 6.7 describes the type of exception. Table 6.8 explains the characteristics of each excep- tion type.
Table 6.7 Exception Type Characteristics
6.2 Exceptions
Exception
Description
Type
Precise Debug Data Break
A precise EJTAG data break on load (address+data match only) condition was asserted. Prioritized last because all aspects of the data fetch must complete in order to do data match.
Synchronous Debug
Exception Type
Characteristics
Asynchronous Reset
Denotes a reset-type exception that occurs asynchronously to instruction execution. These exceptions always have the highest priority to guarantee that the processor can always be placed in a runnable state.
Asynchronous Debug
Denotes an EJTAG debug exception that occurs asynchronously to instruction execu- tion. These exceptions have very high priority with respect to other exceptions because of the desire to enter Debug Mode, even in the presence of other exceptions, both asyn- chronous and synchronous.
Asynchronous
Denotes any other type of exception that occurs asynchronously to instruction execu- tion. These exceptions are shown with higher priority than synchronous exceptions mainly for notational convenience. If one thinks of asynchronous exceptions as occur- ring between instructions, they are either the lowest priority relative to the previous instruction, or the highest priority relative to the next instruction. The ordering of the table above considers them in the second way.
Synchronous Debug
Denotes an EJTAG debug exception that occurs as a result of instruction execution, and is reported precisely with respect to the instruction that caused the exception. These exceptions are prioritized above other synchronous exceptions to allow entry to Debug Mode, even in the presence of other exceptions.
Synchronous
Denotes any other exception that occurs as a result of instruction execution, and is reported precisely with respect to the instruction that caused the exception. These exceptions tend to be prioritized below other types of exceptions, but there is a relative priority of synchronous exceptions with each other.
6.2.2 Exception Vector Locations
The Reset, Soft Reset, and NMI exceptions are always vectored to location 0xBFC0.0000. EJTAG Debug excep- tions are vectored to location 0xBFC0.0480, or to location 0xFF20.0200 if the ProbTrap bit is zero or one, respectively, in the EJTAG_Control_register.
Addresses for all other exceptions are a combination of a vector offset and a vector base address. In Release 1 of the architecture, the vector base address was fixed. In Release 2 of the architecture (and subsequent releases), software is allowed to specify the vector base address via the EBase register for exceptions that occur when StatusBEV equals 0. Table 6.8 gives the vector base address as a function of the exception and whether the BEV bit is set in the Status reg- ister. Table 6.9 gives the offsets from the vector base address as a function of the exception. Note that the IV bit in the Cause register causes Interrupts to use a dedicated exception vector offset, rather than the general exception vector. For implementations of Release 2 of the Architecture (and subsequent releases), Table 6.4 gives the offset from the base address in the case where StatusBEV = 0 and CauseIV = 1. For implementations of Release 1 of the architecture in which CauseIV = 1, the vector offset is as if IntCtlVS were 0.
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Table 6.10 combines these two tables into one that contains all possible vector addresses as a function of the state that can affect the vector selection. To avoid complexity in the table, the vector address value assumes that the EBase reg- ister, as implemented in Release 2 devices, is not changed from its reset state and that IntCtlVS is 0.
In Release 2 of the Architecture (and subsequent releases), software must guarantee that EBase15..12 contains zeros in all bit positions less than or equal to the most significant bit in the vector offset. This situation can only occur when a vector offset greater than 0xFFF is generated when an interrupt occurs with VI or EIC interrupt mode enabled. The operation of the processor is UNDEFINED if this condition is not met.
Table 6.8 Exception Vector Base Addresses
Exception
StatusBEV
0
1
Reset, Soft Reset, NMI
0xBFC0.0000
EJTAG Debug (with ProbTrap = 0 in the EJTAG_Control_register)
0xBFC0.0480
EJTAG Debug (with ProbTrap = 1 in the EJTAG_Control_register)
0xFF20.0200
Cache Error
For Release 1 of the architecture:
0xA000.0000
For Release 2 of the architecture:
EBase31..30 || 1 || EBase28..12 || 0x000
Note that EBase31..30 have the fixed value 0b10
0xBFC0.0200
Other
For Release 1 of the architecture:
0x8000.0000
For Release 2 of the architecture:
EBase31..12 || 0x000 Note that EBase31..30 have the fixed value 0b10
0xBFC0.0200
Table 6.9 Exception Vector Offsets
Exception
Vector Offset
TLB Refill, EXL = 0
0x000
Cache error
0x100
General Exception
0x180
Interrupt, CauseIV = 1
0x200 (In Release 2 implementa- tions, this is the base of the vectored interrupt table when StatusBEV = 0)
Reset, Soft Reset, NMI
None (Uses Reset Base Address)
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Table 6.10 Exception Vectors
6.2 Exceptions
Exception
StatusBEV
StatusEXL
CauseIV
EJTAG ProbTrap
Vector
For Release 2 Implementations, assumes that EBase retains its reset state and that IntCtlVS = 0
Reset, Soft Reset, NMI
x
x
x
x
0xBFC0.0000
EJTAG Debug
x
x
x
0
0xBFC0.0480
EJTAG Debug
x
x
x
1
0xFF20.0200
TLB Refill
0
0
x
x
0x8000.0000
TLB Refill
0
1
x
x
0x8000.0180
TLB Refill
1
0
x
x
0xBFC0.0200
TLB Refill
1
1
x
x
0xBFC0.0380
Cache Error
0
x
x
x
0xA000.0100
Cache Error
1
x
x
x
0xBFC0.0300
Interrupt
0
0
0
x
0x8000.0180
Interrupt
0
0
1
x
0x8000.0200
Interrupt
1
0
0
x
0xBFC0.0380
Interrupt
1
0
1
x
0xBFC0.0400
All others
0
x
x
x
0x8000.0180
All others
1
x
x
x
0xBFC0.0380
‘x’ denotes don’t care
6.2.3 General Exception Processing
With the exception of Reset, Soft Reset, NMI, cache error, and EJTAG Debug exceptions, which have their own spe- cial processing as described below, exceptions have the same basic processing flow:
• If the EXL bit in the Status register is zero, the EPC register is loaded with the PC at which execution will be restarted and the BD bit is set appropriately in the Cause register (see Table 9.30 on page 134). The value loaded into the EPC register is dependent on whether the processor implements the MIPS16 ASE, and whether the instruction is in the delay slot of a branch or jump which has delay slots. Table 6.11 shows the value stored in each of the CP0 PC registers, including EPC. For implementations of Release 2 of the Architecture if StatusBEV = 0, the CSS field in the SRSCtl register is copied to the PSS field, and the CSS value is loaded from the appro- priate source.
If the EXL bit in the Status register is set, the EPC register is not loaded and the BD bit is not changed in the Cause register. For implementations of Release 2 of the Architecture, the SRSCtl register is not changed.
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.
Table 6.11 Value Stored in EPC, ErrorEPC, or DEPC on an Exception
MIPS16 Implemented?
In Branch/Jump Delay Slot?
Value stored in EPC/ErrorEPC/DEPC
No
No
Address of the instruction
No
Yes
Address of the branch or jump instruction (PC-4)
Yes
No
Upper 31 bits of the address of the instruction, combined with the ISA Mode bit
Yes
Yes
Upper 31 bits of the branch or jump instruction (PC-2 in the MIPS16 ISA Mode and PC-4 in the 32-bit ISA Mode), combined with the ISA Mode bit
• The CE, and ExcCode fields of the Cause registers are loaded with the values appropriate to the exception. The CE field is loaded, but not defined, for any exception type other than a coprocessor unusable exception.
• The EXL bit is set in the Status register.
• The processor is started at the exception vector.
The value loaded into EPC represents the restart address for the exception and need not be modified by exception handler software in the normal case. Software need not look at the BD bit in the Cause register unless it wishes to identify the address of the instruction that actually caused the exception.
Note that individual exception types may load additional information into other registers. This is noted in the descrip- tion of each exception type below.
Operation:
/* If StatusEXL is 1, all exceptions go through the general exception vector */ /* and neither EPC nor CauseBD nor SRSCtl are modified */
if StatusEXL = 1 then
vectorOffset ← 0x180 else
if InstructionInBranchDelaySlot then
EPC ← restartPC/* PC of branch/jump */ CauseBD ← 1
else
EPC ← restartPC /* PC of instruction */ CauseBD ← 0
endif
/* Compute vector offsets as a function of the type of exception */ NewShadowSet ← SRSCtlESS /* Assume exception, Release 2 only */ if ExceptionType = TLBRefill then
vectorOffset ← 0x000
elseif (ExceptionType = Interrupt) then
if (CauseIV = 0) then vectorOffset ← 0x180
else
if (StatusBEV = 1) or (IntCtlVS = 0) then
vectorOffset ← 0x200 else
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if Config3VEIC = 1 then if (EIC_option1)
VecNum ← CauseRIPL elseif (EIC_option2)
VecNum ← EIC_VecNum_Signal endif
NewShadowSet ← SRSCtlEICSS else
VecNum ← VIntPriorityEncoder()
NewShadowSet ← SRSMapIPL×4+3..IPL×4 endif
if (EIC_option3)
vectorOffset ← EIC_VectorOffset_Signal
else
vectorOffset ← 0x200 + (VecNum × (IntCtlVS || 0b00000))
endif
endif /* if (StatusBEV = 1) or (IntCtlVS = 0) then */
endif /* if (CauseIV = 0) then */
endif /* elseif (ExceptionType = Interrupt) then */
/* Update the shadow set information for an implementation of */
/* Release 2 of the architecture */
if (ArchitectureRevision ≥ 2) and (SRSCtlHSS > 0) and (StatusBEV = 0) then
SRSCtlPSS ← SRSCtlCSS
SRSCtlCSS ← NewShadowSet endif
endif /* if StatusEXL = 1 then */
CauseCE ← FaultingCoprocessorNumber CauseExcCode ← ExceptionType StatusEXL ← 1
/* Calculate the vector base address */ if StatusBEV = 1 then
vectorBase ← 0xBFC0.0200 else
if ArchitectureRevision ≥ 2 then
/* The fixed value of EBase31..30 forces the base to be in kseg0 or kseg1 */ vectorBase ← EBase31..12 || 0x000
else
vectorBase ← 0x8000.0000
endif endif
/* Exception PC is the sum of vectorBase and vectorOffset. Vector */ /* offsets > 0xFFF (vectored or EIC interrupts only), require */
/* that EBase15..12 have zeros in each bit position less than or */
/* equal to the most significant bit position of the vector offset */ PC ← vectorBase31..30 || (vectorBase29..0 + vectorOffset29..0)
/* No carry between bits 29 and 30 */
6.2.4 EJTAG Debug Exception
An EJTAG Debug Exception occurs when one of a number of EJTAG-related conditions is met. Refer to the EJTAG Specification for details of this exception.
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Interrupts and Exceptions
Entry Vector Used
0xBFC0 0480 if the ProbTrap bit is zero in the EJTAG_Control_register; 0xFF20 0200 if the ProbTrap bit is one.
6.2.5 Reset Exception
A Reset Exception occurs when the Cold Reset signal is asserted to the processor. This exception is not maskable. When a Reset Exception occurs, the processor performs a full reset initialization, including aborting state machines, establishing critical state, and generally placing the processor in a state in which it can execute instructions from uncached, unmapped address space. On a Reset Exception, only the following registers have defined state:
• The Random register is initialized to the number of TLB entries – 1.
• The Wired register is initialized to zero.
• The Config, Config1, Config2, and Config3 registers are initialized with their boot state.
• The RP, BEV, TS, SR, NMI, and ERL fields of the Status register are initialized to a specified state.
• Watch register enables and Performance Counter register interrupt enables are cleared.
• The ErrorEPC register is loaded with the restart PC, as described in Table 6.11. Note that this value may or may not be predictable if the Reset Exception was taken as the result of power being applied to the processor because PC may not have a valid value in that case. In some implementations, the value loaded into ErrorEPC register may not be predictable on either a Reset or Soft Reset Exception.
• PC is loaded with 0xBFC0 0000. Cause Register ExcCode Value
None
Additional State Saved
None
Entry Vector Used
Reset (0xBFC0 0000) Operation
Random ← TLBEntries – 1 PageMaskMaskX ← 0 PageGrainESP ← 0
Wired ← 0
# 1KB page support implemented
# 1KB page support implemented
HWREna ← 0
EntryHiVPN2X ← 0
StatusRP ← 0
StatusBEV ← 1
StatusTS ← 0
StatusSR ← 0
StatusNMI ← 0
StatusERL ← 1
IntCtlVS ← 0
SRSCtlHSS ← HighestImplementedShadowSet
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SRSCtlESS ← 0 SRSCtlPSS ← 0 SRSCtlCSS ← 0 SRSMap ← 0 CauseDC ← 0
EBaseExceptionBase ← 0
Config ← ConfigurationState
ConfigK0 ← 2
Config1 ← ConfigurationState Config2 ← ConfigurationState Config3 ← ConfigurationState WatchLo[n]I ← 0
WatchLo[n]R ← 0
WatchLo[n]W ← 0 PerfCnt.Control[n]IE ← 0
if InstructionInBranchDelaySlot then
# Suggested – see Config register description
# For all implemented Watch registers
# For all implemented Watch registers
# For all implemented Watch registers
# For all implemented PerfCnt registers
ErrorEPC ← restartPC # PC of branch/jump else
ErrorEPC ← restartPC # PC of instruction endif
PC ← 0xBFC0 0000 6.2.6 Soft Reset Exception
A Soft Reset Exception occurs when the Reset signal is asserted to the processor. This exception is not maskable. When a Soft Reset Exception occurs, the processor performs a subset of the full reset initialization. Although a Soft Reset Exception does not unnecessarily change the state of the processor, it may be forced to do so in order to place the processor in a state in which it can execute instructions from uncached, unmapped address space. Since bus, cache, or other operations may be interrupted, portions of the cache, memory, or other processor state may be incon- sistent.
The primary difference between the Reset and Soft Reset Exceptions is in actual use. The Reset Exception is typically used to initialize the processor on power-up, while the Soft Reset Exception is typically used to recover from a non-responsive (hung) processor. The semantic difference is provided to allow boot software to save critical copro- cessor 0 or other register state to assist in debugging the potential problem. As such, the processor may reset the same state when either reset signal is asserted, but the interpretation of any state saved by software may be very different.
In addition to any hardware initialization required, the following state is established on a Soft Reset Exception:
• The RP, BEV, TS, SR, NMI, and ERL fields of the Status register are initialized to a specified state.
• Watch register enables and Performance Counter register interrupt enables are cleared.
• The ErrorEPC register is loaded with the restart PC, as described in Table 6.11.
• PC is loaded with 0xBFC0 0000. Cause Register ExcCode Value
None
Additional State Saved
None
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Entry Vector Used
Reset (0xBFC0 0000) Operation
PageMaskMaskX ← 0
PageGrainESP ← 0
EntryHiVPN2X ← 0
ConfigK0 ← 2
StatusRP ← 0
StatusBEV ← 1
StatusTS ← 0
StatusSR ← 1
StatusNMI ← 0
StatusERL ← 1
WatchLo[n]I ← 0
WatchLo[n]R ← 0
WatchLo[n]W ← 0 PerfCnt.Control[n]IE ← 0
if InstructionInBranchDelaySlot then
# 1KB page support implemented
# 1KB page support implemented
# 1KB page support implemented
# Suggested – see Config register description
# For all implemented Watch registers
# For all implemented Watch registers
# For all implemented Watch registers
# For all implemented PerfCnt registers
ErrorEPC ← restartPC # PC of branch/jump else
ErrorEPC ← restartPC # PC of instruction endif
PC ← 0xBFC0 0000
6.2.7 Non Maskable Interrupt (NMI) Exception
A non maskable interrupt exception occurs when the NMI signal is asserted to the processor.
Although described as an interrupt, it is more correctly described as an exception because it is not maskable. An NMI occurs only at instruction boundaries, so does not do any reset or other hardware initialization. The state of the cache, memory, and other processor state is consistent and all registers are preserved, with the following exceptions:
• The BEV, TS, SR, NMI, and ERL fields of the Status register are initialized to a specified state.
• The ErrorEPC register is loaded with restart PC, as described in Table 6.11.
• PC is loaded with 0xBFC0 0000. Cause Register ExcCode Value
None
Additional State Saved
None
Entry Vector Used
Reset (0xBFC0 0000) Operation
StatusBEV ← 1 StatusTS ← 0 StatusSR ← 0 StatusNMI ← 1
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StatusERL ← 1
if InstructionInBranchDelaySlot then
ErrorEPC ← restartPC # PC of branch/jump else
ErrorEPC ← restartPC # PC of instruction endif
PC ← 0xBFC0 0000
6.2.8 Machine Check Exception
A machine check exception occurs when the processor detects an internal inconsistency. The following conditions cause a machine check exception:
• Detection of multiple matching entries in the TLB in a TLB-based MMU.
Cause Register ExcCode Value
MCheck (See Table 9.31 on page 138) Additional State Saved
Depends on the condition that caused the exception. See the descriptions above.
Entry Vector Used
General exception vector (offset 0x180)
6.2.9 Address Error Exception
An address error exception occurs under the following circumstances:
• An instruction is fetched from an address that is not aligned on a word boundary.
• A load or store word instruction is executed in which the address is not aligned on a word boundary.
• A load or store halfword instruction is executed in which the address is not aligned on a halfword boundary.
• A reference is made to a kernel address space from User Mode or Supervisor Mode.
• A reference is made to a supervisor address space from User Mode.
Note that in the case of an instruction fetch that is not aligned on a word boundary, the PC is updated before the con- dition is detected. Therefore, both EPC and BadVAddr point at the unaligned instruction address.
Cause Register ExcCode Value
AdEL: Reference was a load or an instruction fetch AdES: Reference was a store
See Table 9.31 on page 138.
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Additional State Saved
Register State
BadVAddr ContextVPN2 EntryHiVPN2 EntryLo0 EntryLo1
Value
failing address UNPREDICTABLE UNPREDICTABLE UNPREDICTABLE UNPREDICTABLE
Entry Vector Used
General exception vector (offset 0x180)
6.2.10 TLB Refill Exception
A TLB Refill exception occurs in a TLB-based MMU when no TLB entry matches a reference to a mapped address space and the EXL bit is zero in the Status register. Note that this is distinct from the case in which an entry matches but has the valid bit off, in which case a TLB Invalid exception occurs.
Cause Register ExcCode Value
TLBL: Reference was a load or an instruction fetch TLBS: Reference was a store
See Table 9.31 on page 138.
Additional State Saved
Register State
BadVAddr Context
EntryHi
EntryLo0 EntryLo1
Entry Vector Used
Value
Failing address
If Config3CTXTC bit is set, then the bits of the Context reg- ister corresponding to the set bits of the VirtualIndex field of the ContextConfig register are loaded with the high-order bits of the virtual address that missed.
If Config3CTXTC bit is clear, then the BadVPN2 field con- tains VA31..13 of the failing address
The VPN2 field contains VA31..13 of the failing address; the ASID field contains the ASID of the reference that missed.
UNPREDICTABLE UNPREDICTABLE
• TLB Refill vector (offset 0x000) if StatusEXL = 0 at the time of exception.
• General exception vector (offset 0x180) if StatusEXL = 1 at the time of exception
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6.2.11 Execute-Inhibit Exception
An Execute-Inhibit exception occurs when the virtual address of an instruction fetch matches a TLB entry whose XI bit is set. This exception type can only occur if the XI bit is implemented within the TLB and is enabled, this is denoted by the PageGrainXIE bit.
Cause Register ExcCode Value if PageGrainIEC == 0 TLBL
if PageGrainIEC == 1 TLBXI See Table 9.31 on page 138.
Additional State Saved
Register State
BadVAddr Context
EntryHi
EntryLo0 EntryLo1
Entry Vector Used
Value
6.2 Exceptions
Failing address
If Config3CTXTC bit is set, then the bits of the Context reg- ister corresponding to the set bits of the VirtualIndex field of the ContextConfig register are loaded with the high-order bits of the virtual address that missed.
If Config3CTXTC bit is clear, then the BadVPN2 field con- tains VA31..13 of the failing address
The VPN2 field contains VA31..13 of the failing address; the ASID field contains the ASID of the reference that missed.
UNPREDICTABLE UNPREDICTABLE
General exception vector (offset 0x180)
6.2.12 Read-Inhibit Exception
An Read-Inhibit exception occurs when the virtual address of a memory load reference matches a TLB entry whose RI bit is set. This exception type can only occur if the RI bit is implemented within the TLB and is enabled, this is denoted by the PageGrainRIE bit. MIPS16 PC-relative loads are a special case and are not affected by the RI bit.
Cause Register ExcCode Value if PageGrainIEC == 0 TLBL
if PageGrainIEC == 1 TLBRI See Table 9.31 on page 138.
Additional State Saved
Register State
BadVAddr
Value
Failing address
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Register State
Context
EntryHi
EntryLo0 EntryLo1
Entry Vector Used
Value
If Config3CTXTC bit is set, then the bits of the Context reg- ister corresponding to the set bits of the VirtualIndex field of the ContextConfig register are loaded with the high-order bits of the virtual address that missed.
If Config3CTXTC bit is clear, then the BadVPN2 field con- tains VA31..13 of the failing address
The VPN2 field contains VA31..13 of the failing address; the ASID field contains the ASID of the reference that missed.
UNPREDICTABLE UNPREDICTABLE
General exception vector (offset 0x180)
6.2.13 TLB Invalid Exception
A TLB invalid exception occurs when a TLB entry matches a reference to a mapped address space, but the matched entry has the valid bit off.
Note that the condition in which no TLB entry matches a reference to a mapped address space and the EXL bit is one in the Status register is indistinguishable from a TLB Invalid Exception, in the sense that both use the general excep- tion vector and supply an ExcCode value of TLBL or TLBS. The only way to distinguish these two cases is by prob- ing the TLB for a matching entry (using TLBP).
If the RI and XI bits are implemented within the TLB and the PageGrainIEC bit is clear, then this exception also occurs if a valid, matching TLB entry is found with the RI bit set on a memory load reference, or with the XI bit set
on an instruction fetch memory reference. MIPS16 PC-relative loads are a special case and are not affected by the RI bit.
Cause Register ExcCode Value
TLBL: Reference was a load or an instruction fetch TLBS: Reference was a store
See Table 9.30 on page 134.
Additional State Saved
Register State
BadVAddr Context
Value
Failing address
If Config3CTXTC bit is set, then the bits of the Context reg- ister corresponding to the set bits of the VirtualIndex field of the ContextConfig register are loaded with the high-order bits of the virtual address that missed.
If Config3CTXTC bit is clear, then the BadVPN2 field con- tains VA31..13 of the failing address
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Register State
EntryHi
EntryLo0 EntryLo1
Entry Vector Used
Value
The VPN2 field contains VA31..13 of the failing address; the ASID field contains the ASID of the reference that missed.
UNPREDICTABLE UNPREDICTABLE
6.2 Exceptions
General exception vector (offset 0x180)
6.2.14 TLB Modified Exception
A TLB modified exception occurs on a store reference to a mapped address when the matching TLB entry is valid, but the entry’s D bit is zero, indicating that the page is not writable.
Cause Register ExcCode Value Mod (See Table 9.30 on page 134)
Additional State Saved
Register State
BadVAddr Context
EntryHi
EntryLo0 EntryLo1
Entry Vector Used
Value
Failing address
If Config3CTXTC bit is set, then the bits of the Context reg- ister corresponding to the set bits of the VirtualIndex field of the ContextConfig register are loaded with the high-order bits of the virtual address that missed.
If Config3CTXTC bit is clear, then the BadVPN2 field con- tains VA31..13 of the failing address
The VPN2 field contains VA31..13 of the failing address; the ASID field contains the ASID of the reference that missed.
UNPREDICTABLE UNPREDICTABLE
General exception vector (offset 0x180)
6.2.15 Cache Error Exception
A cache error exception occurs when an instruction or data reference detects a cache tag or data error, or a parity or ECC error is detected on the system bus when a cache miss occurs. This exception is not maskable. Because the error was in a cache, the exception vector is to an unmapped, uncached address.
Cause Register ExcCode Value N/A
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Additional State Saved
Entry Vector Used
Cache error vector (offset 0x100)
Operation
Register State
CacheErr ErrorEPC
Value
Error state Restart PC
CacheErr ← ErrorState
StatusERL ← 1
if InstructionInBranchDelaySlot then
ErrorEPC ← restartPC # PC of branch/jump else
ErrorEPC ← restartPC # PC of instruction endif
if StatusBEV = 1 then
PC ← 0xBFC0 0200 + 0x100
else
if ArchitectureRevision ≥ 2 then
/* The fixed value of EBase31..30 and bit 29 forced to a 1 puts the */ /* vector in kseg1 */
PC ← EBase31..30 || 1 || EBase28..12 || 0x100
else
PC ← 0xA000 0000 + 0x100
endif endif
6.2.16 Bus Error Exception
A bus error occurs when an instruction, data, or prefetch access makes a bus request (due to a cache miss or an uncacheable reference) and that request is terminated in an error. Note that parity errors detected during bus transac- tions are reported as cache error exceptions, not bus error exceptions.
Cause Register ExcCode Value
IBE: Error on an instruction reference DBE: Error on a data reference
See Table 9.31 on page 138.
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
6.2.17 Integer Overflow Exception
An integer overflow exception occurs when selected integer instructions result in a 2’s complement overflow.
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Cause Register ExcCode Value Ov (See Table 9.31 on page 138)
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
6.2.18 Trap Exception
A trap exception occurs when a trap instruction results in a TRUE value.
Cause Register ExcCode Value Tr (See Table 9.31 on page 138)
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
6.2.19 System Call Exception
A system call exception occurs when a SYSCALL instruction is executed.
Cause Register ExcCode Value Sys (See Table 9.30 on page 134)
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
6.2.20 Breakpoint Exception
A breakpoint exception occurs when a BREAK instruction is executed.
Cause Register ExcCode Value Bp (See Table 9.31 on page 138)
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
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6.2.21 Reserved Instruction Exception
A Reserved Instruction Exception occurs if any of the following conditions is true:
• An instruction was executed that specifies an encoding of the opcode field that is flagged with “∗” (reserved),
“β” (higher-order ISA), or an unimplemented “ε” (ASE).
• An instruction was executed that specifies a SPECIAL opcode encoding of the function field that is flagged with
“∗” (reserved), or “β” (higher-order ISA).
• An instruction was executed that specifies a REGIMM opcode encoding of the rt field that is flagged with “∗”
(reserved).
• An instruction was executed that specifies an unimplemented SPECIAL2 opcode encoding of the function field
that is flagged with an unimplemented “θ” (partner available), or an unimplemented “σ” (EJTAG).
• An instruction was executed that specifies a COPz opcode encoding of the rs field that is flagged with “∗” (reserved), “β” (higher-order ISA), or an unimplemented “ε” (ASE), assuming that access to the coprocessor is allowed. If access to the coprocessor is not allowed, a Coprocessor Unusable Exception occurs instead. For the COP1 opcode, some implementations of previous ISAs reported this case as a Floating Point Exception, setting the Unimplemented Operation bit in the Cause field of the FCSR register.
• An instruction was executed that specifies an unimplemented COP0 opcode encoding of the function field when rs is CO that is flagged with “∗” (reserved), or an unimplemented “σ” (EJTAG), assuming that access to copro- cessor 0 is allowed. If access to the coprocessor is not allowed, a Coprocessor Unusable Exception occurs instead.
• An instruction was executed that specifies a COP1 opcode encoding of the function field that is flagged with “∗” (reserved), “β” (higher-order ISA), or an unimplemented “ε” (ASE), assuming that access to coprocessor 1 is allowed. If access to the coprocessor is not allowed, a Coprocessor Unusable Exception occurs instead. Some implementations of previous ISAs reported this case as a Floating Point Exception, setting the Unimplemented Operation bit in the Cause field of the FCSR register.
Cause Register ExcCode Value RI (See Table 9.31 on page 138)
Additional State Saved
None
Entry Vector Used
General exception vector (offset 0x180)
6.2.22 Coprocessor Unusable Exception
A coprocessor unusable exception occurs if any of the following conditions is true:
• A COP0 or Cache instruction was executed while the processor was running in a mode other than Debug Mode
or Kernel Mode, and the CU0 bit in the Status register was a zero
• A COP1, COP1X,LWC1, SWC1, LDC1, SDC1 or MOVCI (Special opcode function field encoding) instruction
was executed and the CU1 bit in the Status register was a zero.
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• A COP2, LWC2, SWC2, LDC2, or SDC2 instruction was executed, and the CU2 bit in the Status register was a zero. COP2 instructions include MFC2, DMFC2, CFC2, MFHC2, MTC2, DMTC2, CTC2, MTHC2.
NOTE: In Release 2 of the MIPS32 Architecture, the use of COP3 as a user-defined coprocessor has been removed. The use of COP3 is reserved for the future extension of the architecture.
Cause Register ExcCode Value CpU (See Table 9.30 on page 134)
Additional State Saved
Register State
CauseCE
Entry Vector Used
Value
unit number of the coprocessor being referenced
General exception vector (offset 0x180)
6.2.23 Floating Point Exception
A floating point exception is initiated by the floating point coprocessor to signal a floating point exception.
Register ExcCode Value
FPE (See Table 9.30 on page 134) Additional State Saved
Register State
FCSR
Entry Vector Used
Value
indicates the cause of the floating point exception
6.2 Exceptions
General exception vector (offset 0x180)
6.2.24 Coprocessor 2 Exception
A coprocessor 2 exception is initiated by coprocessor 2 to signal a precise coprocessor 2 exception.
Register ExcCode Value
C2E (See Table 9.30 on page 134) Additional State Saved
Defined by the coprocessor
Entry Vector Used
General exception vector (offset 0x180)
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6.2.25 Watch Exception
The watch facility provides a software debugging vehicle by initiating a watch exception when an instruction or data reference matches the address information stored in the WatchHi and WatchLo registers. A watch exception is taken immediately if the EXL and ERL bits of the Status register are both zero. If either bit is a one at the time that a watch exception would normally be taken, the WP bit in the Cause register is set, and the exception is deferred until both the EXL and ERL bits in the Status register are zero. Software may use the WP bit in the Cause register to determine if the EPC register points at the instruction that caused the watch exception, or if the exception actually occurred while in kernel mode.
If the EXL or ERL bits are one in the Status register and a single instruction generates both a watch exception (which is deferred by the state of the EXL and ERL bits) and a lower-priority exception, the lower priority exception is taken.
Watch exceptions are never taken if the processor is executing in Debug Mode. Should a watch register match while the processor is in Debug Mode, the exception is inhibited and the WP bit is not changed.
It is implementation dependent whether a data watch exception is triggered by a prefetch or cache instruction whose address matches the Watch register address match conditions. A watch triggered by a SC instruction does so even if the store would not complete because the LL bit is zero.
Register ExcCode Value
WATCH (See Table 9.30 on page 134) Additional State Saved
Register State
CauseWP
Entry Vector Used
Value
indicates that the watch exception was deferred until after both StatusEXL and StatusERL were zero. This bit directly causes a watch exception, so software must clear this bit as part of the exception handler to prevent a watch exception loop at the end of the current handler execution.
General exception vector (offset 0x180)
6.2.26 Interrupt Exception
The interrupt exception occurs when an enabled request for interrupt service is made. See Section 6.1 more information.
on page 43 for
Register ExcCode Value
Int (See Table 9.31 on page 138) Additional State Saved
Register State
CauseIP
Value
indicates the interrupts that are pending.
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Entry Vector Used
General exception vector (offset 0x180) if the IV bit in the Cause register is zero. Interrupt vector (offset 0x200) if the IV bit in the Cause register is one.
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Chapter 7
GPR Shadow Registers
The capability in this chapter is targeted at removing the need to save and restore GPRs on entry to high priority inter- rupts or exceptions, and to provide specified processor modes with the same capability. This is done by introducing multiple copies of the GPRs, called shadow sets, and allowing privileged software to associate a shadow set with entry to Kernel Mode via an interrupt vector or exception. The normal GPRs are logically considered shadow set zero.
The number of GPR shadow sets is implementation dependent and may range from one (the normal GPRs) to an architectural maximum of 16. The highest number actually implemented is indicated by the SRSCtlHSS field, and all shadow sets between 0 and SRSCtlHSS, inclusive must be implemented. If this field is zero, only the normal GPRs are implemented.
7.1 Introduction to Shadow Sets
Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to Kernel Mode via an interrupt or exception. Once a shadow set is bound to a Kernel Mode entry condition, reference to GPRs work exactly as one would expect, but they are redirected to registers that are dedicated to that condition. Privileged software may need to reference all GPRs in the register file, even specific shadow registers that are not visible in the current mode. The RDPGPR and WRPGPR instructions are used for this purpose. The CSS field of the SRSCtl register provides the number of the current shadow register set, and the PSS field of the SRSCtl register provides the number of the previous shadow register set (that which was current before the last exception or interrupt occurred).
If the processor is operating in VI interrupt mode, binding of a vectored interrupt to a shadow set is done by writing to the SRSMap register. If the processor is operating in EIC interrupt mode, the binding of the interrupt to a specific shadow set is provided by the external interrupt controller, and is configured in an implementation-dependent way. Binding of an exception or non-vectored interrupt to a shadow set is done by writing to the ESS field of the SRSCtl register. When an exception or interrupt occurs, the value of SRSCtlCSS is copied to SRSCtlPSS, and SRSCtlCSS is set to the value taken from the appropriate source. On an ERET, the value of SRSCtlPSS is copied back into SRSCtlCSS to restore the shadow set of the mode to which control returns. More precisely, the rules for updating the fields in the SRSCtl register on an interrupt or exception are as follows:
1. No field in the SRSCtl register is updated if any of the following conditions are true. In this case, steps 2 and 3 are skipped.
• The exception is one that sets StatusERL: NMI or cache error.
• The exception causes entry into EJTAG Debug Mode
• StatusBEV = 1
• StatusEXL = 1
2. SRSCtlCSS is copied to SRSCtlPSS
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3. SRSCtlCSS is updated from one of the following sources:
• The appropriate field of the SRSMap register, based on IPL, if the exception is an interrupt, CauseIV = 1,
IntCtlVSS ≠ 0, Config3VEIC = 0, and Config3VInt = 1. These are the conditions for a vectored interrupt.
• The EICSS field of the SRSCtl register if the exception is an interrupt, CauseIV = 1, IntCtlVSS ≠ 0, and
Config3VEIC = 1. These are the conditions for a vectored EIC interrupt.
• The ESS field of the SRSCtl register in any other case. This is the condition for a non-interrupt exception, or a non-vectored interrupt.
Similarly, the rules for updating the fields in the SRSCtl register at the end of an exception or interrupt are as follows:
1. No field in the SRSCtl register is updated if any of the following conditions is true. In this case, step 2 is skipped.
• A DERET is executed
• An ERET is executed with StatusERL = 1 or StatusBEV = 1
2. SRSCtlPSS is copied to SRSCtlCSS
These rules have the effect of preserving the SRSCtl register in any case of a nested exception or one which occurs before the processor has been fully initialize (StatusBEV = 1).
Privileged software may switch the current shadow set by writing a new value into SRSCtlPSS, loading EPC with a target address, and doing an ERET.
7.2 Support Instructions
Table 7.1 Instructions Supporting Shadow Sets
Mnemonic
Function
MIPS64 Only?
RDPGPR
Read GPR From Previous Shadow Set
No
WRPGPR
Write GPR to Shadow Set
No
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Chapter 8
CP0 Hazards
8.1 Introduction
Because resources controlled via Coprocessor 0 affect the operation of various pipeline stages of a MIPS32/microMIPS32 processor, manipulation of these resources may produce results that are not detectable by sub- sequent instructions for some number of execution cycles. When no hardware interlock exists between one instruc- tion that causes an effect that is visible to a second instruction, a CP0 hazard exists.
In Release 1 of the MIPS32® Architecture, CP0 hazards were relegated to implementation-dependent cycle-based solutions, primarily based on the SSNOP instruction. Since that time, it has become clear that this is an insufficient and error-prone practice that must be addressed with a firm compact between hardware and software. As such, new instructions have been added to Release 2 of the architecture which act as explicit barriers that eliminate hazards. To the extent that it was possible to do so, the new instructions have been added in such a way that they are back- ward-compatible with existing MIPS processors.
8.2 Types of Hazards
In privileged software, there are two different types of hazards: execution hazards and instruction hazards. Both are defined below.
Implementations using Release 1 of the architecture should refer to their Implementation documentation for the required instruction “spacing” that is required to eliminate these hazards.
Note that, for superscalar MIPS implementations, the number of instructions issued per cycle may be greater than one, and thus that the duration of the hazard in instructions may be greater than the duration in cycles. It is for this reason that MIPS32 Release 1 defines the SSNOP instruction to convert instruction issues to cycles in a superscalar design.
8.2.1 Possible Execution Hazards
Execution hazards are those created by the execution of one instruction, and seen by the execution of another instruc- tion. Table 8.1 lists the possible execution hazards that might exist when there are no hardware interlocks.
Table 8.1 Possible Execution Hazards
Producer → Consumer
Hazard On
Hazards Related to the TLB
MTC0 → TLBR, TLBWI, TLBWR
EntryHi
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Table 8.1 Possible Execution Hazards
Producer → Consumer
Hazard On
MTC0 → TLBWI, TLBWR
EntryLo0, EntryLo1, Index, PageMask, PageGrain
MTCO → TLBWR
Wired
MTC0 → TLBP,
Load or Store Instruction
EntryHiASID
MTC0 → Load/store affected by new state
EntryHiASID, WatchHi, WatchLo, Config
TLBP → MFC0, TLBWI
Index
TLBR → MFC0
EntryHi, EntryLo0, EntryLo1, PageMask
TLBWI, → TLBP, TLBWR TLBR,
Load/store using new TLB entry
TLB entry
Hazards Related to Exceptions or Interrupts
MTC0 → Coprocessor instruction execution depends on the
new value of StatusCU
StatusCU
MTC0 → ERET
DEPC, EPC, ErrorEPC, Status
MTC0 → Interrupted Instruction
CauseIP,
CauseIV Compare, Count, PerfCnt ControlIE, PerfCnt Counter, StatusIE, StatusIM EBase SRSCtl SRSMap
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Table 8.1 Possible Execution Hazards
8.2 Types of Hazards
Producer → Consumer
Hazard On
EI, DI → Interrupted Instruction
StatusIE, StatusIM
Other Hazards
LL → MFC0
LLAddr
MTC0 → CACHE
PageGrain
CACHE → MFC0
TagLo
MTC0 → MFC0
any CoProcessor 0 register
8.2.2 Possible Instruction Hazards
Instruction hazards are those created by the execution of one instruction, and seen by the instruction fetch of another instruction. Table 8.2 lists the possible instruction hazards when there are no hardware interlocks.
Table 8.2 Possible Instruction Hazards
Producer → Consumer
Hazard On
Hazards Related to the TLB
MTC0 → Instruction fetch seeing the new value
EntryHiASID, WatchHi, WatchLo Config
MTC0 → Instruction fetch seeing the new value (including a change to ERL followed by an instruction fetch from the useg
segment)
Status
TLBWI, → Instruction fetch using new TLB entry TLBWR
TLB entry
Hazards Related to Writing the Instruction Stream or Modifying an Instruction Cache Entry
Instruction → Instruction fetch seeing the new stream writes instruction stream
Cache entries
CACHE → Instruction fetch seeing the new instruction stream
Cache entries
Other Hazards
MTC0 → RDPGPR WRPGPR
SRSCtlPSS1
1. This is not precisely a hazard on the instruction fetch. Rather it is a hazard on a modifi- cation to the previous GPR context field, followed by a previous-context reference to the GPRs. It is considered an instruction hazard rather than an execution hazard because some implementation may require that the previous GPR context be established early in the pipeline, and execution hazards are not meant to cover this case.
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CP0 Hazards
8.3 Hazard Clearing Instructions and Events
Table 8.3 lists the instructions designed to eliminate hazards.
Table 8.3 Hazard Clearing Instructions
Mnemonic
Function
Supported Architecture
DERET
Clear both execution and instruction hazards
EJTAG
EHB
Clear execution hazard
Release 2 onwards
ERET
Clear both execution and instruction hazards
All
IRET
Clear both execution and instruction hazards when not chaining to another interrupt.
MCU ASE
JALR.HB
Clear both execution and instruction hazards
Release 2 onwards
JR.HB
Clear both execution and instruction hazards
Release 2 onwards
SSNOP
Superscalar No Operation
Release 1 onwards
SYNCI1
Synchronize caches after instruction stream write
Release 2 onwards
1. SYNCI synchronizes caches after an instruction stream write, and before execution of that instruction stream. As such, it is not precisely a coprocessor 0 hazard, but is included here for completeness.
DERET, ERET, and SSNOP are available in Release 1 of the Architecture; EHB, JALR.HB, JR.HB, and SYNCI were added in Release 2 of the Architecture. In both Release 1 and Release 2 of the Architecture, DERET and ERET clear both execution and instruction hazards and they are the only timing-independent instructions which will do this in both releases of the architecture.
Even though DERET and ERET clear hazards between the execution of the instruction and the target instruction stream, an execution hazard may still be created between a write of the DEPC, EPC, ErrorEPC, or Status registers and the DERET or ERET instruction.
In addition, an exception or interrupt also clears both execution and instruction hazards between the instruction that created the hazard and the first instruction of the exception or interrupt handler. Said another way, no hazards remain visible by the first instruction of an exception or interrupt handler.
8.3.1 MIPS32 Instruction Encoding
The EHB instruction is encoded using a variant of the NOP/SSNOP encoding. This encoding was chosen for compat- ibility with the Release 1 SSNOP instruction, such that existing software may be modified to be compatible with both Release 1 and Release 2 implementations. See the EHB instruction description for additional information.
The JALR.HB and JR.HB instructions are encoding using bit 10 of the hint field of the JALR and JR instructions. These encodings were chosen for compatibility with existing MIPS implementations, including many which pre-date
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the MIPS32 architecture. Because a pipeline flush clears hazards on most early implementations, the JALR.HB or JR.HB instructions can be included in existing software for backward and forward compatibility. See the JALR.HB and JR.HB instructions for additional information.
The SYNCI instruction is encoded using a new encoding of the REGIMM opcode. This encoding was chosen because it causes a Reserved Instruction exception on all Release 1 implementations. As such, kernel software run- ning on processors that don’t implement Release 2 can emulate the function using the CACHE instruction.
8.3.2 microMIPS32 Instruction Encoding
The EHB and SSNOP instructions are encoded using a variant of the NOP encoding. See the EHB and SSNOP instruction description for additional information.
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Chapter 9
Coprocessor 0 Registers
The Coprocessor 0 (CP0) registers provide the interface between the ISA and the PRA. Each register is discussed below, with the registers presented in numerical order, first by register number, then by select field number.
9.1 Coprocessor 0 Register Summary
Table 9.1 lists the CP0 registers in numerical order. The individual registers are described later in this document. If the compliance level is qualified (e.g., “Required (TLB MMU)”), it applies only if the qualifying condition is true. The Sel column indicates the value to be used in the field of the same name in the MFC0 and MTC0 instructions.
Table 9.1 Coprocessor 0 Registers in Numerical Order
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
0
0
Index
Index into the TLB array
Section 9.4 on page 92
Required (TLB MMU); Optional (Others)
0
1
MVPControl
Per-processor register containing global MIPS® MT configuration data
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
0
2
MVPConf0
Per-processor multi-VPE dynamic con- figuration information
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
0
3
MVPConf1
Per-processor multi-VPE dynamic con- figuration information
MIPS®MT ASE Specification
Optional
1
0
Random
Randomly generated index into the TLB array
Section 9.5 on page 93
Required (TLB MMU); Optional (Others)
1
1
VPEControl
Per-VPE register containing relatively volatile thread configuration data
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
1
2
VPEConf0
Per-VPE multi-thread configuration information
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
1
3
VPEConf1
Per-VPE multi-thread configuration information
MIPS®MT ASE Specification
Optional
1
4
YQMask
Per-VPE register defining which YIELD qualifier bits may be used without gener- ating an exception
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
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Coprocessor 0 Registers
Table 9.1 Coprocessor 0 Registers in Numerical Order
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
1
5
VPESchedule
Per-VPE register to manage scheduling of a VPE within a processor
MIPS®MT ASE Specification
Optional
1
6
VPEScheFBack
Per-VPE register to provide scheduling feedback to software
MIPS®MT ASE Specification
Optional
1
7
VPEOpt
Per-VPE register to provide control over optional features, such as cache partition- ing control
MIPS®MT ASE Specification
Optional
2
0
EntryLo0
Low-order portion of the TLB entry for even-numbered virtual pages
Section 9.6 on page 94
Required (TLB MMU); Optional (Others)
2
1
TCStatus
Per-TC status information, including cop- ies of thread-specific bits of Status and EntryHi registers.
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
2
2
TCBind
Per-TC information about TC ID and VPE binding
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
2
3
TCRestart
Per-TC value of restart instruction address for the associated thread of exe- cution
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
2
4
TCHalt
Per-TC register controlling Halt state of TC
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
2
5
TCContext
Per-TC read/write storage for operating system use
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
2
6
TCSchedule
Per-TC register to manage scheduling of a TC
MIPS®MT ASE Specification
Optional
2
7
TCScheFBack
Per-TC register to provide scheduling feedback to software
MIPS®MT ASE Specification
Optional
3
0
EntryLo1
Low-order portion of the TLB entry for odd-numbered virtual pages
Section 9.6 on page 94
Required (TLB MMU); Optional (Others)
3
7
TCOpt
Per-TC register to provide control over optional features, such as cache partition- ing control
MIPS®MT ASE Specification
Optional
4
0
Context
Pointer to page table entry in memory
Section 9.7 on page 99
Required (TLB MMU); Optional (Others)
4
1
ContextConfig
Context register configuration
SmartMIPS ASE Specification and Section 9.8 on page 103
Required (Smart- MIPS ASE); Optional (Others)
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Table 9.1 Coprocessor 0 Registers in Numerical Order
9.1 Coprocessor 0 Register Summary
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
4
2
UserLocal
User information that can be written by privileged software and read via RDHWR register 29. If the processor implements the MIPS® MT ASE, this is a per-TC register.
Section 9.9 on page 105
Recommended (Release 2)
4
3
XContext register configuration in 64-bit implementations
Reserved
5
0
PageMask
Control for variable page size in TLB entries
Section 9.10 on page 106
Required (TLB MMU); Optional (Others)
5
1
PageGrain
Control for small page support
Section 9.11 on page 108 and Smart- MIPS ASE Specifi- cation
Required (Smart- MIPS ASE); Optional (Release 2)
6
0
Wired
Controls the number of fixed (“wired”) TLB entries
Section 9.12 on page 111
Required (TLB MMU); Optional (Others)
6
1
SRSConf0
Per-VPE register indicating and option- ally controlling shadow register set con- figuration
MIPS®MT ASE Specification
Required (MIPS MT ASE); Optional (Oth- ers)
6
2
SRSConf1
Per-VPE register indicating and option- ally controlling shadow register set con- figuration
MIPS®MT ASE Specification
Optional
6
3
SRSConf2
Per-VPE register indicating and option- ally controlling shadow register set con- figuration
MIPS®MT ASE Specification
Optional
6
4
SRSConf3
Per-VPE register indicating and option- ally controlling shadow register set con- figuration
MIPS®MT ASE Specification
Optional
6
5
SRSConf4
Per-VPE register indicating and option- ally controlling shadow register set con- figuration
MIPS®MT ASE Specification
Optional
7
0
HWREna
Enables access via the RDHWR instruc- tion to selected hardware registers
Section 9.13 on page 113
Required (Release 2)
7
1-7
Reserved for future extensions
Reserved
8
0
BadVAddr
Reports the address for the most recent address-related exception
Section 9.14 on page 115
Required
9
0
Count
Processor cycle count
Section 9.15 on page 116
Required
9
6-7
Available for implementation dependent user
Section 9.16 on page 116
Implementation Dependent
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Coprocessor 0 Registers
Table 9.1 Coprocessor 0 Registers in Numerical Order
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
10
0
EntryHi
High-order portion of the TLB entry
Section 9.17 on page 117
Required (TLB MMU); Optional (Others)
11
0
Compare
Timer interrupt control
Section 9.18 on page 119
Required
11
6-7
Available for implementation dependent user
Section 9.19 on page 119
Implementation Dependent
12
0
Status
Processor status and control
Section 9.20 on page 120
Required
12
1
IntCtl
Interrupt system status and control
Section 9.21 on page 127
Required (Release 2)
12
2
SRSCtl
Shadow register set status and control
Section 9.22 on page 130
Required (Release 2)
12
3
SRSMap
Shadow set IPL mapping
Section 9.23 on page 133
Required (Release 2 and shadow sets implemented)
12
4
View_IPL
Contiguous view of IM and IPL fields.
MIPS® MCU ASE Specification
Required (MIPS MCU ASE); Optional (Others)
12
5
SRSMap2
Shadow set IPL mapping
MIPS® MCU ASE Specification
Required (MIPS MCU ASE); Optional (Others)
13
0
Cause
Cause of last general exception
Section 9.24 on page 134
Required
13
4
View_RIPL
Contiguous view of IP and RIPL fields.
MIPS® MCU ASE Specification
Required (MIPS MCU ASE); Optional (Others)
14
0
EPC
Program counter at last exception
Section 9.25 on page 140
Required
15
0
PRId
Processor identification and revision
Section 9.26 on page 142
Required
15
1
EBase
Exception vector base register
Section 9.27 on page 144
Required (Release 2)
15
2
CDMMBase
Common Device Memory Map Base register
Section 9.28 on page 146
Optional
15
3
CMGCRBase
Coherency Manager Global Control Reg- ister Base register
Section 9.29 on page 148
Optional
16
0
Config
Configuration register
Section 9.30 on page 149
Required
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Table 9.1 Coprocessor 0 Registers in Numerical Order
9.1 Coprocessor 0 Register Summary
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
16
1
Config1
Configuration register 1
Section 9.31 on page 152
Required
16
2
Config2
Configuration register 2
Section 9.32 on page 156
Optional
16
3
Config3
Configuration register 3
Section 9.33 on page 159
Optional
16
3
Config4
Configuration register 4
Section 9.34 on page 165
Optional
16
6-7
Available for implementation dependent user
Section 9.35 on page 169
Implementation Dependent
17
0
LLAddr
Load linked address
Section 9.36 on page 170
Optional
18
0-n
WatchLo
Watchpoint address
Section 9.37 on page 171
Optional
19
0-n
WatchHi
Watchpoint control
Section 9.38 on page 173
Optional
20
0
XContext in 64-bit implementations
Reserved
21
all
Reserved for future extensions
Reserved
22
all
Available for implementation dependent use
Section 9.39 on page 175
Implementation Dependent
23
0
Debug
EJTAG Debug register
EJTAG Specification
Optional
23
1
TraceControl
PDtrace control register
PDtrace Specifica- tion
Optional
23
2
TraceControl2
PDtrace control register
PDtrace Specifica- tion
Optional
23
3
UserTraceData1
PDtrace control register
PDtrace Specifica- tion
Optional
23
4
TraceIBPC
PDtrace control register
PDtrace Specifica- tion
Optional
23
5
TraceDBPC
PDtrace control register
PDtrace Specifica- tion
Optional
23
6
Debug2
EJTAG Debug2 register
EJTAG Specification
Optional
24
0
DEPC
Program counter at last EJTAG debug exception
EJTAG Specification
Optional
24
2
TraceContol3
PDtrace control register
PDtrace Specifica- tion
Optional
24
3
UserTraceData2
PDtrace control register
PDtrace Specifica- tion
Optional
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Coprocessor 0 Registers
Table 9.1 Coprocessor 0 Registers in Numerical Order
Register Number
Sel1
Register Name
Function
Reference
Compliance Level
25
0-n
PerfCnt
Performance counter interface
Section 9.43 on page 180
Recommended
26
0
ErrCtl
Parity/ECC error control and status
Section 9.44 on page 184
Optional
27
0-3
CacheErr
Cache parity error control and status
Section 9.45 on page 185
Optional
28
even selects
TagLo
Low-order portion of cache tag interface
Section 9.46 on page 186
Required (Cache)
28
odd selects
DataLo
Low-order portion of cache data interface
Section 9.47 on page 187
Optional
29
even selects
TagHi
High-order portion of cache tag interface
Section 9.48 on page 188
Required (Cache)
29
odd selects
DataHi
High-order portion of cache data inter- face
Section 9.49 on page 189
Optional
30
0
ErrorEPC
Program counter at last error
Section 9.50 on page 190
Required
31
0
DESAVE
EJTAG debug exception save register
EJTAG Specification
Optional
31
2-7
KScratchn
Scratch Registers for Kernel Mode
Section 9.52 on page 194
Optional; KScratch1 at select 2 and KScratch2 at select 3 are recommended.
1. Any select (Sel) value not explicitly noted as available for implementation-dependent use is reserved for future use by the Architec- ture.
9.2 Notation
For each register described below, field descriptions include the read/write properties of the field, and the reset state of the field. For the read/write properties of the field, the following notation is used:
Table 9.2 Read/Write Bit Field Notation
Read/Write Notation
Hardware Interpretation
Software Interpretation
R/W
A field in which all bits are readable and writable by software and, potentially, by hardware. Hardware updates of this field are visible by software read. Software updates of this field are vis- ible by hardware read.
If the Reset State of this field is “Undefined”, either software or hardware must initialize the value before the first read will return a predictable value. This should not be confused with the formal definition of UNDEFINED behavior.
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Table 9.2 Read/Write Bit Field Notation
9.3 Writing CPU Registers
Read/Write Notation
Hardware Interpretation
Software Interpretation
R
A field which is either static or is updated only by hardware.
If the Reset State of this field is either “0”, “Preset”, or “Externally Set”, hardware initial- izes this field to zero or to the appropriate state, respectively, on powerup. The term “Pre- set” is used to suggest that the processor estab- lishes the appropriate state, whereas the term “Externally Set” is used to suggest that the state is established via an external source (e.g., personality pins or initialization bit stream). These terms are suggestions only, and are not intended to act as a requirement on the imple- mentation.
If the Reset State of this field is “Undefined”, hardware updates this field only under those conditions specified in the description of the field.
A field to which the value written by software is ignored by hardware. Software may write any value to this field without affecting hard- ware behavior. Software reads of this field return the last value updated by hardware.
If the Reset State of this field is “Undefined”, software reads of this field result in an UNPREDICTABLE value except after a hardware update done under the conditions specified in the description of the field.
0
A field which hardware does not update, and for which hardware can assume a zero value.
A field to which the value written by software must be zero. Software writes of non-zero val- ues to this field may result in UNDEFINED behavior of the hardware. Software reads of this field return zero as long as all previous software writes are zero.
If the Reset State of this field is “Undefined”, software must write this field with zero before it is guaranteed to read as zero.
9.3 Writing CPU Registers
With certain restrictions, software may assume that it can validly write the value read from a coprocessor 0 register back to that register without having unintended side effects. This rule means that software can read a register, modify one field, and write the value back to the register without having to consider the impact of writes to other fields. Pro- cessor designers should take this into consideration when using coprocessor 0 register fields that are reserved for implementations and make sure that the use of these bits is consistent with software assumptions.
The most significant exception to this rule is a situation in which the processor modifies the register between the soft- ware read and write, such as might occur if an exception or interrupt occurs between the read and write. Software must guarantee that such an event does not occur.
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9.4 Index Register (CP0 Register 0, Select 0)
31
Figure 9-1 Index Register Format
Table 9.3 Index Register Field Descriptions
n n-1 0
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
The Index register is a 32-bit read/write register which contains the index used to access the TLB for TLBP, TLBR, and TLBWI instructions. The width of the index field is implementation-dependent as a function of the number of TLB entries that are implemented. The minimum value for TLB-based MMUs is Ceiling(Log2(TLBEntries)). For example, six bits are required for a TLB with 48 entries).
The operation of the processor is UNDEFINED if a value greater than or equal to the number of TLB entries is writ- ten to the Index register.
Figure 9-1 shows the format of the Index register; Table 9.3 describes the Index register fields.
P
0
Index
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
P
31
Probe Failure. Hardware writes this bit during execu- tion of the TLBP instruction to indicate whether a TLB match occurred:
Encoding
Meaning
0
A match occurred, and the Index field contains the index of the matching entry
1
No match occurred and the Index field is UNPREDICTABLE
R
Undefined
Required
0
30..n
Must be written as zero; returns zero on read.
0
0
Reserved
Index
n-1..0
TLB index. Software writes this field to provide the index to the TLB entry referenced by the TLBR and TLBWI instructions.
Hardware writes this field with the index of the match- ing TLB entry during execution of the TLBP instruc- tion. If the TLBP fails to find a match, the contents of this field are UNPREDICTABLE.
R/W
Undefined
Required
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9.5 Random Register (CP0 Register 1, Select 0)
31
Figure 9-2 Random Register Format
Table 9.4 Random Register Field Descriptions
n n-1 0
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
The Random register is a read-only register whose value is used to index the TLB during a TLBWR instruction. The
width of the Random field is calculated in the same manner as that described for the Index register above.
The value of the register varies between an upper and lower bound as follow:
• A lower bound is set by the number of TLB entries reserved for exclusive use by the operating system (the con- tents of the Wired register). The entry indexed by the Wired register is the first entry available to be written by a TLB Write Random operation.
• An upper bound is set by the total number of TLB entries minus 1.
Within the required constraints of the upper and lower bounds, the manner in which the processor selects values for
the Random register is implementation-dependent.
The processor initializes the Random register to the upper bound on a Reset Exception, and when the Wired register
is written.
Figure 9-2 shows the format of the Random register; Table 9.4 describes the Random register fields.
9.5 Random Register (CP0 Register 1, Select 0)
0
Random
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
0
31..n
Must be written as zero; returns zero on read.
0
0
Reserved
Random
n-1..0
TLB Random Index
R
TLB Entries – 1
Required
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9.6 EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0)
Compliance Level: EntryLo0 is Required for a TLB-based MMU; Optional otherwise. Compliance Level: EntryLo1 is Required for a TLB-based MMU; Optional otherwise.
The pair of EntryLo registers act as the interface between the TLB and the TLBP, TLBR, TLBWI, and TLBWR instructions. EntryLo0 holds the entries for even pages and EntryLo1 holds the entries for odd pages.
Software may determine the value of PABITS by writing all ones to the EntryLo0 or EntryLo1 registers and reading the value back. Bits read as “1” from the PFN field allow software to determine the boundary between the PFNand Fill fields to calculate the value of PABITS.
The contents of the EntryLo0 and EntryLo1 registers are not defined after an address error exception and some fields may be modified by hardware during the address error exception sequence. Software writes of the EntryHi register (via MTC0) do not cause the implicit update of address-related fields in the BadVAddr or Context registers.
For Release 1 of the Architecture, Figure 9-3 shows the format of the EntryLo0 and EntryLo1 registers; Table 9.5 describes the EntryLo0 and EntryLo1 register fields.
For Release 2 of the Architecture, Figure 9-4 shows the format of the EntryLo0 and EntryLo1 registers; Table 9.6 describes the EntryLo0 and EntryLo1 register fields.
For Release 3 of the Architecture, Figure 9-5 shows the format of the EntryLo0 and EntryLo1 registers; Figure 9.8 describes the EntryLo0 and EntryLo1 register fields.
Figure 9-3 EntryLo0, EntryLo1 Register Format in Release 1 of the Architecture
31 30 29 6 5 3 2 1 0
Table 9.5 EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture
Fill
PFN
C
D
V
G
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Fill
31..30
These bits are ignored on write and return zero on read. The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R
0
Required
PFN
29..6
Page Frame Number. Corresponds to bits PABITS-1..12 of the physical address, where PABITS is the width of the physical address in bits. The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R/W
Undefined
Required
C
5..3
Cacheability and Coherency Attribute of the page. See Table 9.9 below.
R/W
Undefined
Required
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Table 9.5 EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture
9.6 EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
D
2
“Dirty” bit, indicating that the page is writable. If this bit is a one, stores to the page are permitted. If this bit is a zero, stores to the page cause a TLB Modified exception. Kernel software may use this bit to implement paging algorithms that require knowing which pages have been written. If this bit is always zero when a page is initially mapped, the TLB Modified exception that results on any store to the page can be used to update kernel data struc- tures that indicate that the page was actually written.
R/W
Undefined
Required
V
1
Valid bit, indicating that the TLB entry, and thus the vir- tual page mapping are valid. If this bit is a one, accesses to the page are permitted. If this bit is a zero, accesses to the page cause a TLB Invalid exception.
R/W
Undefined
Required
G
0
Global bit. On a TLB write, the logical AND of the G bits from both EntryLo0 and EntryLo1 becomes the G bit in the TLB entry. If the TLB entry G bit is a one, ASID comparisons are ignored during TLB matches. On a read from a TLB entry, the G bits of both EntryLo0 and EntryLo1 reflect the state of the TLB G bit.
R/W
Undefined
Required (TLB MMU)
Figure 9-4 EntryLo0, EntryLo1 Register Format in Release 2 of the Architecture
31 30 29 6 5 3 2 1 0
Table 9.6 EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture
Fill
PFN
C
D
V
G
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Fill
31..30
These bits are ignored on write and return zero on read. The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R
0
Required
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Table 9.6 EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
PFN
29..6
Page Frame Number. This field contains the physical page number corresponding to the virtual page.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the PFN field corresponds to bits 33..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 def- inition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the PFN field cor- responds to bits 35..12 of the physical address.
The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R/W
Undefined
Required
C
5..3
The definition of this field is unchanged from Release 1. See Table 9.5 above and Table 9.9 below.
R/W
Undefined
Required
D
2
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required
V
1
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required
G
0
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required (TLB MMU)
Table 9.7 shows the movement of the Fill and PFN fields as a function of 1KB page support enabled, and the value of PABITS. Note that in implementations of Release 1 of the Architecture, there is no support for 1KB pages, so only the first row of the table applies to Release 1.
Table 9.7 EntryLo Field Widths as a Function of PABITS
1KB Page Support Enabled?
PABITS Value
Corresponding EntryLo Field Bit Ranges
Release 2 Required?
Fill Field
PFN Field
No
36 ≥ PABITS > 12
31..(30-(36-PABITS)) Example: 31..30 if PABITS = 36 31..7 if PABITS = 13
(29-(36-PABITS))..6 Example: 29..6 if PABITS = 36 6..6 if PABITS = 13
EntryLo29..6 = PA35..12
No
Yes
34 ≥ PABITS > 10
31..(30-(34-PABITS)) Example: 31..30 if PABITS = 34 31..7 if PABITS = 11
(29-(34-PABITS))..6 Example: 29..6 if PABITS = 34 6..6 if PABITS = 11
EntryLo29..6 = PA33..10
Yes
Figure 9-5 EntryLo0, EntryLo1 Register Format in Release 3 of the Architecture
31 30 29 6 5 3 2 1 0
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RI
XI
PFN
C
D
V
G
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Table 9.8 EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture
9.6 EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Fill
31..30
These bits are ignored on write and return zero on read. The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R
0
Required if RI and XI fields are not imple- mented.
RI
31
Read Inhibit. If this bit is set in a TLB entry, an attempt, other than a MIPS16 PC-relative load, to read data on the virtual page causes a TLB Invalid or a TLBRI excep- tion, even if the V (Valid) bit is set. The RI bit is writable only if the RIE bit of the PageGrain register is set. If the RIE bit of PageGrain is not set, the RI bit of EntryLo0/EntryLo1 is set to zero on any write to the register, regardless of the value written.
This bit is optional and its existence is denoted by the Config3RXI or Config3 SM register fields.
R/W
0
Required by
SmartMIPS ASE; Optional otherwise
If not imple- mented, this bit location is part of the Fill field.
XI
30
Execute Inhibit. If this bit is set in a TLB entry, an attempt to fetch an instruction or to load MIPS16 PC-rel- ative data from the virtual page causes a TLB Invalid or a TLBXI exception, even if the V (Valid) bit is set. The XI bit is writable only if the XIE bit of the PageGrain register is set. If the XIE bit of PageGrain is not set, the XI bit of EntryLo0/EntryLo1 is set to zero on any write to the register, regardless of the value written.
This bit is optional and its existence is denoted by the Config3RXI or Config3 SM register fields.
R/W
0
Required by
SmartMIPS ASE; Optional otherwise
If not imple- mented, this bit location is part of the Fill field.
PFN
29..6
Page Frame Number. This field contains the physical page number corresponding to the virtual page.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the PFN field corresponds to bits 33..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 def- inition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the PFN field cor- responds to bits 35..12 of the physical address.
The boundaries of this field change as a function of the value of PABITS. See Table 9.7 for more information.
R/W
Undefined
Required
C
5..3
The definition of this field is unchanged from Release 1. See Table 9.5 above and Table 9.9 below.
R/W
Undefined
Required
D
2
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required
V
1
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required
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Table 9.8 EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
G
0
The definition of this field is unchanged from Release 1. See Table 9.5 above.
R/W
Undefined
Required (TLB MMU)
Programming Note:
In implementations of Release 2 of the Architecture (and subsequent releases), the PFN field of both the EntryLo0 and EntryLo1 registers must be written with zero and the TLB must be flushed before each instance in which the value of the PageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.
Table 9.9 lists the encoding of the C field of the EntryLo0 and EntryLo1 registers and the K0 field of the Config reg- ister. An implementation may choose to implement a subset of the cache coherency attributes shown, but must imple- ment at least encodings 2 and 3 such that software can always depend on these encodings working appropriately. In other cases, the operation of the processor is UNDEFINED if software uses a TLB mapping (either for an instruction fetch or for a load/store instruction) which was created with a C field encoding which is RESERVED for the imple- mentation.
Table 9.9 lists the required and optional encodings for the cacheability and coherency attributes. Table 9.9 Cacheability and Coherency Attributes
C(5:3) Value
Cacheability and Coherency Attributes With Historical Usage
Compliance
0
Available for implementation dependent use
Optional
1
Available for implementation dependent use
Optional
2
Uncached
Required
3
• Cacheable
Required
4
Available for implementation dependent use
Optional
5
Available for implementation dependent use
Optional
6
Available for implementation dependent use
Optional
7
Available for implementation dependent use
Optional
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9.7 Context Register (CP0 Register 4, Select 0)
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
The Context register is a read/write register containing a pointer to an entry in the page table entry (PTE) array. This array is an operating system data structure that stores virtual-to-physical translations. During a TLB miss, the operat- ing system loads the TLB with the missing translation from the PTE array. The Context register duplicates some of the information provided in the BadVAddr register.
If Config3CTXTC =0 and Config3SM =0 then the Context register is organized in such a way that the operating sys- tem can directly reference a 16-byte structure in memory that describes the mapping. For PTE structures of other sizes, the content of this register can be used by the TLB refill handler after appropriate shifting and masking.
If Config3CTXTC =0 and Config3SM =0 then a TLB exception (TLB Refill, TLB Invalid, or TLB Modified) causes bits VA31..13 of the virtual address to be written into the BadVPN2 field of the Context register. The PTEBase field is written and used by the operating system.
The BadVPN2 field of the Context register is not defined after an address error exception and this field may be mod- ified by hardware during the address error exception sequence.
Figure 9-6 shows the format of the Context Register when Config3CTXTC =0 and Config3SM =0; Table 9.10 describes the Context register fields Config3CTXTC =0 and Config3SM =0.
Figure 9-6 Context Register Format when Config3CTXTC=0 and Config3SM=0
31 2322 43 0
Table 9.10 Context Register Field Descriptions when Config3CTXTC=0 and Config3SM=0
9.7 Context Register (CP0 Register 4, Select 0)
PTEBase
BadVPN2
0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
PTEBase
31..23
This field is for use by the operating system and is normally written with a value that allows the oper- ating system to use the Context Register as a pointer into the current PTE array in memory.
R/W
Undefined
Required
BadVPN2
22..4
This field is written by hardware on a TLB excep- tion. It contains bits VA31..13 of the virtual address that caused the exception.
R
Undefined
Required
0
3..0
Must be written as zero; returns zero on read.
0
0
Reserved
If Config3CTXTC =1 or Config3SM =1 then the pointer implemented by the Context register can point to any power-of-two-sized PTE structure within memory. This allows the TLB refill handler to use the pointer without addi- tional shifting and masking steps. Depending on the value in the ContextConfig register, it may point to an 8-byte pair
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of 32-bit PTEs within a single-level page table scheme, or to a first level page directory entry in a two-level lookup scheme.
If Config3CTXTC =1 or Config3SM =1 then the a TLB exception (Refill, Invalid, or Modified) causes bits VA31:31-((X-Y)-1) to be written to a variable range of bits “(X-1):Y” of the Context register, where this range corre-
sponds to the contiguous range of set bits in the ContextConfig register. Bits 31:X are R/W to software, and are unaf- fected by the exception. Bits Y-1:0 are unaffected by the exception. If X = 23 and Y = 4, i.e. bits 22:4 are set in ContextConfig, the behavior is identical to the standard MIPS32 Context register (bits 22:4 are filled with VA31:13). Although the fields have been made variable in size and interpretation, the MIPS32 nomenclature is retained. Bits 31:X are referred to as the PTEBase field, and bits X-1:Y are referred to as BadVPN2.
If Config3SM =1 then Bits Y-1:0 will always read as 0.
The value of the Context register is UNPREDICTABLE following a modification of the contents of the
ContextConfig register.
Figure 9-7 shows the format of the Context Register when Config3CTXTC =1 or Config3SM =1; Table 9.11 describes
the Context register fields Config3CTXTC =1 or Config3SM =1.
Figure 9-7 Context Register Format when Config3CTXTC=1 or Config3SM=1
31 XX-1 YY-1 0
Table 9.11 Context Register Field Descriptions when Config3CTXTC=1 or Config3SM=1
PTEBase
BadVPN2
0
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
PTEBase
Variable, 31:X where X in {31..0}.
May be null.
This field is for use by the operating system and is normally written with a value that allows the operating system to use the Context Register as a pointer to an array of data structures in memory corresponding to the address region containing the virtual address which caused the exception.
R/W
Undefined
Required
BadVPN2
Variable, (X-1):Y where
X in {32..1} and Y in {31..0}. May be null.
This field is written by hardware on a TLB exception. It contains bits VA31:31-((X-Y)-1) of
the virtual address that caused the exception.
R
Undefined
Required
0
Variable, (Y-1):0 where
Y in {31:1}. May be null.
Must be written as zero; returns zero on read.
0
0
Reserved
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9.7 Context Register (CP0 Register 4, Select 0)
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9.8 ContextConfig Register (CP0 Register 4, Select 1)
Compliance Level: Optional.
The ContextConfig register defines the bits of the Context register into which the high order bits of the virtual address causing a TLB exception will be written, and how many bits of that virtual address will be extracted. Bits above the selected field of the Context register are R/W to software and serve as the PTEBase field. Bits below the selected field of the Context register will be unaffected by TLB exceptions.
The field to contain the virtual address index is defined by a single block of contiguous non-zero bits within the ContextConfig register’s VirtualIndex field. Any zero bits to the right of the least significant one bit cause the corre- sponding Context register bits to be unaffected by TLB exceptions. Any zero bits to the left of the most significant one bit cause the corresponding Context register bits to be R/W to software and unaffected by TLB exceptions.
If Config3SM is set, then any zero bits to the right of the least significant one bit causes the corresponding Context reg- ister bits to be read as zero.
It is permissible to implement a subset of the ContextConfig register, in which some number of bits are read-only and set to one or zero as appropriate. It is possible for software to determine which bits are implemented by alternately writing all zeroes and all ones to the register, and reading back the resulting values. All implementations of the ContextConfig register must allow for the emulation of the MIPS32/microMIPS32 fixed Context register configura- tion.
This paragraph describes restrictions on how the ContextConfig register may be programmed. The set bits of ContextConfig define the BadVPN2 field within the Config register. The BadVPN2 field cannot contain address bits which are used to index a memory location within the even-odd page pairs used by the JTLB entries. This limits the least significant writeable bit within ContextConfig to the bits that represents BadVPN2 of the smallest implemented page size. For example, if the smallest implemented page size is 4KB, virtual address bit 13 is the least significant bit of the BadVPN2 field. This example would restrict the least significant writeable bit within ContextConfig to be bit 4 (corresponds to virtual address bit 13) or larger. Another example: if 1KB was the smallest implemented page size then the least significant writeable bit within ContextConfig would be bit 2 or larger.
A value of all zeroes means that the full 32 bits of the Context register are R/W for software and unaffected by TLB exceptions.
The ContextConfig register is optional and its existence is denoted by the Config3CTXTC or Config3SM register fields. Figure 9.8 shows the formats of the ContextConfig Register; Table 9.12 describes the ContextConfig register fields.
Figure 9.8 ContextConfig Register Format
31 0
VirtualIndex
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9.8 ContextConfig Register (CP0 Register 4, Select 1)
103

Table 9.12 ContextConfig Register Field Descriptions
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
VirtualIndex
31:0
A mask of 0 to 32 contiguous 1 bits in this field causes the corresponding bits of the Context register to be writ- ten with the high-order bits of the virtual address causing a TLB exception.
Behavior of the processor is UNDEFINED if non-con- tiguous 1 bits are written into the register field.
R/W
0x007ffff0
Required
Table 9.13 describes some useful ContextConfig values.
Table 9.13 Recommended ContextConfig Values
Value
Page Table Organization
Page Size
PTE Size
Compliance
0x007ffff0
Single Level
4K
64 bits/page
REQUIRED
0x007ffff8
Single Level
2K
32 bits/page
RECOMMENDED
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9.9 UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via
the RDHWR instruction.
If the MIPS® MT ASE is implemented, the UserLocal register is instantiated per TC.
This register only exists if the Config3ULRI register field is set.
Figure 9-9 shows the format of the UserLocal register; Table 9.14 describes the UserLocal register fields.
Figure 9-9 UserLocal Register Format
31 0
Table 9.14 UserLocal Register Field Descriptions
Programming Notes
Privileged software may write this register with arbitrary information and make it accessable to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. In some operating environments, the UserLocal register contains a pointer to a thread-specific storage block that is obtained via the RDHWR register.
9.9 UserLocal Register (CP0 Register 4, Select 2)
UserInformation
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
UserInfor- mation
31..0
This field contains software information that is not inter- preted by the hardware.
R/W
Undefined
Required
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9.10 PageMask Register (CP0 Register 5, Select 0)
31
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
The PageMask register is a read/write register used for reading from and writing to the TLB. It holds a comparison mask that sets the variable page size for each TLB entry, as shown in Table 9.16. Figure 9-10 shows the format of the PageMask register; Table 9.15 describes the PageMask register fields.
Figure 9-10 PageMask Register Format
29 28 13 12 11 10 0
Table 9.15 PageMask Register Field Descriptions
0
Mask
MaskX
0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Mask
28..13
The Mask field is a bit mask in which a “1” bit indicates that the corresponding bit of the vir- tual address should not participate in the TLB match.
R/W
Undefined
Required
MaskX
12..11
In Release 2 of the Architecture (and subse- quent releases), the MaskX field is an exten- sion to the Mask field to support 1KB pages with definition and action analogous to that of the Mask field, defined above.
If 1KB pages are enabled (Config3SP = 1 and PageGrainESP = 1), these bits are writable and readable, and their values are copied to and from the TLB entry on a TLB write or read, respectively.
If 1KB pages are not enabled (Config3SP = 0 or PageGrainESP = 0), these bits are not writ- able, return zero on read, and the effect on the TLB entry on a write is as if they were written with the value 0b11.
In Release 1 of the Architecture, these bits must be written as zero, return zero on read, and have no effect on the virtual address trans- lation.
R/W
0
(See Description)
Required (Release 2)
0
31..29, 10..0
Ignored on write; returns zero on read.
R
0
Required
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Table 9.16 Values for the Mask and MaskX1 Fields of the PageMask Register
9.10 PageMask Register (CP0 Register 5, Select 0)
Page Size
Values for Mask field (lsb of value is located at PageMask13)
Values for MaskX1 field
1 KByte
0x0
0x0
4 KByte
0x0
0x3
16 KByte
0x3
0x3
64 KByte
0xF
0x3
256 KByte
0x3F
0x3
1 MByte
0xFF
0x3
4 MByte
0x3FF
0x3
16 MByte
0xFFF
0x3
64 MByte
0x3FFF
0x3
256 MByte
0xFFFF
0x3
1. PageMask12..11 = PageMaskMaskX exists only on implementations of Release 2 of the architec- ture and are treated as if they had the value 0b11 if 1K pages are not enabled (Config3SP = 0 or PageGrainESP = 0).
It is implementation dependent how many of the encodings described in Table 9.16 are implemented. All processors must implement the 4KB page size. If a particular page size encoding is not implemented by a processor, a read of the PageMask register must return zeros in all bits that correspond to encodings that are not implemented, thereby potentially returning a value different than that written by software.
Software may determine which page sizes are supported by writing all ones to the PageMask register, then reading the value back. If a pair of bits reads back as ones, the processor implements that page size. The operation of the pro- cessor is UNDEFINED if software loads the Mask field with a value other than one of those listed in Table 9.16, even if the hardware returns a different value on read. Hardware may depend on this requirement in implementing hard- ware structures
Programming Note:
In implementations of Release 2 (and subsequent releases) of the Architecture, the MaskX field of the PageMask register must be written with 0b11 and the TLB must be flushed before each instance in which the value of the PageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.
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9.11 PageGrain Register (CP0 Register 5, Select 1)
Compliance Level: Required for implementations of Release 2 (and subsequent releases) of the Architecture that include TLB-based MMUs and support 1KB pages, the XI/RI TLB protection bits; Required for SmartMIPSTM ASE; otherwise Optional.
The PageGrain register is a read/write register used for enabling 1KB page support, the XI/RI TLB protection bits. The PageGrain register is present in both the SmartMIPSTM ASE, and in Release 2 (and subsequent releases) of the Architecture. As such, the description below only describes the fields relevant to Release 2 of the Architecture. In implementations of both Release 2 of the Architecture and the SmartMIPSTM ASE, the ASE definitions take prece- dence. Figure 9-11 shows the format of the PageGrain register; Table 9.17 describes the PageGrain register fields.
Figure 9-11 PageGrain Register Format
31 30 29 28 27 26 13 12 8 7 0
Table 9.17 PageGrain Register Field Descriptions
RIE
XIE
ELPA
ESP
IEC
0
ASE
0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
RIE
31
Read Inhibit Enable.
This bit is optional. The existence of this bit is denoted by either the SM or RXI bits within the Config3 register. If this bit is not settable then the RI bit within the EntryLo* registers is not implemented.
Encoding
Meaning
0
RI bit of the EntryLo0 and EntryLo1 registers is disabled and not writeable by software.
1
RI bit of the EntryLo0 and EntryLo1 registers is enabled.
R/W or R
0
Required by SmartMIPS ASE; Optional otherwise
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Table 9.17 PageGrain Register Field Descriptions
9.11 PageGrain Register (CP0 Register 5, Select 1)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
XIE
30
Execute Inhibit Enable.
This bit is optional. The existence of this bit is denoted by either the SM or RXI bits within the Config3 register. If this bit is not settable then the XI bit within the EntryLo* registers is not implemented.
Encoding
Meaning
0
XI bit of the EntryLo0 and EntryLo1 registers is disabled and not writeable by software.
1
XI bit of the EntryLo0 and EntryLo1 registers is enabled.
R/W or R
0
Required by SmartMIPS ASE; Optional otherwise
ASE
12..8
These fields are control features of the SmartMIPSTM ASE and are not used in implementations of Release 2 of the Architecture unless such an implementation also implements the SmartMIPSTM ASE.
0
0
Required
ELPA
29
Used to enable support for large physical addresses in MIPS64 processors; not used by MIPS32 processors. This bit is ignored on write and returns zero on read.
R
0
Required
ESP
28
Enables support for 1KB pages.
If this bit is a 1, the following changes occur to coproces- sor 0 registers:
• The PFN field of the EntryLo0 and EntryLo1 regis-
ters holds the physical address down to bit 10 (the field is shifted left by 2 bits from the Release 1 defini- tion)
• The MaskX field of the PageMask register is writ- able and is concatenated to the right of the Mask field to form the “don’t care” mask for the TLB entry.
• The VPN2X field of the EntryHi register is writable and bits 12..11 of the virtual address.
• The virtual address translation algorithm is modified to reflect the smaller page size.
If Config3SP = 0, 1KB pages are not implemented, and this bit is ignored on write and returns zero on read.
Encoding
Meaning
0
1KB page support is not enabled
1
1KB page support is enabled
R/W
0
Required
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Table 9.17 PageGrain Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IEC
27
Enables unique exception codes for the Read-Inhibit and Execute-Inhibit exceptions.
Encoding
Meaning
0
Read-Inhbit and Execute-Inhibit exceptions both use the TLBL excep- tion code.
1
Read-Inhibit exceptions use the TLBRI exception code. Execute-Inhibit exceptions use the TLBXI exception code
For implementations which follow the SmartMIPS ASE, this bit is ignored by the hardware, meaning the Read-Inhibit and Execute-Inhibit exceptions can only use the TLBL exception code.
R/W
0
Required
0
26..13, 7..0
Must be written as zero; returns zero on read.
0
0
Reserved
Programming Note:
In implementations of Release 2 (and subsequent releases) of the Architecture, the following fields must be written with the specified values, and the TLB must be flushed before each instance in which the value of the PageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.
Field
EntryLo0PFN, EntryLo1PFN EntryLo0PFNX, EntryLo1PFNX PageMaskMaskX EntryHiVPN2X
Required Value
0
0 0b11 0
Note also that if PageGrain is changed, a hazard may be created between the instruction that writes PageGrain and a subsequent CACHE instruction. This hazard must be cleared using the EHB instruction.
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9.12 Wired Register (CP0 Register 6, Select 0)
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
The Wired register is a read/write register that specifies the boundary between the wired and random entries in the
TLB as shown in Figure 9-12.
Figure 9-12 Wired And Random Entries In The TLB
9.12 Wired Register (CP0 Register 6, Select 0)
Entry TLBSize-1
Entry 10
Entry 0
31
Wired Register 10
The width of the Wired field is calculated in the same manner as that described for the Index register. Wired entries are fixed, non-replaceable entries which are not overwritten by a TLBWR instruction.Wired entries can be overwrit- ten by a TLBWI instruction.
The Wired register is set to zero by a Reset Exception. Writing the Wired register causes the Random register to reset to its upper bound.
The operation of the processor is UNDEFINED if a value greater than or equal to the number of TLB entries is writ- ten to the Wired register.
Figure 9-12 shows the format of the Wired register; Table 9.18 describes the Wired register fields.
Figure 9-13 Wired Register Format
n n-1 0
0
Wired
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Wired Random

Table 9.18 Wired Register Field Descriptions
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
0
31..n
Must be written as zero; returns zero on read.
0
0
Reserved
Wired
n-1..0
TLB wired boundary
R/W
0
Required
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9.13 HWREna Register (CP0 Register 7, Select 0)
Compliance Level: Required (Release 2).
The HWREna register contains a bit mask that determines which hardware registers are accessible via the RDHWR
instruction when that instruction is executed in a mode in which coprocessor 0 is not enabled.
Figure 9-14 shows the format of the HWREna Register; Table 9.19 describes the HWREna register fields.
31 30 29
Figure 9-14 HWREna Register Format
Table 9.19 HWREna Register Field Descriptions
4 3 0
9.13 HWREna Register (CP0 Register 7, Select 0)
Impl
Mask
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
31..30
Impl
These bits enable access to the implementa- tion-dependent hardware registers 31 and 30.
If a register is not implemented, the corresponding bit returns a zero and is ignored on write.
If a register is implemented, access to that register is enabled if the corresponding bit in this field is a 1 and disabled if the corresponding bit is a 0.
R/W
0
Optional – Reserved for Implementations
Mask
29..0
Each bit in this field enables access by the RDHWR instruction to a particular hardware register (which may not be an actual register).
If RDHWR register ‘n’ is not implemented, bit ‘n’ of this field returns a zero and is ignored on a write.
If RDHWR register ‘n’ is implemented, access to the register is enabled if bit ‘n’ in this field is a 1 and disabled if bit ‘n’ of this field is a 0.
See the RDHWR instruction for a list of valid hard- ware registers.
Table 9.20 lists the RDHWR registers, and register number ‘n’ corresponds to bit ‘n’ in this field.
R/W
0
Required
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Table 9.20 RDHWR Register Numbers
Register Number
Mnemonic
Description
Compliance
0
CPUNum
Number of the CPU on which the program is currently running. This register provides read access to the coprocessor 0 EBaseCPUNum field.
Required
1
SYNCI_Step
Address step size to be used with the SYNCI instruction. See that instruc- tion’s description for the use of this value. In the typical implementation, this value should be zero if there are no caches in the system which must be syn- chronize (either because there are no caches, or because the instruction cache tracks writes to the data cache). In other cases, the return value should be the smallest line size of the caches that must be synchronize.
Required
2
CC
High-resolution cycle counter. This register provides read access to the coprocessor 0 Count Register.
Required
3
CCRes
Resolution of the CC register. This value denotes the number of cycles between update of the register. For example:
CCRes Value
Meaning
1
CC register increments every CPU cycle
2
CC register increments every second CPU cycle
3
CC register increments every third CPU cycle
etc.
Required
4-28
These registers numbers are reserved for future architecture use. Access results in a Reserved Instruction Exception.
Reserved
29
ULR
User Local Register. This register provides read access to the coprocessor 0 UserLocal register, if it is implemented. In some operating environments, the UserLocal register is a pointer to a thread-specific storage block.
Required if the
UserLocal
register is implemented
30-31
These register numbers are reserved for implementation-dependent use. If they are not implemented, access results in a Reserved Instruction Exception.
Optional
Using the HWREna register, privileged software may select which of the hardware registers are accessible via the RDHWR instruction. In doing so, a register may be virtualized at the cost of handling a Reserved Instruction Excep- tion, interpreting the instruction, and returning the virtualized value. For example, if it is not desirable to provide direct access to the Count register, access to that register may be individually disabled and the return value can be virtualized by the operating system.
Software may determine which registers are implemented by writing all ones to the HWREna register, then reading the value back. If a bit reads back as a one, the processor implements that hardware register.
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9.14 BadVAddr Register (CP0 Register 8, Select 0)
Compliance Level: Required.
The BadVAddr register is a read-only register that captures the most recent virtual address that caused one of the fol-
lowing exceptions:
• Address error (AdEL or AdES)
• TLB Refill
• TLB Invalid (TLBL, TLBS)
• TLB Modified
The BadVAddr register does not capture address information for cache or bus errors, or for Watch exceptions, since none is an addressing error.
Figure 9-15 shows the format of the BadVAddr register; Table 9.21 describes the BadVAddr register fields.
Figure 9-15 BadVAddr Register Format
31 0
Table 9.21 BadVAddr Register Field Descriptions
9.14 BadVAddr Register (CP0 Register 8, Select 0)
BadVAddr
Fields
Description
Read/W rite
Reset State
Compliance
Name
Bits
BadVAddr
31..0
Bad virtual address
R
Undefined
Required
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9.15 Count Register (CP0 Register 9, Select 0)
Compliance Level: Required.
The Count register acts as a timer, incrementing at a constant rate, whether or not an instruction is executed, retired, or any forward progress is made through the pipeline. The rate at which the counter increments is implementation dependent, and is a function of the pipeline clock of the processor, not the issue width of the processor.
The Count register can be written for functional or diagnostic purposes, including at reset or to synchronize proces- sors.
The Count register can also be read via RDHWR register 2.
Figure 9-16 shows the format of the Count register; Table 9.22 describes the Count register fields.
Figure 9-16 Count Register Format
31 0
Table 9.22 Count Register Field Descriptions
9.16 Reserved for Implementations (CP0 Register 9, Selects 6 and 7)
Compliance Level: Implementation Dependent.
CP0 register 9, Selects 6 and 7 are reserved for implementation dependent use and are not defined by the architecture.
Count
Fields
Description
Read/W rite
Reset State
Compliance
Name
Bits
Count
31..0
Interval counter
R/W
Undefined
Required
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9.17 EntryHi Register (CP0 Register 10, Select 0)
31
Compliance Level: Required for TLB-based MMU; Optional otherwise.
The EntryHi register contains the virtual address match information used for TLB read, write, and access operations.
A TLB exception (TLB Refill, TLB Invalid, or TLB Modified) causes bits VA31..13 of the virtual address to be written into the VPN2 field of the EntryHi register. An implementation of Release 2 of the Architecture which supports 1KB pages also writes VA12..11 into the VPN2X field of the EntryHi register. A TLBR instruction writes the EntryHi regis- ter with the corresponding fields from the selected TLB entry. The ASID field is written by software with the current address space identifier value and is used during the TLB comparison process to determine TLB match.
Because the ASID field is overwritten by a TLBR instruction, software must save and restore the value of ASID around use of the TLBR. This is especially important in TLB Invalid and TLB Modified exceptions, and in other memory management software.
The VPNX2 and VPN2 fields of the EntryHi register are not defined after an address error exception and these fields may be modified by hardware during the address error exception sequence.Software writes of the EntryHi register (via MTC0) do not cause the implicit write of address-related fields in the BadVAddr or Context registers.
Figure 9-17 shows the format of the EntryHi register; Table 9.23 describes the EntryHi register fields.
Figure 9-17 EntryHi Register Format
13 12 11 10 8 7 0
Table 9.23 EntryHi Register Field Descriptions
9.17 EntryHi Register (CP0 Register 10, Select 0)
VPN2
VPN2X
0
ASID
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
VPN2
31..13
VA31..13 of the virtual address (virtual page number / 2). This field is written by hardware on a TLB exception or on a TLB read, and is written by software before a TLB write.
R/W
Undefined
Required
VPN2X
12..11
In Release 2 of the Architecture (and subsequent releases), the VPN2X field is an extension to the VPN2 field to support 1KB pages. These bits are not writable by either hardware or software unless Config3SP = 1 and PageGrainESP = 1. If enabled for write, this field con- tains VA12..11 of the virtual address and is written by hardware on a TLB exception or on a TLB read, and is by software before a TLB write.
If writes are not enabled, and in implementations of Release 1 of the Architecture, this field must be written with zero and returns zeros on read.
R/W
0
Required (Release 2 and 1KB Page Sup- port)
0
10..8
Must be written as zero; returns zero on read.
0
0
Reserved
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Table 9.23 EntryHi Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
ASID
7..0
Address space identifier. This field is written by hard- ware on a TLB read and by software to establish the cur- rent ASID value for TLB write and against which TLB references match each entry’s TLB ASID field.
R/W
Undefined
Required (TLB MMU)
Programming Note:
In implementations of Release 2 (and subsequent releases) of the Architecture, the VPN2X field of the EntryHi regis- ter must be written with zero and the TLB must be flushed before each instance in which the value of the PageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.
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9.18 Compare Register (CP0 Register 11, Select 0)
Compliance Level: Required.
The Compare register acts in conjunction with the Count register to implement a timer and timer interrupt function.
The Compare register maintains a stable value and does not change on its own.
When the value of the Count register equals the value of the Compare register, an interrupt request is made. In Release 1 of the architecture, this request is combined in an implementation-dependent way with hardware interrupt 5 to set interrupt bit IP(7) in the Cause register. In Release 2 (and subsequent releases) of the Architecture, the pres- ence of the interrupt is visible to software via the CauseTI bit and is combined in an implementation-dependent way with a hardware or software interrupt. For Vectored Interrupt Mode, the interrupt is at the level specified by the IntCtlIPTI field.
For diagnostic purposes, the Compare register is a read/write register. In normal use however, the Compare register is write-only. Writing a value to the Compare register, as a side effect, clears the timer interrupt. Figure 9-18 shows the format of the Compare register; Table 9.24 describes the Compare register fields.
Figure 9-18 Compare Register Format
31 0
Table 9.24 Compare Register Field Descriptions
Programming Note:
In Release 2 of the Architecture, the EHB instruction can be used to make interrupt state changes visible when the Compare register is written. See 6.1.2.1 “Software Hazards and the Interrupt System” on page 54.
9.19 Reserved for Implementations (CP0 Register 11, Selects 6 and 7)
Compliance Level: Implementation Dependent.
CP0 register 11, Selects 6 and 7 are reserved for implementation dependent use and are not defined by the architec-
ture.
9.18 Compare Register (CP0 Register 11, Select 0)
Compare
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Compare
31..0
Interval count compare value
R/W
Undefined
Required
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9.20 Status Register (CP Register 12, Select 0)
31
Compliance Level: Required.
The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Fields of this register combine to create operating modes for the processor. Refer to “MIPS32 and microMIPS32 Operating Modes” on page 19 for a discussion of operating modes, and “Interrupts” on page 43 for a discussion of interrupt modes.
Figure 9-19 shows the format of the Status register; Table 9.25 describes the Status register fields.
Figure 9-19 Status Register Format
28 27 26 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0
Table 9.25 Status Register Field Descriptions
CU3..CU0
RP
FR
RE
MX
0
BEV
TS
SR
NMI
ASE
Impl
IM7..IM2
IM1..IM0
0
UM
R0
ERL
EXL
IE
IPL
KSU
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CU (CU3.. CU0)
31..28
Controls access to coprocessors 3, 2, 1, and 0, respec- tively:
Coprocessor 0 is always usable when the processor is running in Kernel Mode or Debug Mode, independent of the state of the CU0 bit.
In Release 2 (and subsequent releases) of the Architec- ture, and for 64-bit implementations of Release 1 of the Architecture, execution of all floating point instructions, including those encoded with the COP1X opcode, is controlled by the CU1 enable. CU3 is no longer used and is reserved for future use by the Architecture.
If there is no provision for connecting a coprocessor, the corresponding CU bit must be ignored on write and read as zero.
Encoding
Meaning
0
Access not allowed
1
Access allowed
R/W
Undefined
Required for all implemented coprocessors
RP
27
Enables reduced power mode on some implementations. The specific operation of this bit is implementation dependent.
If this bit is not implemented, it must be ignored on write and read as zero. If this bit is implemented, the reset state must be zero so that the processor starts at full perfor- mance.
R/W
0
Optional
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Table 9.25 Status Register Field Descriptions (Continued)
9.20 Status Register (CP Register 12, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
FR
26
In Release 1 of the Architecture, only MIPS64 proces- sors could implement a 64-bit floating point unit. In Release 2 of the Architecture (and subsequent releases) , both 32-bit and 64-bit processors can implement a 64-bit floating point unit. This bit is used to control the floating point register mode for 64-bit floating point units:
This bit must be ignored on write and read as zero under the following conditions:
• No floating point unit is implemented
• In a MIPS32 implementation of Release 1 of the
Architecture
• In an implementation of Release 2 of the Architecture
(and subsequent releases) in which a 64-bit floating
point unit is not implemented
Certain combinations of the FR bit and other state or operations can cause UNPREDICTABLE behavior. See “64-bit FPR Enable” on page 20 for a discussion of these combinations.
When software changes the value of this bit, the contents of the floating point registers are UNPREDICTABLE.
Encoding
Meaning
0
Floating point registers can contain any 32-bit datatype. 64-bit datatypes are stored in even-odd pairs of regis- ters.
1
Floating point registers can contain any datatype
R/W
Undefined
Required
RE
25
Used to enable reverse-endian memory references while the processor is running in user mode:
Neither Debug Mode nor Kernel Mode nor Supervisor Mode references are affected by the state of this bit.
If this bit is not implemented, it must be ignored on write and read as zero.
Encoding
Meaning
0
User mode uses configured endian- ness
1
User mode uses reversed endianness
R/W
Undefined
Optional
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Table 9.25 Status Register Field Descriptions (Continued)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
MX
24
Enables access to MDMXTM and MIPS® DSP resources on processors implementing one of these ASEs. If nei- ther the MDMX nor the MIPS DSP ASE is imple- mented, this bit must be ignored on write and read as zero.
Encoding
Meaning
0
Access not allowed
1
Access allowed
R if the processor imple- ments nei- ther the MDMX nor the MIPS DSP ASEs; oth- erwise R/W
0 if the processor imple- ments nei- ther the MDMX nor the MIPS DSP ASEs; oth- erwise Undefined
Optional
BEV
22
Controls the location of exception vectors:
See “Exception Vector Locations” on page 57 for details.
Encoding
Meaning
0
Normal
1
Bootstrap
R/W
1
Required
TS1
21
Indicates that the TLB has detected a match on multiple entries. It is implementation dependent whether this detection occurs at all, on a write to the TLB, or an access to the TLB. In Release 2 of the Architecture (and subsequent releases), multiple TLB matches may only be reported on a TLB write. When such a detection occurs, the processor initiates a machine check exception and sets this bit. It is implementation depen- dent whether this condition can be corrected by soft- ware. If the condition can be corrected, this bit should be cleared by software before resuming normal operation. See “TLB Initialization” on page 31 for a discussion of software TLB initialization used to avoid a machine check exception during processor initialization.
If this bit is not implemented, it must be ignored on write and read as zero.
Software should not write a 1 to this bit when its value is a 0, thereby causing a 0-to-1 transition. If such a transi- tion is caused by software, it is UNPREDICTABLE whether hardware ignores the write, accepts the write with no side effects, or accepts the write and initiates a machine check exception.
R/W
0
Required if the processor detects and reports a match on multiple TLB entries
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Table 9.25 Status Register Field Descriptions (Continued)
9.20 Status Register (CP Register 12, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
SR
20
Indicates that the entry through the reset exception vec- tor was due to a Soft Reset:
If this bit is not implemented, it must be ignored on write and read as zero.
Software should not write a 1 to this bit when its value is a 0, thereby causing a 0-to-1 transition. If such a transi- tion is caused by software, it is UNPREDICTABLE whether hardware ignores or accepts the write.
Encoding
Meaning
0
Not Soft Reset (NMI or Reset)
1
Soft Reset
R/W
1 for Soft Reset; 0 otherwise
Required if Soft Reset is imple- mented
NMI
19
Indicates that the entry through the reset exception vec- tor was due to an NMI exception:
If this bit is not implemented, it must be ignored on write and read as zero.
Software should not write a 1 to this bit when its value is a 0, thereby causing a 0-to-1 transition. If such a transi- tion is caused by software, it is UNPREDICTABLE whether hardware ignores or accepts the write.
Encoding
Meaning
0
Not NMI (Soft Reset or Reset)
1
NMI
R/W
1 for NMI; 0 otherwise
Required if NMI is implemented
ASE
18
This bit is reserved for the MCU ASE.
If MCU ASE is not implemented, then this bit must be written as zero; returns zero on read.
0 if MCU ASE is not imple- mented
0 if MCU ASE is not imple- mented
Required for MCU ASE; Otherwise Reserved
Impl
17..16
These bits are implementation dependent and are not defined by the architecture. If they are not implemented, they must be ignored on write and read as zero.
Undefined
Optional
IM7..IM2
15..10
Interrupt Mask: Controls the enabling of each of the hardware interrupts. Refer to “Interrupts” on page 43 for a complete discussion of enabled interrupts.
In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled (Config3VEIC = 1), these bits take on a different meaning and are interpreted as the IPL field, described below.
Encoding
Meaning
0
Interrupt request disabled
1
Interrupt request enabled
R/W
Undefined
Required
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Table 9.25 Status Register Field Descriptions (Continued)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IPL
15..10
Interrupt Priority Level.
In implementations of Release 2 of the Architecture (and subsequent releases) in which EIC interrupt mode is enabled (Config3VEIC = 1), this field is the encoded (0..63) value of the current IPL. An interrupt will be sig- naled only if the requested IPL is higher than this value. If EIC interrupt mode is not enabled (Config3VEIC = 0), these bits take on a different meaning and are interpreted as the IM7..IM2 bits, described above.
R/W
Undefined
Optional (Release 2 and EIC interrupt mode only)
IM1..IM0
9..8
Interrupt Mask: Controls the enabling of each of the soft- ware interrupts. Refer to “Interrupts” on page 43 for a complete discussion of enabled interrupts.
In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled (Config3VEIC = 1), these bits are writable, but have no effect on the interrupt system.
Encoding
Meaning
0
Interrupt request disabled
1
Interrupt request enabled
R/W
Undefined
Required
0
,23,7:5
Must be written as zero; returns zero on reads
R
0
Reserved
KSU
4..3
If Supervisor Mode is implemented, the encoding of this field denotes the base operating mode of the processor. See “MIPS32 and microMIPS32 Operating Modes” on page 19 for a full discussion of operating modes. The encoding of this field is:
Note: This field overlaps the UM and R0 fields, described below.
Encoding
Meaning
0b00
Base mode is Kernel Mode
0b01
Base mode is Supervisor Mode
0b10
Base mode is User Mode
0b11
Reserved. The operation of the pro- cessor is UNDEFINED if this value is written to the KSU field
R/W
Undefined
Required if Supervisor Mode is imple- mented; Optional other- wise
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Table 9.25 Status Register Field Descriptions (Continued)
9.20 Status Register (CP Register 12, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
UM
4
If Supervisor Mode is not implemented, this bit denotes the base operating mode of the processor. See “MIPS32 and microMIPS32 Operating Modes” on page 19 for a full discussion of operating modes. The encoding of this bit is:
Note: This bit overlaps the KSU field, described above.
Encoding
Meaning
0
Base mode is Kernel Mode
1
Base mode is User Mode
R/W
Undefined
Required
R0
3
If Supervisor Mode is not implemented, this bit is reserved. This bit must be ignored on write and read as zero.
Note: This bit overlaps the KSU field, described above.
R
0
Reserved
ERL
2
Error Level; Set by the processor when a Reset, Soft Reset, NMI or Cache Error exception are taken.
When ERL is set:
• The processor is running in kernel mode
• Hardware and software interrupts are disabled
• The ERET instruction will use the return address held
in ErrorEPC instead of EPC
• Segment kuseg is treated as an unmapped and
uncached region. See “Address Translation for the kuseg Segment when StatusERL = 1” on page 29. This allows main memory to be accessed in the presence of cache errors. The operation of the processor is
UNDEFINED if the ERL bit is set while the proces- sor is executing instructions from kuseg.
Encoding
Meaning
0
Normal level
1
Error level
R/W
1
Required
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Table 9.25 Status Register Field Descriptions (Continued)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
EXL
1
Exception Level; Set by the processor when any excep- tion other than Reset, Soft Reset, NMI or Cache Error exception are taken.
When EXL is set:
• The processor is running in Kernel Mode
• Hardware and software interrupts are disabled.
• TLB Refill exceptions use the general exception vec-
tor instead of the TLB Refill vector.
• EPC, CauseBD and SRSCtl (implementations of
Release 2 of the Architecture only) will not be updated if another exception is taken
Encoding
Meaning
0
Normal level
1
Exception level
R/W
Undefined
Required
IE
0
Interrupt Enable: Acts as the master enable for software and hardware interrupts:
In Release 2 of the Architecture (and subsequent releases), this bit may be modified separately via the DI and EI instructions.
Encoding
Meaning
0
Interrupts are disabled
1
Interrupts are enabled
R/W
Undefined
Required
1. The TS bit originally indicated a “TLB Shutdown” condition in which circuits detected multiple TLB matches and shutdown the TLB to prevent physical damage. In newer designs, multiple TLB matches do not cause physical damage to the TLB structure, so the TS bit retains its name, but is simply an indicator to the machine check exception handler that multiple TLB matches were detected and reported by the processor.
Programming Note:
In Release 2 of the Architecture, the EHB instruction can be used to make interrupt state changes visible when the IM, IPL, ERL, EXL, or IE fields of the Status register are written. See “Software Hazards and the Interrupt System” on page 54.
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9.21 IntCtl Register (CP0 Register 12, Select 1)
31
Compliance Level: Required (Release 2).
The IntCtl register controls the expanded interrupt capability added in Release 2 of the Architecture, including vec- tored interrupts and support for an external interrupt controller. This register does not exist in implementations of Release 1 of the Architecture.
Figure 9-20 shows the format of the IntCtl register; Table 9.26 describes the IntCtl register fields. .
Figure 9-20 IntCtl Register Format
29 28 26 25 23 22 14 13 10 9 5 4 0
Table 9.26 IntCtl Register Field Descriptions
9.21 IntCtl Register (CP0 Register 12, Select 1)
IPTI
IPPCI
IPFDC
MCU ASE
0000
VS
0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IPTI
31..29
For Interrupt Compatibility and Vectored Interrupt modes, this field specifies the IP number to which the Timer Interrupt request is merged, and allows software to determine whether to consider CauseTI for a potential interrupt.
Encoding
IP bit
Hardware Interrupt Source
2
2
HW0
3
3
HW1
4
4
HW2
5
5
HW3
6
6
HW4
7
7
HW5
The value of this field is UNPREDICTABLE if Exter- nal Interrupt Controller Mode is both implemented and enabled. The external interrupt controller is expected to provide this information for that interrupt mode.
R
Preset or Externally Set
Required
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Table 9.26 IntCtl Register Field Descriptions (Continued)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IPPCI
28..26
For Interrupt Compatibility and Vectored Interrupt modes, this field specifies the IP number to which the Performance Counter Interrupt request is merged, and allows software to determine whether to consider CausePCI for a potential interrupt.
Encoding
IP bit
Hardware Interrupt Source
2
2
HW0
3
3
HW1
4
4
HW2
5
5
HW3
6
6
HW4
7
7
HW5
The value of this field is UNPREDICTABLE if Exter- nal Interrupt Controller Mode is both implemented and enabled. The external interrupt controller is expected to provide this information for that interrupt mode.
If performance counters are not implemented (Config1PC = 0), this field returns zero on read.
R
Preset or Externally Set
Optional (Performance Counters Implemented)
IPFDC
25..23
For Interrupt Compatibility and Vectored Interrupt modes, this field specifies the IP number to which the Fast Debug Channel Interrupt request is merged, and allows software to determine whether to consider CauseFDC for a potential interrupt.
Encoding
IP bit
Hardware Interrupt Source
2
2
HW0
3
3
HW1
4
4
HW2
5
5
HW3
6
6
HW4
7
7
HW5
The value of this field is UNPREDICTABLE if Exter- nal Interrupt Controller Mode is both implemented and enabled. The external interrupt controller is expected to provide this information for that interrupt mode.
If EJTAG FDC is not implemented, this field returns zero on read.
R
Preset or Externally Set
Optional (EJTAG Fast Debug Chan- nel Imple- mented)
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Table 9.26 IntCtl Register Field Descriptions (Continued)
9.21 IntCtl Register (CP0 Register 12, Select 1)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
MCU ASE
22..14
These bits are reserved for the MicroController ASE.
If that ASE is not implemented, must be written as zero; returns zero on read.
0
0
Reserved
0
..10
Must be written as zero; returns zero on read.
0
0
Reserved
VS
9..5
Vector Spacing. If vectored interrupts are implemented (as denoted by Config3VInt or Config3VEIC), this field specifies the spacing between vectored interrupts.
Encoding
Spacing Between Vectors
(hex)
(decimal)
0x00
0x000
0
0x01
0x020
32
0x02
0x040
64
0x04
0x080
128
0x08
0x100
256
0x10
0x200
512
All other values are reserved. The operation of the pro- cessor is UNDEFINED if a reserved value is written to this field.
If neither EIC interrupt mode nor VI mode are imple- mented (Config3VEIC = 0 and Config3VINT = 0), this field is ignored on write and reads as zero.
R/W
0
Optional
0
4..0
Must be written as zero; returns zero on read.
0
0
Reserved
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9.22 SRSCtl Register (CP0 Register 12, Select 2)
Compliance Level: Required (Release 2).
The SRSCtl register controls the operation of GPR shadow sets in the processor. This register does not exist in imple-
mentations of the architecture prior to Release 2.
Figure 9-21 shows the format of the SRSCtl register; Table 9.27 describes the SRSCtl register fields.
Figure 9-21 SRSCtl Register Format
31 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 0
Table 9.27 SRSCtl Register Field Descriptions
0 00
HSS
0 00 00
EICSS
0 00
ESS
0 00
PSS
0 00
CSS
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
0
31..30
Must be written as zeros; returns zero on read.
0
0
Reserved
HSS
29..26
Highest Shadow Set. This field contains the highest shadow set number that is implemented by this proces- sor. A value of zero in this field indicates that only the normal GPRs are implemented. A non-zero value in this field indicates that the implemented shadow sets are numbered 0..n, where n is the value of the field.
The value in this field also represents the highest value that can be written to the ESS, EICSS, PSS, and CSS fields of this register, or to any of the fields of the SRSMap register. The operation of the processor is UNDEFINED if a value larger than the one in this field is written to any of these other values.
R
Preset
Required
0
25..22
Must be written as zeros; returns zero on read.
0
0
Reserved
EICSS
21..18
EIC interrupt mode shadow set. If Config3VEIC is 1 (EIC interrupt mode is enabled), this field is loaded from the external interrupt controller for each interrupt request and is used in place of the SRSMap register to select the current shadow set for the interrupt.
See “External Interrupt Controller Mode” on page 50 for a discussion of EIC interrupt mode. If Config3VEIC is 0, this field must be written as zero, and returns zero on read.
R
Undefined
Required (EIC inter- rupt mode only)
0
17..16
Must be written as zeros; returns zero on read.
0
0
Reserved
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Table 9.27 SRSCtl Register Field Descriptions (Continued)
9.22 SRSCtl Register (CP0 Register 12, Select 2)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
ESS
15..12
Exception Shadow Set. This field specifies the shadow set to use on entry to Kernel Mode caused by any excep- tion other than a vectored interrupt.
The operation of the processor is UNDEFINED if soft- ware writes a value into this field that is greater than the value in the HSS field.
R/W
0
Required
0
11..10
Must be written as zeros; returns zero on read.
0
0
Reserved
PSS
9..6
Previous Shadow Set. If GPR shadow registers are implemented, and with the exclusions noted in the next paragraph, this field is copied from the CSS field when an exception or interrupt occurs. An ERET instruction copies this value back into the CSS field if StatusBEV = 0.
This field is not updated on any exception which sets StatusERL to 1 (i.e., NMI or cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with StatusEXL = 1, or StatusBEV = 1.
The operation of the processor is UNDEFINED if soft- ware writes a value into this field that is greater than the value in the HSS field.
R/W
0
Required
0
5..4
Must be written as zeros; returns zero on read.
0
0
Reserved
CSS
3..0
Current Shadow Set. If GPR shadow registers are imple- mented, this field is the number of the current GPR set. With the exclusions noted in the next paragraph, this field is updated with a new value on any interrupt or exception, and restored from the PSS field on an ERET. Table 9.28 describes the various sources from which the CSS field is updated on an exception or interrupt.
This field is not updated on any exception which sets StatusERL to 1 (i.e., NMI or cache error), an entry into EJTAG Debug mode, or any exception or interrupt that occurs with StatusEXL = 1, or StatusBEV = 1. Neither is it updated on an ERET with StatusERL = 1 or StatusBEV = 1.
The value of CSS can be changed directly by software only by writing the PSS field and executing an ERET instruction.
R
0
Required
Table 9.28 Sources for new SRSCtlCSS on an Exception or Interrupt
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Exception Type
Condition
SRSCtlCSS Source
Comment
Exception
All
SRSCtlESS
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Table 9.28 Sources for new SRSCtlCSS on an Exception or Interrupt
Exception Type
Condition
SRSCtlCSS Source
Comment
Non-Vectored Interrupt
CauseIV = 0
SRSCtlESS
Treat as exception
Vectored Interrupt
CauseIV = 1 and Config3VEIC = 0 and Config3VInt = 1
SRSMapVectNum ×4+3..VectNum×4
Source is internal map regis- ter
Vectored EIC Interrupt
CauseIV = 1 and Config3VEIC = 1
SRSCtlEICSS
Source is external interrupt controller.
Programming Note:
A software change to the PSS field creates an instruction hazard between the write of the SRSCtl register and the use of a RDPGPR or WRPGPR instruction. This hazard must be cleared with a JR.HB or JALR.HB instruction as described in “Hazard Clearing Instructions and Events” on page 82. A hardware change to the PSS field as the result of interrupt or exception entry is automatically cleared for the execution of the first instruction in the interrupt or exception handler.
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9.23 SRSMap Register (CP0 Register 12, Select 3)
31
Compliance Level: Required in Release 2 (and subsequent releases) of the Architecture if Additional Shadow Sets and Vectored Interrupt Mode are Implemented
The SRSMap register contains 8 4-bit fields that provide the mapping from an vector number to the shadow set num- ber to use when servicing such an interrupt. The values from this register are not used for a non-interrupt exception, or a non-vectored interrupt (CauseIV = 0 or IntCtlVS = 0). In such cases, the shadow set number comes from SRSCt-
lESS.
If SRSCtlHSS is zero, the results of a software read or write of this register are UNPREDICTABLE.
The operation of the processor is UNDEFINED if a value is written to any field in this register that is greater than the value of SRSCtlHSS.
The SRSMap register contains the shadow register set numbers for vector numbers 7..0. The same shadow set num- ber can be established for multiple interrupt vectors, creating a many-to-one mapping from a vector to a single shadow register set number.
Figure 9-22 shows the format of the SRSMap register; Table 9.29 describes the SRSMap register fields.
Figure 9-22 SRSMap Register Format
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Table 9.29 SRSMap Register Field Descriptions
9.23 SRSMap Register (CP0 Register 12, Select 3)
SSV7
SSV6
SSV5
SSV4
SSV3
SSV2
SSV1
SSV0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
SSV7
31..28
Shadow register set number for Vector Number 7
R/W
0
Required
SSV6
27..24
Shadow register set number for Vector Number 6
R/W
0
Required
SSV5
23..20
Shadow register set number for Vector Number 5
R/W
0
Required
SSV4
19..16
Shadow register set number for Vector Number 4
R/W
0
Required
SSV3
15..12
Shadow register set number for Vector Number 3
R/W
0
Required
SSV2
11..8
Shadow register set number for Vector Number 2
R/W
0
Required
SSV1
7..4
Shadow register set number for Vector Number 1
R/W
0
Required
SSV0
3..0
Shadow register set number for Vector Number 0
R/W
0
Required
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9.24 Cause Register (CP0 Register 13, Select 0)
Compliance Level: Required.
The Cause register primarily describes the cause of the most recent exception. In addition, fields also control soft- ware interrupt requests and the vector through which interrupts are dispatched. With the exception of the IP1..0, DC, IV, and WP fields, all fields in the Cause register are read-only. Release 2 of the Architecture added optional support for an External Interrupt Controller (EIC) interrupt mode, in which IP7..2 are interpreted as the Requested Interrupt Priority Level (RIPL).
Figure 9-23 shows the format of the Cause register; Table 9.30 describes the Cause register fields.
Figure 9-23 Cause Register Format
31 30 29 28 27 26 25 24 23 22 21 20 17 15 10 9 8 7 6 2 1 0
Table 9.30 Cause Register Field Descriptions
BD
TI
CE
DC
PCI
ASE
IV
WP
FD CI
000
ASE
ASE
IP9..IP2
IP1..IP0
0
Exc Code
0
RIPL
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
BD
31
Indicates whether the last exception taken occurred in a branch delay slot:
The processor updates BD only if StatusEXL was zero when the exception occurred.
Encoding
Meaning
0
Not in delay slot
1
In delay slot
R
Undefined
Required
TI
30
Timer Interrupt. In an implementation of Release 2 of the Architecture, this bit denotes whether a timer inter- rupt is pending (analogous to the IP bits for other inter- rupt types):
In an implementation of Release 1 of the Architecture, this bit must be written as zero and returns zero on read.
Encoding
Meaning
0
No timer interrupt is pending
1
Timer interrupt is pending
R
Undefined
Required (Release 2)
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Table 9.30 Cause Register Field Descriptions
9.24 Cause Register (CP0 Register 13, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CE
29..28
Coprocessor unit number referenced when a Coproces- sor Unusable exception is taken. This field is loaded by hardware on every exception, but is UNPREDICT- ABLE for all exceptions except for Coprocessor Unus- able.
R
Undefined
Required
DC
27
Disable Count register. In some power-sensitive applica- tions, the Count register is not used but may still be the source of some noticeable power dissipation. This bit allows the Count register to be stopped in such situa- tions.
In an implementation of Release 1 of the Architecture, this bit must be written as zero, and returns zero on read.
Encoding
Meaning
0
Enable counting of Count register
1
Disable counting of Count register
R/W
0
Required (Release 2)
PCI
26
Performance Counter Interrupt. In an implementation of Release 2 of the Architecture (and subsequent releases), this bit denotes whether a performance counter interrupt is pending (analogous to the IP bits for other interrupt types):
In an implementation of Release 1 of the Architecture, or if performance counters are not implemented (Config1PC = 0), this bit must be written as zero and returns zero on read.
Encoding
Meaning
0
No performance counter interrupt is pending
1
Performance counter interrupt is pending
R
Undefined
Required (Release 2 and performance counters imple- mented)
ASE
25:24, 17:16
These bits are reserved for the MCU ASE.
If MCU ASE is not implemented, these bits return zero on reads and must be written with zeros.
Rrequired for MCU ASE; Otherwise Reserved
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Table 9.30 Cause Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IV
23
Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector:
In implementations of Release 2 of the architecture (and subsequent releases), if the CauseIV is 1 and StatusBEV is 0, the special interrupt vector represents the base of the vectored interrupt table.
Encoding
Meaning
0
Use the general exception vector (0x180)
1
Use the special interrupt vector (0x200)
R/W
Undefined
Required
WP
22
Indicates that a watch exception was deferred because StatusEXL or StatusERL were a one at the time the watch exception was detected. This bit both indicates that the watch exception was deferred, and causes the exception to be initiated once StatusEXL and StatusERL are both zero. As such, software must clear this bit as part of the watch exception handler to prevent a watch exception loop.
Software should not write a 1 to this bit when its value is a 0, thereby causing a 0-to-1 transition. If such a transi- tion is caused by software, it is UNPREDICTABLE whether hardware ignores the write, accepts the write with no side effects, or accepts the write and initiates a watch exception once StatusEXL and StatusERL are both zero.
If watch registers are not implemented, this bit must be ignored on write and read as zero.
R/W
Undefined
Required if watch registers are implemented
FDCI
21
Fast Debug Channel Interrupt. This bit denotes whether a FDC interrupt is pending :
Encoding
Meaning
0
No FDCinterrupt is pending
1
FDC interrupt is pending
R
Undefined
Required
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Table 9.30 Cause Register Field Descriptions
9.24 Cause Register (CP0 Register 13, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IP7..IP2
15..10
Indicates an interrupt is pending:
Bit
Name
15
IP7
14
IP6
13
IP5
12
IP4
11
IP3
10
IP2
Meaning
Hardware interrupt 5 Hardware interrupt 4 Hardware interrupt 3 Hardware interrupt 2 Hardware interrupt 1 Hardware interrupt 0
In implementations of Release 1 of the Architecture, timer and performance counter interrupts are combined in an implementation-dependent way with hardware interrupt 5.
In implementations of Release 2 of the Architecture (and subsequent releases) in which EIC interrupt mode is not enabled (Config3VEIC = 0), timer and performance counter interrupts are combined in an implementa- tion-dependent way with any hardware interrupt. If EIC interrupt mode is enabled (Config3VEIC = 1), these bits take on a different meaning and are interpreted as the RIPL field, described below.
R
Undefined
Required
RIPL
..10
Requested Interrupt Priority Level.
In implementations of Release 2 of the Architecture (and subsequent releases) in which EIC interrupt mode is enabled (Config3VEIC = 1), this field is the encoded (0..63) value of the requested interrupt. A value of zero indicates that no interrupt is requested.
If EIC interrupt mode is not enabled (Config3VEIC = 0), these bits take on a different meaning and are interpreted as the IP..IP2 bits, described above.
R
Undefined
Optional (Release 2 and EIC interrupt mode only)
IP1..IP0
9..8
Controls the request for software interrupts:
An implementation of Release 2 of the Architecture (and subsequent releases) which also implements EIC inter- rupt mode exports these bits to the external interrupt controller for prioritization with other interrupt sources.
Bit
Name
Meaning
9
IP1
Request software interrupt 1
8
IP0
Request software interrupt 0
R/W
Undefined
Required
ExcCode
6..2
Exception code – see Table 9.31
R
Undefined
Required
0
20..16, 7, 1..0
Must be written as zero; returns zero on read.
0
0
Reserved
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Table 9.31 Cause Register ExcCode Field
Exception Code Value
Mnemonic
Description
Decimal
Hexadecimal
0
0x00
Int
Interrupt
1
0x01
Mod
TLB modification exception
2
0x02
TLBL
TLB exception (load or instruction fetch)
3
0x03
TLBS
TLB exception (store)
4
0x04
AdEL
Address error exception (load or instruction fetch)
5
0x05
AdES
Address error exception (store)
6
0x06
IBE
Bus error exception (instruction fetch)
7
0x07
DBE
Bus error exception (data reference: load or store)
8
0x08
Sys
Syscall exception
9
0x09
Bp
Breakpoint exception. If EJTAG is implemented and an SDBBP instruction is executed while the processor is running in EJTAG Debug Mode, this value is written to the DebugDExcCode field to denote an SDBBP in Debug Mode.
10
0x0a
RI
Reserved instruction exception
11
0x0b
CpU
Coprocessor Unusable exception
12
0x0c
Ov
Arithmetic Overflow exception
13
0x0d
Tr
Trap exception
14
0x0e
–
Reserved
15
0x0f
FPE
Floating point exception
16-17
0x10-0x11
–
Available for implementation dependent use
18
0x12
C2E
Reserved for precise Coprocessor 2 exceptions
19
0x13
TLBRI
TLB Read-Inhibit exception
20
0x14
TLBXI
TLB Execution-Inhibit exception
21
0x15
–
Reserved
22
0x16
MDMX
MDMX Unusable Exception (MDMX ASE)
23
0x17
WATCH
Reference to WatchHi/WatchLo address
24
0x18
MCheck
Machine check
25
0x19
Thread
Thread Allocation, Deallocation, or Scheduling Exceptions (MIPS® MT ASE)
26
0x1A
DSPDis
DSP ASE State Disabled exception (MIPS® DSP ASE)
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Table 9.31 Cause Register ExcCode Field
9.24 Cause Register (CP0 Register 13, Select 0)
Exception Code Value
Mnemonic
Description
Decimal
Hexadecimal
27-29
0x20-0x1d
–
Reserved
30
0x1e
CacheErr
Cache error. In normal mode, a cache error exception has a dedi- cated vector and the Cause register is not updated. If EJTAG is implemented and a cache error occurs while in Debug Mode, this code is written to the DebugDExcCode field to indicate that re-entry to Debug Mode was caused by a cache error.
31
0x1f
–
Reserved
Programming Note:
In Release 2 of the Architecture (and the subsequent releases), the EHB instruction can be used to make interrupt state changes visible when the IP1..0 field of the Cause register is written. See “Software Hazards and the Interrupt System” on page 54.
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9.25 Exception Program Counter (CP0 Register 14, Select 0)
Compliance Level: Required.
The Exception Program Counter (EPC) is a read/write register that contains the address at which processing
resumes after an exception has been serviced. All bits of the EPC register are significant and must be writable. Unless the EXL bit in the Status register is already a 1, the processor writes the EPC register when an exception
occurs.
• For synchronous (precise) exceptions, EPC contains either:
• the virtual address of the instruction that was the direct cause of the exception, or
• the virtual address of the immediately preceding branch or jump instruction, when the exception causing
instruction is in a branch delay slot, and the Branch Delay bit in the Cause register is set.
• For asynchronous (imprecise) exceptions, EPC contains the address of the instruction at which to resume execu-
tion.
The processor reads the EPC register as the result of execution of the ERET instruction.
Software may write the EPC register to change the processor resume address and read the EPC register to determine at what address the processor will resume.
Figure 9-24 shows the format of the EPC register; Table 9.32 describes the EPC register fields.
Figure 9-24 EPC Register Format
31 0
Table 9.32 EPC Register Field Descriptions
9.25.1 Special Handling of the EPC Register in Processors That Implement the MIPS16e ASE or the microMIPS32 Base Architectures
In processors that implement the MIPS16e ASE or microMIPS32 base architecture, the EPC register requires special handling.
When the processor writes the EPC register, it combines the address at which processing resumes with the value of the ISA Mode register:
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EPC
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
EPC
31..0
Exception Program Counter
R/W
Undefined
Required
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EPC ← resumePC31..1 || ISAMode0
9.25 Exception Program Counter (CP0 Register 14, Select 0)
“resumePC” is the address at which processing resumes, as described above.
When the processor reads the EPC register, it distributes the bits to the PC and ISAMode registers: PC ← EPC31..1 || 0
ISAMode ← EPC0
Software reads of the EPC register simply return to a GPR the last value written with no interpretation. Software
writes to the EPC register store a new value which is interpreted by the processor as described above.
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9.26 Processor Identification (CP0 Register 15, Select 0)
31
Compliance Level: Required.
The Processor Identification (PRId) register is a 32 bit read-only register that contains information identifying the manufacturer, manufacturer options, processor identification and revision level of the processor. Figure 9-25 shows the format of the PRId register; Table 9.33 describes the PRId register fields.
Figure 9-25 PRId Register Format
24 23 16 15 8 7 0
Table 9.33 PRId Register Field Descriptions
Company Options
Company ID
Processor ID
Revision
Name
Company Options
Company ID
Processor ID
Fields
Bits
31..24
23..16
15..8
Description
Available to the designer or manufacturer of the proces- sor for company-dependent options. The value in this field is not specified by the architecture. If this field is not implemented, it must read as zero.
Identifies the company that designed or manufactured the processor.
Software can distinguish a MIPS32/microMIPS32 or MIPS64/microMIPS64 processor from one implement- ing an earlier MIPS ISA by checking this field for zero. If it is non-zero the processor implements the MIPS32/microMIPS32 or MIPS64/microMIPS64 Architecture.
Company IDs are assigned by MIPS Technologies when a MIPS32/microMIPS32 or MIPS64/microMIPS64 license is acquired. The encodings in this field are:
Read / Write
R
R
Reset State
Preset
Preset
Compliance
Optional
Required
Encoding
0
1
2-255
MIPS Technologies, Inc.
Meaning
Not a MIPS32/microMIPS32 or MIPS64/microMIPS64 processor
Contact MIPS Technologies, Inc. for the list of Company ID assignments
Identifies the type of processor. This field allows soft- ware to distinguish between various processor imple- mentations within a single company, and is qualified by the CompanyID field, described above. The combination of the CompanyID and ProcessorID fields creates a unique number assigned to each processor implementa- tion.
R
Preset
Required
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9.26 Processor Identification (CP0 Register 15, Select 0)
Table 9.33 PRId Register Field Descriptions
Software should not use the fields of this register to infer configuration information about the processor. Rather, the configuration registers should be used to determine the capabilities of the processor. Programmers who identify cases in which the configuration registers are not sufficient, requiring them to revert to check on the PRId register value, should send email to support@mips.com, reporting the specific case.
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Revision
7..0
Specifies the revision number of the processor. This field allows software to distinguish between one revision and another of the same processor type. If this field is not implemented, it must read as zero.
R
Preset
Optional
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9.27 EBase Register (CP0 Register 15, Select 1)
Compliance Level: Required (Release 2).
The EBase register is a read/write register containing the base address of the exception vectors used when StatusBEV equals 0, and a read-only CPU number value that may be used by software to distinguish different processors in a multi-processor system.
The EBase register provides the ability for software to identify the specific processor within a multi-processor sys- tem, and allows the exception vectors for each processor to be different, especially in systems composed of heteroge- neous processors. Bits 31..12 of the EBase register are concatenated with zeros to form the base of the exception vectors when StatusBEV is 0. The exception vector base address comes from the fixed defaults (see 6.2.2 “Exception Vector Locations” on page 57) when StatusBEV is 1, or for any EJTAG Debug exception. The reset state of bits 31..12 of the EBase register initialize the exception base register to 0x8000.0000, providing backward compatibility with Release 1 implementations.
Bits 31..30 of the EBase register are fixed with the value 0b10,and the addition of the base address and the excep- tion offset is done inhibiting a carry between bit 29 and bit 30 of the final exception address. The combination of these two restrictions forces the final exception address to be in the kseg0 or kseg1 unmapped virtual address seg- ments. For cache error exceptions, bit 29 is forced to a 1 in the ultimate exception base address so that this exception always runs in the kseg1 unmapped, uncached virtual address segment.
If the value of the exception base register is to be changed, this must be done with StatusBEV equal 1. The operation of the processor is UNDEFINED if the Exception Base field is written with a different value when StatusBEV is 0.
Figure 9-26 shows the format of the EBase register; Table 9.34 describes the EBase register fields.
Figure 9-26 EBase Register Format
31 30 29 12 11 10 9 0
Table 9.34 EBase Register Field Descriptions
1
0
Exception Base
00
CPUNum
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
1
31
This bit is ignored on write and returns one on read.
R
1
Required
0
30
This bit is ignored on write and returns zero on read.
R
0
Required
Exception Base
29..12
In conjunction with bits 31..30, this field specifies the base address of the exception vectors when StatusBEV is zero.
R/W
0
Required
0
11..10
Must be written as zero; returns zero on read.
0
0
Reserved
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Table 9.34 EBase Register Field Descriptions
9.27 EBase Register (CP0 Register 15, Select 1)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CPUNum
9..0
This field specifies the number of the CPU in a multi-processor system and can be used by software to distinguish a particular processor from the others. The value in this field is set by inputs to the processor hard- ware when the processor is implemented in the system environment. In a single processor system, this value should be set to zero.
This field can also be read via RDHWR register 0
R
Preset or Exter- nally Set
Required
Programming Note:
Software must set EBase15..12 to zero in all bit positions less than or equal to the most significant bit in the vector off- set. This situation can only occur when a vector offset greater than 0xFFF is generated when an interrupt occurs with
VI or EIC interrupt mode enabled. The operation of the processor is UNDEFINED if this condition is not met. Table 9.35 shows the conditions under which each EBase bit must be set to zero. VN represents the interrupt vector number as described in Table 6.4 and the bit must be set to zero if any of the relationships in the row are true. No EBase bits must be set to zero if the interrupt vector spacing is 32 (or zero) bytes.
Table 9.35 Conditions Under Which EBase15..12 Must Be Zero
Interrupt Vector Spacing in Bytes (IntCtlVS1)
EBase bit
32
64
128
256
512
15
None
None
None
None
VN ≥ 63
14
None
None
VN ≥ 62
VN ≥ 31
13
None
VN ≥ 60
VN ≥ 30
VN ≥ 15
12
VN ≥ 56
VN ≥ 28
VN ≥ 14
VN ≥ 7
1. See Table 9.26 on page 127
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9.28 CDMMBase Register (CP0 Register 15, Select 2)
31
Compliance Level: Optional.
The 36-bit physical base address for the Common Device Memory Map facility is defined by this register. This regis-
ter only exists if Config3CDMM is set to one.
For devices that implement multiple VPEs, access to this register is controlled by the VPEConf0MVP register field. If
the MVP bit is cleared, a read to this register returns all zeros and a write to this register is ignored. Figure 9.27 has the format of the CDMMBase register, and Table 9.36 describes the register fields.
Figure 9.27 CDMMBase Register
11 10 9 8 0
Table 9.36 CDMMBase Register Field Descriptions
CDMM_UPPER_ADDR
EN
CI
CDMMSize
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CDMM_UP PER_ADDR
31:11
Bits 35:15 of the base physical address of the memory mapped registers.
The number of implemented physical address bits is implementation specific. For the unimplemented address bits – writes are ignored, returns zero on read.
R/W
Undefined
Required
EN
10
Enables the CDMM region.
If this bit is cleared, memory requests to this address region go to regular system memory. If this bit is set, memory requests to this region go to the CDMM logic
Encoding
Meaning
0
CDMM Region is disabled.
1
CDMM Region is enabled.
R/W
0
Required
CI
9
If set to 1, this indicates that the first 64-byte Device Reg- ister Block of the CDMM is reserved for additional regis- ters which manage CDMM region behavior and are not IO device registers.
R
Preset
Optional
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Table 9.36 CDMMBase Register Field Descriptions (Continued)
9.28 CDMMBase Register (CP0 Register 15, Select 2)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CDMMSize
8:0
This field represents the number of 64-byte Device Regis- ter Blocks are instantiated in the core.
Encoding
Meaning
0
1 DRB
1
2 DRBs
2
3 DRBs
…
…
511
512 DRBs
R
Preset
Required
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9.29 CMGCRBase Register (CP0 Register 15, Select 3)
31
Compliance Level: Optional.
The 36-bit physical base address for the memory-mapped Coherency Manager Global Configuration Register space is
reflected by this register. This register only exists if Config3CMGCR is set to one.
On devices that implement the MIPS MT ASE, this register is instantiated once per processor.
Figure 9.28 has the format of the CMGCRBase register, and Table 9.37 describes the register fields.
Figure 9.28 CMGCRBase Register
11 10 0
Table 9.37 CMGCRBase Register Field Descriptions
CMGCR_BASE_ADDR
0
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
CMGCR_B ASE_ADDR
31:11
Bits 35:15 of the base physical address of the memory- mapped Coherency Manager GCR registers.
This register field reflects the value of the GCR_BASE field within the memory-mapped Coherency Manager GCR Base Register.
The number of implemented physical address bits is implementation specific. For the unimplemented address bits – writes are ignored, returns zero on read.
R
Preset (IP Configu- ration Value)
Required
0
10:0
Must be written as zero; returns zero on read
0
0
Reserved
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9.30 Configuration Register (CP0 Register 16, Select 0)
Compliance Level: Required.
The Config register specifies various configuration and capabilities information. Most of the fields in the Config reg- ister are initialized by hardware during the Reset Exception process, or are constant. Three fields, K23, KU, and K0, must be initialized by software in the reset exception handler.
Figure 9-29 shows the format of the Config register; Table 9.38 describes the Config register fields.
Figure 9-29 Config Register Format
31 30 28 27 25 24 16 15 14 13 12 10 9 7 6 4 3 2 0
Table 9.38 Config Register Field Descriptions
9.30 Configuration Register (CP0 Register 16, Select 0)
M
K23
KU
Impl
BE
AT
AR
MT
0
VI
K0
Name
M
K23
KU
Impl
BE
Fields
Bits
31
30:28
27:25
24:16
15
Description
Denotes that the Config1 register is implemented at a select field value of 1.
For processors that implement a Fixed Mapping MMU, this field specifies the kseg2 and kseg3 cacheability and coherency attribute. For processors that do not imple- ment a Fixed Mapping MMU, this field reads as zero and is ignored on write.
See “Alternative MMU Organizations” on page 195 for a description of the Fixed Mapping MMU organization.
For processors that implement a Fixed Mapping MMU, this field specifies the kuseg cacheability and coherency attribute. For processors that do not implement a Fixed Mapping MMU, this field reads as zero and is ignored on write.
See “Alternative MMU Organizations” on page 195 for a description of the Fixed Mapping MMU organization.
This field is reserved for implementations. Refer to the processor specification for the format and definition of this field
Indicates the endian mode in which the processor is run- ning:
Encoding
0
1
Little endian
Big endian
Meaning
Read / Write
R
R/W
R/W
R
Reset State
1
Undefined for processors with a Fixed Map- ping MMU; 0 otherwise
Undefined for processors with a Fixed Map- ping MMU; 0 otherwise
Undefined
Preset or Exter- nally Set
Compliance
Required
Optional
Optional
Optional
Required
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Table 9.38 Config Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
AT
14:13
Architecture Type implemented by the processor.
For Release 3, encoding values of 0-2, denotes address and register width (32-bit or 64-bit).
The implemented instruction sets (MIPS32/64 and/or microMIPS32/64) are denoted by the ISA register field of Config3.
Encoding
Meaning
0
MIPS32 or microMIPS32
1
MIPS64 or microMIPS64 with access only to 32-bit compatibility segments
2
MIPS64or microMIPS64 with access to all address segments
3
Reserved
R
Preset
Required
AR
12:10
MIPS32 Architecture revision level.
microMIPS32 Architecture revision level is denoted by the MMAR field of Config3. If Config3 register is not implemented then microMIPS is not implemented.
If the ISA field of Config3 is one, then MIPS32 is not implemented and this field is not used.
Encoding
Meaning
0
Release 1
1
Release 2 or Release 3/MIPSr3
All features introduced in Release 3 are optional and detectable through Config3 register fields.
2-7
Reserved
R
Preset
Required
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Table 9.38 Config Register Field Descriptions
9.30 Configuration Register (CP0 Register 16, Select 0)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
MT
9:7
MMU Type:
Encoding
Meaning
0
None
1
Standard TLB (See “TLB Organization” on page 30)
2
BAT (See “Block Address Translation” on page 199)
3
Fixed Mapping (See “Fixed Mapping MMU” on page 195)
4
Dual VTLB and FTLB (See “Dual Variable-Page-Size and Fixed-Page-Size TLBs” on page 202)
R
Preset
Required
0
6:4
Must be written as zero; returns zero on read.
0
0
Reserved
VI
3
Virtual instruction cache (using both virtual indexing and virtual tags):
Encoding
Meaning
0
Instruction Cache is not virtual
1
Instruction Cache is virtual
R
Preset
Required
K0
2:0
Kseg0 cacheability and coherency attribute. See Table 9.9 on page 98 for the encoding of this field.
R/W
Undefined
Required
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9.31 Configuration Register 1 (CP0 Register 16, Select 1) Compliance Level: Required.
The Config1 register is an adjunct to the Config register and encodes additional capabilities information. All fields in the Config1 register are read-only.
The Icache and Dcache configuration parameters include encodings for the number of sets per way, the line size, and the associativity. The total cache size for a cache is therefore:
Cache Size = Associativity * Line Size * Sets Per Way
If the line size is zero, there is no cache implemented.
Figure 9-1 shows the format of the Config1 register; Table 9-1 describes the Config1 register fields.
Figure 9-1 Config1 Register Format
31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0
Table 9-1 Config1 Register Field Descriptions
M
MMU Size – 1
IS
IL
IA
DS
DL
DA
C2
MD
PC
WR
CA
EP
FP
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
M
31
This bit is reserved to indicate that a Config2 register is present. If the Config2 register is not implemented, this bit should read as a 0. If the Config2 register is implemented, this bit should read as a 1.
R
Preset
Required
MMU Size – 1
30..25
Number of entries in the TLB minus one. The values 0 through 63 in this field correspond to 1 to 64 TLB entries. The value zero is implied by ConfigMT having a value of ‘none’.
R
Preset
Required
IS
24:22
Icache sets per way:
Encoding
Meaning
0
64
1
128
2
256
3
512
4
1024
5
2048
6
4096
7
32
R
Preset
Required
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9.31 Configuration Register 1 (CP0 Register 16, Select 1)
Table 9-1 Config1 Register Field Descriptions
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
IL
21:19
Icache line size:
Encoding
Meaning
0
No Icache present
1
4 bytes
2
8 bytes
3
16 bytes
4
32 bytes
5
64 bytes
6
128 bytes
7
Reserved
R
Preset
Required
IA
18:16
Icache associativity:
Encoding
Meaning
0
Direct mapped
1
2-way
2
3-way
3
4-way
4
5-way
5
6-way
6
7-way
7
8-way
R
Preset
Required
DS
15:13
Dcache sets per way:
Encoding
Meaning
0
64
1
128
2
256
3
512
4
1024
5
2048
6
4096
7
32
R
Preset
Required
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Table 9-1 Config1 Register Field Descriptions
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
DL
12:10
Dcache line size:
Encoding
Meaning
0
No Dcache present
1
4 bytes
2
8 bytes
3
16 bytes
4
32 bytes
5
64 bytes
6
128 bytes
7
Reserved
R
Preset
Required
DA
9:7
Dcache associativity:
Encoding
Meaning
0
Direct mapped
1
2-way
2
3-way
3
4-way
4
5-way
5
6-way
6
7-way
7
8-way
R
Preset
Required
C2
6
Coprocessor 2 implemented:
This bit indicates not only that the processor contains support for Coprocessor 2, but that such a coprocessor is attached.
Encoding
Meaning
0
No coprocessor 2 implemented
1
Coprocessor 2 implements
R
Preset
Required
MD
5
Used to denote MDMX ASE implemented on a MIPS64/microMIPS64 processor. Not used on a MIPS32/microMIPS32 processor.
This bit indicates not only that the processor contains support for MDMX, but that such a processing element is attached.
R
0
Required
PC
4
Performance Counter registers implemented:
Encoding
Meaning
0
No performance counter registers implemented
1
Performance counter registers implemented
R
Preset
Required
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9.31 Configuration Register 1 (CP0 Register 16, Select 1)
Table 9-1 Config1 Register Field Descriptions
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
WR
3
Watch registers implemented:
Encoding
Meaning
0
No watch registers implemented
1
Watch registers implemented
R
Preset
Required
CA
2
Code compression (MIPS16e) implemented:
Encoding
Meaning
0
MIPS16e not implemented
1
MIPS16e implemented
R
Preset
Required
EP
1
EJTAG implemented:
Encoding
Meaning
0
No EJTAG implemented
1
EJTAG implemented
R
Preset
Required
FP
0
FPU implemented:
This bit indicates not only that the processor contains support for a floating point unit, but that such a unit is attached.
If an FPU is implemented, the capabilities of the FPU can be read from the capability bits in the FIR CP1 register.
Encoding
Meaning
0
No FPU implemented
1
FPU implemented
R
Preset
Required
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9.32 Configuration Register 2 (CP0 Register 16, Select 2)
Compliance Level: Required if a level 2 or level 3 cache is implemented, or if the Config3 register is required; Optional otherwise.
The Config2 register encodes level 2 and level 3 cache configurations.
Figure 9-30 shows the format of the Config2 register; Table 9.39 describes the Config2 register fields.
Figure 9-30 Config2 Register Format
31 30 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Table 9.39 Config2 Register Field Descriptions
M
TU
TS
TL
TA
SU
SS
SL
SA
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
M
31
This bit is reserved to indicate that a Config3 register is present. If the Config3 register is not implemented, this bit should read as a 0. If the Config3 register is imple- mented, this bit should read as a 1.
R
Preset
Required
TU
30:28
Implementation-specific tertiary cache control or status bits. If this field is not implemented it should read as zero and be ignored on write.
R/W
Preset
Optional
TS
27:24
Tertiary cache sets per way:
Encoding
Sets Per Way
0
64
1
128
2
256
3
512
4
1024
5
2048
6
4096
7
8192
8-15
Reserved
R
Preset
Required
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Table 9.39 Config2 Register Field Descriptions
9.32 Configuration Register 2 (CP0 Register 16, Select 2)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
TL
23:20
Tertiary cache line size:
Encoding
Line Size
0
No cache present
1
4
2
8
3
16
4
32
5
64
6
128
7
256
8-15
Reserved
R
Preset
Required
TA
19:16
Tertiary cache associativity:
Encoding
Associativity
0
Direct Mapped
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8-15
Reserved
R
Preset
Required
SU
15:12
Implementation-specific secondary cache control or sta- tus bits. If this field is not implemented it should read as zero and be ignored on write.
R/W
Preset
Optional
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Table 9.39 Config2 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
SS
11:8
Secondary cache sets per way:
Encoding
Sets Per Way
0
64
1
128
2
256
3
512
4
1024
5
2048
6
4096
7
8192
8-15
Reserved
R
Preset
Required
SL
7:4
Secondary cache line size:
Encoding
Line Size
0
No cache present
1
4
2
8
3
16
4
32
5
64
6
128
7
256
8-15
Reserved
R
Preset
Required
SA
3:0
Secondary cache associativity:
Encoding
Associativity
0
Direct Mapped
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8-15
Reserved
R
Preset
Required
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9.33 Configuration Register 3 (CP0 Register 16, Select 3)
Compliance Level: Required if any optional feature described by this register is implemented: Release 2 of the Architecture, the SmartMIPSTM ASE, or trace logic; Optional otherwise.
The Config3 register encodes additional capabilities. All fields in the Config3 register are read-only. Figure 9-31 shows the format of the Config3 register; Table 9.40 describes the Config3 register fields.
Figure 9-31 Config3 Register Format
31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1 0
9.33 Configuration Register 3 (CP0 Register 16, Select 3)
M
B P G
C M G C R
0 0000000
IPLW
MMAR
M u C o n
ISA On Exc
ISA
U L R I
R X I
D S P 2 P
D S P P
C T X T C
I T L
L P A
V E I C
V I n t
SP
CD M M
M T
SM
TL
Table 9.40 Config3 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
M
31
This bit is reserved to indicate that a Config4 register is present. If the Config4 register is not implemented, this bit should read as a 0. If the Config4 register is imple- mented, this bit should read as a 1.
R
Preset
Required
BPG
30
Big Pages feature is implemented. This bit indicates that TLB pages larger than 256 MB are supported and that C0_PageMask Register is 64-bits wide.
Encoding
Meaning
0
Big Pages are not implemented and PageMask register is 32bits wide.
1
Big Pages are implemented and Page- Mask register is 64bits wide.
R
Preset
Required
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Table 9.40 Config3 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
CMGCR
29
Coherency Manager memory-mapped Global Configura- tion Register Space is implemented.
Encoding
Meaning
0
CM GCR space is not implemented
1
CM GCR space is implemented
R
Preset
Required for Coherent Multiple -Core implementa- tions that use the Coher- ency Man- ager.
0
28:23, 12, 9, 3
Must be written as zeros; returns zeros on read
0
0
Reserved
IPLW
22:21
Width of StatusIPL and CauseRIPL fields:
If the IPL field is 8-bits in width, bits 18 and 16 of Sta- tus are used as the most significant bit and second most significant bit, respectively, of that field.
If the RIPL field is 8-bits in width, bits 17 and 16 of Cause are used as the most significant bit and second most significant bit, respectively, of that field.
Encoding
Meaning
0
IPL and RIPL fields are 6-bits in width.
1
IPL and RIPL fields are 8-bits in width.
Others
Reserved.
R
Preset
Required if MCU ASE is implemented
MMAR
20:18
microMIPS32 Architecture revision level.
MIPS32 Architecture revision level is denoted by the
AR field of Config.
If ISA field of Config3 is zero, then microMIPS32 is not implemented and this field is not used.
Encoding
Meaning
0
Release3/MIPSr3
1-7
Reserved
R
Preset
Required if microMIPS is implemented
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Table 9.40 Config3 Register Field Descriptions
9.33 Configuration Register 3 (CP0 Register 16, Select 3)
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
MCU
17
MIPS® MCU ASE is implemented.
Encoding
Meaning
0
MCU ASE is not implemented.
1
MCU ASE is implemented
R
Preset
Required if MCU ASE is implemented
ISAOn- Exc
16
Reflects the Instruction Set Architecture used after vec- toring to an exception. Affects all exceptions whose off- sets are relative to EBase.
Encoding
Meaning
0
MIPS32is used on entrance to an exception vector.
1
microMIPS is used on entrance to an exception vector.
RW
Undefined
Required if microMIPS is implemented
ISA
15:14
Indicates Instruction Set Availability.
Encoding
Meaning
0
Only MIPS32 Instruction Set is imple- mented.
1
Only microMIPS32 is implemented.
2
Both MIPS32and microMIPS32 ISAs are implemented. MIPS32 ISA used when coming out of reset.
3
Both MIPS32and microMIPS32 ISAs are implemented. microMIPS32 ISA used when coming out of reset.
R
Preset
Required if microMIPS is implemented
ULRI
13
UserLocal register implemented. This bit indicates whether the UserLocal coprocessor 0 register is imple- mented.
Encoding
Meaning
0
UserLocal register is not imple- mented
1
UserLocal register is implemented
R
Preset
Required
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Table 9.40 Config3 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
RXI
12
Indicates whether the RIE and XIE bits exist within the PageGrain register.
Encoding
Meaning
0
The RIE and XIE bits are not implemented within the PageGrain register.
1
The RIE and XIE bits are implemented within the PageGrain register.
R
Preset
Required
DSP2P
11
MIPS® DSP ASE Revision 2 implemented. This bit indicates whether Revision 2 of the MIPS DSP ASE is implemented.
Encoding
Meaning
0
Revision 2 of the MIPS DSP ASE is not implemented
1
Revision 2 of the MIPS DSP ASE is implemented
R
Preset
Required
DSPP
10
MIPS® DSP ASE implemented. This bit indicates whether the MIPS DSP ASE is implemented.
Encoding
Meaning
0
MIPS DSP ASE is not implemented
1
MIPS DSP ASE is implemented
R
Preset
Required
CTXTC
9
ContextConfig registers is implemented and the width of the BadVPN2 field within the Config register register depends on the contents of the ContextConfig register.
Encoding
Meaning
0
ContextConfig is not implemented.
1
ContextConfig is implemented and is used for the ConfigBadVPN2 field.
R
Preset
Required
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Table 9.40 Config3 Register Field Descriptions
9.33 Configuration Register 3 (CP0 Register 16, Select 3)
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
ITL
8
MIPS® IFlowTraceTM mechanism implemented. This bit indicates whether the MIPS IFlowTrace is imple- mented.
Encoding
Meaning
0
MIPS IFlowTrace is not implemented
1
MIPS IFlowTrace is implemented
R
Preset
Required (Release 2.1 Only)
LPA
7
Denotes the presence of support for large physical addresses on MIPS64 processors. Not used by MIPS32 processors and returns zero on read.
For implementations of Release 1 of the Architecture, this bit returns zero on read.
R
Preset
Required (Release 2 Only)
VEIC
6
Support for an external interrupt controller is imple- mented.
For implementations of Release 1 of the Architecture, this bit returns zero on read.
This bit indicates not only that the processor contains support for an external interrupt controller, but that such a controller is attached.
Encoding
Meaning
0
Support for EIC interrupt mode is not implemented
1
Support for EIC interrupt mode is implemented
R
Preset
Required (Release 2 Only)
VInt
5
Vectored interrupts implemented. This bit indicates whether vectored interrupts are implemented.
For implementations of Release 1 of the Architecture, this bit returns zero on read.
Encoding
Meaning
0
Vector interrupts are not implemented
1
Vectored interrupts are implemented
R
Preset
Required (Release 2 Only)
SP
4
Small (1KByte) page support is implemented, and the PageGrain register exists
For implementations of Release 1 of the Architecture, this bit returns zero on read.
Encoding
Meaning
0
Small page support is not imple- mented
1
Small page support is implemented
R
Preset
Required (Release 2 Only)
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Table 9.40 Config3 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Complianc e
Name
Bits
CDMM
3
Common Device Memory Map implemented. This bit indicates whether the CDMM is implemented.
Encoding
Meaning
0
CDMM is not implemented
1
CDMM is implemented
R
Preset
Required
MT
2
MIPS® MT ASE implemented. This bit indicates whether the MIPS MT ASE is implemented.
Encoding
Meaning
0
MIPS MT ASE is not implemented
1
MIPS MT ASE is implemented
R
Preset
Required
SM
1
SmartMIPSTM ASE implemented. This bit indicates whether the SmartMIPS ASE is implemented.
Encoding
Meaning
0
SmartMIPS ASE is not implemented
1
SmartMIPS ASE is implemented
R
Preset
Required
TL
0
Trace Logic implemented. This bit indicates whether PC or data trace is implemented.
Encoding
Meaning
0
Trace logic is not implemented
1
Trace logic is implemented
R
Preset
Required
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9.34 Configuration Register 4 (CP0 Register 16, Select 4)
31
Compliance Level: Required if any optional feature described by this register is implemented: Release 2 of the Architecture; Optional otherwise.
The Config4 register encodes additional capabilities.
The number of page-pair entries within the FTLB = decode(FTLBSets) * decode(FTLBWays).
Figure 9-32 shows the format of the Config4 register; Table 9.41 describes the Config4 register fields.
Figure 9-32 Config4 Register Format
24 23 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
If MMUExtDef=2
If MMUExtDef=1 If MMUExtDef=0, 3
Table 9.41 Config4 Register Field Descriptions
9.34 Configuration Register 4 (CP0 Register 16, Select 4)
M
0000000
KScrExist
MMU Ext Def
Definition Depends on MMUExtDef
000
000000
FTLB PageSize
FTLBWays
MMUSizeExt
FTLBSets
00000000000000
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
M
31
This bit is reserved to indicate that a Config5 register is present. With the current architectural definition, this bit should always read as a 0.
R
Preset
Required
0
30:24
Must be written as zeros; returns zeros on read
R
0
Reserved
KScr Exist
23:16
Indicates how many scratch registers are available to kernel-mode software within COP0 Register 31.
Each bit represents a select for Coproecessor0 Register 31. Bit 16 represents Select 0, Bit 23 represents Select 7. If the bit is set, the associated scratch register is imple- mented and available for kernel-mode software.
Scratch registers meant for other purposes are not repre- sented in this field. For example, if EJTAG is imple- mented, Bit 16 is preset to zero eventhough DESAVE register is implemented at Select 0. Select 1 is reserved for future debug purposes and should not be used as a kernel scratch register, so bit 17 is preset to zero.
R
Preset
Required if Kernel Scratch Reg- isters are available
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Table 9.41 Config4 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
MMU Ext Def
15:14
MMU Extension Definition.
Defines how Config4[13:0] is to be interpreted.
Encoding
Meaning
1
Config4[7:0] used as MMUSizeExt.
2
Config4[3:0] used as FTLBSets. Config4[7:4] used as FTLBWays. Config4[10:8] used as FTLBPageSize.
0, 3
Reserved.
Config4[13:0] – Must be written as zeros, returns zeros on read.
R
Preset
Required
FTLB Page Size
10:8
Indicates the Page Size of the FTLB Array Entries.
Encoding
Page Size
0
1 KB
1
4 KB
2
16 KB
3
64KB
4
256 KB
5
1 GB
6
4 GB
7
Reserved
Implementations are allowed to implement any subset of these sizes, even a subset of only one pagesize. Software can detect if a FTLB page size is implemented by writ- ing the desired size into this register field. If the size is implemented, the register field is updated to the desired encoding. If the size is not implemented, the register field value is not changed.
The FTLB must be flushed of any valid entries before this register field value is changed by software. The FTLB behavior is UNDEFINED if there are valid FTLB entries which were not all programmed using a common page size.
RW if multiple FTLB page- sizes are implle- mented
R if only one FTLB page size is imple- mented.
Preset, chosen value is implemen- tation spe- cific
Required if MMUExt- Def=2
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Table 9.41 Config4 Register Field Descriptions
9.34 Configuration Register 4 (CP0 Register 16, Select 4)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
FTLB Ways
7:4
Indicates the Set Associativity of the FTLB Array.
Encoding
Associativity
0
2
1
3
2
4
3
5
4
6
5
7
6
8
7-15
Reserved
R
Preset
Required if MMUExt- Def=2
FTLB Sets
3:0
Indicates the number of Sets per Way within the FTLB Array.
Encoding
Sets per Way
0
1
1
2
2
4
3
8
4
16
5
32
6
64
7
128
8
256
9
512
10
1024
11
2048
12
4096
13
8192
14
16384
15
32768
R
Preset
Required if MMUExt- Def=2
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Table 9.41 Config4 Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
MMU Size Ext
7:0
If Config4MMUExt=1 then this field is an extension of Config1MMUSize-1 field.
This field is concatenated to the left of the most signifi- cant bit to the MMUSize-1 field to indicate the size of the TLB-1.
R
Preset
Required if MMUExt- Def=1
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9.35 Reserved for Implementations (CP0 Register 16, Selects 6 and 7)
9.35 Reserved for Implementations (CP0 Register 16, Selects 6 and 7)
Compliance Level: Implementation Dependent.
CP0 register 16, Selects 6 and 7 are reserved for implementation dependent use and is not defined by the architecture. In order to use CP0 register 16, Selects 6 and 7, it is not necessary to implement CP0 register 16, Selects 2 through 5 only to set the M bit in each of these registers. That is, if the Config2 and Config3 registers are not needed for the implementation, they need not be implemented just to provide the M bits.
The architecture only defines the use of the M bits for presence detection of Selects 1 to 5.
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9.36 Load Linked Address (CP0 Register 17, Select 0)
Compliance Level: Optional.
The LLAddr register contains relevant bits of the physical address read by the most recent Load Linked instruction. This register is implementation dependent and for diagnostic purposes only and serves no function during normal operation.
Figure 9-33 shows the format of the LLAddr register; Table 9.42 describes the LLAddr register fields.
Figure 9-33 LLAddr Register Format
31 0
Table 9.42 LLAddr Register Field Descriptions
PAddr
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
PAddr
31..0
This field encodes the physical address read by the most recent Load Linked instruction. The format of this regis- ter is implementation dependent, and an implementation may implement as many of the bits or format the address in any way that it finds convenient.
R
Undefined
Optional
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9.37 WatchLo Register (CP0 Register 18)
Compliance Level: Optional.
The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility which initiates a watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate some functions of the EJTAG debug solution. Watch exceptions are taken only if the EXL and ERL bits are zero in the Status register. If either bit is a one, the WP bit is set in the Cause register, and the watch exception is deferred until both the EXL and ERL bits are zero.
An implementation may provide zero or more pairs of WatchLo and WatchHi registers, referencing them via the select field of the MTC0/MFC0 instructions, and each pair of Watch registers may be dedicated to a particular type of reference (e.g., instruction or data). Software may determine if at least one pair of WatchLo and WatchHi registers are implemented via the WR bit of the Config1 register. See the discussion of the M bit in the WatchHi register description below.
The WatchLo register specifies the base virtual address and the type of reference (instruction fetch, load, store) to match. If a particular Watch register only supports a subset of the reference types, the unimplemented enables must be ignored on write and return zero on read. Software may determine which enables are supported by a particular Watch register pair by setting all three enables bits and reading them back to see which ones were actually set.
It is implementation dependent whether a data watch is triggered by a prefetch, CACHE, or SYNCI (Release 2 and subsequent releases only) instruction whose address matches the Watch register address match conditions.
Figure 9-34 shows the format of the WatchLo register; Table 9.43 describes the WatchLo register fields.
Figure 9-34 WatchLo Register Format
31 3210
Table 9.43 WatchLo Register Field Descriptions
9.37 WatchLo Register (CP0 Register 18)
VAddr
I
R
W
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
VAddr
31..3
This field specifies the virtual address to match. Note that this is a doubleword address, since bits [2:0] are used to control the type of match.
R/W
Undefined
Required
I
2
If this bit is one, watch exceptions are enabled for instruction fetches that match the address and are actu- ally issued by the processor (speculative instructions never cause Watch exceptions).
If this bit is not implemented, writes to it must be ignored, and reads must return zero.
R/W
0
Optional
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Table 9.43 WatchLo Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
R
1
If this bit is one, watch exceptions are enabled for loads that match the address.
For the purposes of the MIPS16e PC-relative load instructions, the PC-relative reference is considered to be a data, rather than an instruction reference. That is, the watchpoint is triggered only if this bit is a 1.
If this bit is not implemented, writes to it must be ignored, and reads must return zero.
R/W
0
Optional
W
0
If this bit is one, watch exceptions are enabled for stores that match the address.
If this bit is not implemented, writes to it must be ignored, and reads must return zero.
R/W
0
Optional
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9.38 WatchHi Register (CP0 Register 19)
Compliance Level: Optional.
The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility which initiates a watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate some functions of the EJTAG debug solution. Watch exceptions are taken only if the EXL and ERL bits are zero in the Status register. If either bit is a one, the WP bit is set in the Cause register, and the watch exception is deferred until both the EXL and ERL bits are zero.
An implementation may provide zero or more pairs of WatchLo and WatchHi registers, referencing them via the select field of the MTC0/MFC0 instructions, and each pair of Watch registers may be dedicated to a particular type of reference (e.g., instruction or data). Software may determine if at least one pair of WatchLo and WatchHi registers are implemented via the WR bit of the Config1 register. If the M bit is one in the WatchHi register reference with a select field of ‘n’, another WatchHi/WatchLo pair is implemented with a select field of ‘n+1’.
The WatchHi register contains information that qualifies the virtual address specified in the WatchLo register: an ASID, a G(lobal) bit, an optional address mask, and three bits (I, R, and W) which denote the condition that caused the watch register to match. If the G bit is one, any virtual address reference that matches the specified address will cause a watch exception. If the G bit is a zero, only those virtual address references for which the ASID value in the WatchHi register matches the ASID value in the EntryHi register cause a watch exception. The optional mask field provides address masking to qualify the address specified in WatchLo.
The I, R, and W bits are set by the processor when the corresponding watch register condition is satisfied and indicate which watch register pair (if more than one is implemented) and which condition matched. When set by the proces- sor, each of these bits remain set until cleared by software. All three bits are “write one to clear”, such that software must write a one to the bit in order to clear its value. The typical way to do this is to write the value read from the WatchHi register back to WatchHi. In doing so, only those bits which were set when the register was read are cleared when the register is written back.
Figure 9-35 shows the format of the WatchHi register; Table 9.44 describes the WatchHi register fields.
Figure 9-35 WatchHi Register Format
31 30 29 24 23 16 15 12 11 3 2 1 0
Table 9.44 WatchHi Register Field Descriptions
9.38 WatchHi Register (CP0 Register 19)
M
G
0
ASID
0
Mask
I
R
W
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
M
31
If this bit is one, another pair of WatchHi/WatchLo reg- isters is implemented at a MTC0 or MFC0 select field value of ‘n+1’
R
Preset
Required
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Table 9.44 WatchHi Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
G
30
If this bit is one, any address that matches that specified in the WatchLo register will cause a watch exception. If this bit is zero, the ASID field of the WatchHi register must match the ASID field of the EntryHi register to cause a watch exception.
R/W
Undefined
Required
ASID
23..16
ASID value which is required to match that in the EntryHi register if the G bit is zero in the WatchHi reg- ister.
R/W
Undefined
Required
Mask
11..3
Optional bit mask that qualifies the address in the WatchLo register. If this field is implemented, any bit in this field that is a one inhibits the corresponding address bit from participating in the address match.
If this field is not implemented, writes to it must be ignored, and reads must return zero.
Software may determine how many mask bits are imple- mented by writing ones the this field and then reading back the result.
R/W
Undefined
Optional
I
2
This bit is set by hardware when an instruction fetch condition matches the values in this watch register pair. When set, the bit remains set until cleared by software, which is accomplished by writing a 1 to the bit.
W1C
Undefined
Required (Release 2)
R
1
This bit is set by hardware when a load condition matches the values in this watch register pair. When set, the bit remains set until cleared by software, which is accomplished by writing a 1 to the bit.
W1C
Undefined
Required (Release 2)
W
0
This bit is set by hardware when a store condition matches the values in this watch register pair. When set, the bit remains set until cleared by software, which is accomplished by writing a 1 to the bit.
W1C
Undefined
Required (Release 2)
0
29..24, 15..12
Must be written as zero; returns zero on read.
0
0
Reserved
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9.39 Reserved for Implementations (CP0 Register 22, all Select values)
9.39 Reserved for Implementations (CP0 Register 22, all Select values)
Compliance Level: Implementation Dependent.
CP0 register 22 is reserved for implementation dependent use and is not defined by the architecture.
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9.40 Debug Register (CP0 Register 23, Select 0 )
Compliance Level: Optional.
The Debug register is part of the EJTAG specification. Refer to that specification for the format and description of
this register.
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9.40 Debug Register (CP0 Register 23, Select 0 )
177

9.41 Debug2 Register (CP0 Register 23, Select 6)
Compliance Level: Optional.
The Debug2 register is part of the EJTAG specification. Refer to that specification for the format and description of
this register.
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9.42 DEPC Register (CP0 Register 24)
Compliance Level: Optional.
The DEPC register is a read-write register that contains the address at which processing resumes after a debug excep- tion has been serviced. It is part of the EJTAG specification and the reader is referred there for the format and descrip- tion of the register. All bits of the DEPC register are significant and must be writable.
When a debug exception occurs, the processor writes the DEPC register with,
• the virtual address of the instruction that was the direct cause of the exception, or
• the virtual address of the immediately preceding branch or jump instruction, when the exception causing instruc- tion is in a branch delay slot, and the Branch Delay bit in the Cause register is set.
The processor reads the DEPC register as the result of execution of the DERET instruction.
Software may write the DEPC register to change the processor resume address and read the DEPC register to deter-
mine at what address the processor will resume.
9.42.1 Special Handling of the DEPC Register in Processors That Implement the MIPS16e ASE or microMIPS32 Base Architecture
In processors that implement the MIPS16e ASE or the microMIPS32 base architecture, the DEPC register requires special handling.
When the processor writes the DEPC register, it combines the address at which processing resumes with the value of the ISA Mode register:
DEPC ← resumePC31..1 || ISAMode0
“resumePC” is the address at which processing resumes, as described above.
When the processor reads the DEPC register, it distributes the bits to the PC and ISA Mode registers: PC ← DEPC31..1 || 0
ISAMode ← DEPC0
Software reads of the DEPC register simply return to a GPR the last value written with no interpretation. Software
writes to the DEPC register store a new value which is interpreted by the processor as described above.
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9.42 DEPC Register (CP0 Register 24)
179

9.43 Performance Counter Register (CP0 Register 25)
Compliance Level: Recommended.
The Architecture supports implementation dependent performance counters that provide the capability to count events or cycles for use in performance analysis. If performance counters are implemented, each performance counter consists of a pair of registers: a 32-bit control register and a 32-bit counter register. To provide additional capability, multiple performance counters may be implemented.
Performance counters can be configured to count implementation dependent events or cycles under a specified set of conditions that are determined by the control register for the performance counter. The counter register increments once for each enabled event. When the most significant bit of the counter register is a one (the counter overflows), the performance counter optionally requests an interrupt. In implementations of Release 1 of the Architecture, this inter- rupt is combined in a implementation-dependent way with hardware interrupt 5. In Release 2 of the Architecture, pending interrupts from all performance counters are ORed together to become the PCI bit in the Cause register, and are prioritized as appropriate to the interrupt mode of the processor. Counting continues after a counter register over- flow whether or not an interrupt is requested or taken.
Each performance counter is mapped into even-odd select values of the PerfCnt register: Even selects access the con- trol register and odd selects access the counter register. Table 9.45 shows an example of two performance counters and how they map into the select values of the PerfCnt register.
Table 9.45 Example Performance Counter Usage of the PerfCnt CP0 Register
Performance Counter
PerfCnt Register Select Value
PerfCnt Register Usage
0
PerfCnt, Select 0
Control Register 0
PerfCnt, Select 1
Counter Register 0
1
PerfCnt, Select 2
Control Register 1
PerfCnt, Select 3
Counter Register 1
More or less than two performance counters are also possible, extending the select field in the obvious way to obtain the desired number of performance counters. Software may determine if at least one pair of Performance Counter Control and Counter registers is implemented via the PC bit in the Config1 register. If the M bit is one in the Perfor- mance Counter Control register referenced via a select field of ‘n’, another pair of Performance Counter Control and Counter registers is implemented at the select values of ‘n+2’ and ‘n+3’.
The Control Register associated with each performance counter controls the behavior of the performance counter. Figure 9-36 shows the format of the Performance Counter Control Register; Table 9.46 describes the Performance Counter Control Register fields.
Figure 9-36 Performance Counter Control Register Format
31 30 29 25 24 16 15 14 11 10 5 4 3 2 1 0
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M
W
Impl
0
PC T D
EventExt
Event
IE
U
S
K
EXL
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Table 9.46 Performance Counter Control Register Field Descriptions
9.43 Performance Counter Register (CP0 Register 25)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
M
31
If this bit is a one, another pair of Performance Counter Control and Counter registers is implemented at a MTC0 or MFC0 select field value of ‘n+2’ and ‘n+3’.
R
Preset
Required
W
30
Denotes that the corresponding Counter register is 64 bits wide on a MIPS64/microMIPS64 processor. Unused on a MIPS32/microMIPS32 processor.
R
Preset
Required
Impl
29:25
This field is implementation dependent and is not speci- fied by the architecture.
If not used by the implementation, must be written as zero; returns zero on read.
Undefined
0 if not used by the implemen- tation
Optional
0
24..16
Must be written as zero; returns zero on read
0
0
Reserved
PCTD
15
Performance Counter Trace Disable.
The PDTrace facility (revision 6.00 and higher) has the ability to trace Performance Counter in its output. This bit is used to disable the specified performance counter from being traced when performance counter trace is enabled and a performance counter trace event is trig- gered.
Encoding
Meaning
0
Tracing is enabled for this counter.
1
Tracing is disabled for this counter.
RW
0
Required if PDTrace Perfor- mance Counter Tracing feature is implemented.
EventExt
14..11
In some implementations which support more than the the 64 encodings possible in the 6-bit Event field, the EventExt field acts as an extension to the Event field. In such instances the event selection is the concatentation of the two fields, i.e., EventExt|Event.
The actual field width is implementation dependent. Any bits that are not implemented read as zero and are ignored on write.
RW
Undefined
Optional
Event
10..5
Selects the event to be counted by the corresponding Counter Register. The list of events is implementation dependent, but typical events include cycles, instruc- tions, memory reference instructions, branch instruc- tions, cache and TLB misses, etc.
Implementations that support multiple performance counters allow ratios of events, e.g., cache miss ratios if cache miss and memory references are selected as the events in two counters
R/W
Undefined
Required
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Table 9.46 Performance Counter Control Register Field Descriptions
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
IE
4
Interrupt Enable. Enables the interrupt request when the corresponding counter overflows (the most significant bit of the counter is one. This is bit 31 for a 32-bit wide counter or bit 63 of a 64-bit wide counter, denoted by the W bit in this register).
Note that this bit simply enables the interrupt request. The actual interrupt is still gated by the normal interrupt masks and enable in the Status register.
Encoding
Meaning
0
Performance counter interrupt dis- abled
1
Performance counter interrupt enabled
R/W
0
Required
U
3
Enables event counting in User Mode. Refer to Section 3.4 “User Mode” on page 20 for the conditions under which the processor is operating in User Mode.
Encoding
Meaning
0
Disable event counting in User Mode
1
Enable event counting in User Mode
R/W
Undefined
Required
S
2
Enables event counting in Supervisor Mode (for those processors that implement Supervisor Mode). Refer to Section 3.3 “Supervisor Mode” on page 19 for the con- ditions under which the processor is operating in Super- visor mode.
If the processor does not implement Supervisor Mode, this bit must be ignored on write and return zero on read.
Encoding
Meaning
0
Disable event counting in Supervisor Mode
1
Enable event counting in Supervisor Mode
R/W
Undefined
Required
K
1
Enables event counting in Kernel Mode. Unlike the usual definition of Kernel Mode as described in Section 3.2 “Kernel Mode” on page 19, this bit enables event counting only when the EXL and ERL bits in the Status register are zero.
Encoding
Meaning
0
Disable event counting in Kernel Mode
1
Enable event counting in Kernel Mode
R/W
Undefined
Required
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Table 9.46 Performance Counter Control Register Field Descriptions
9.43 Performance Counter Register (CP0 Register 25)
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
EXL
0
Enables event counting when the EXL bit in the Status register is one and the ERL bit in the Status register is zero.
Counting is never enabled when the ERL bit in the Sta- tus register or the DM bit in the Debug register is one.
Encoding
Meaning
0
Disable event counting while EXL = 1, ERL = 0
1
Enable event counting while EXL = 1, ERL = 0
R/W
Undefined
Required
The Counter Register associated with each performance counter increments once for each enabled event. Figure 9-37 shows the format of the Performance Counter Counter Register; Table 9.47 describes the Performance Counter Counter Register fields.
Figure 9-37 Performance Counter Counter Register Format
31 0
Table 9.47 Performance Counter Counter Register Field Descriptions
Event Count
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
Event Count
31..0
Increments once for each event that is enabled by the corresponding Control Register. When the most signif- icant bit is one, a pending interrupt request is ORed with those from other performance counters and indi- cated by the PCI bit in the Cause register.
R/W
Undefined
Required
Programming Note:
In Release 2 of the Architecture, the EHB instruction can be used to make interrupt state changes visible when the IE field of the Control register or the Event Count Field of the Counter register are written. See sECTION 6.1.2.1 “Software Hazards and the Interrupt System” on page 54.
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9.44 ErrCtl Register (CP0 Register 26, Select 0)
Compliance Level: Optional.
The ErrCtl register provides an implementation dependent diagnostic interface with the error detection mechanisms implemented by the processor. This register has been used in previous implementations to read and write parity or ECC information to and from the primary or secondary cache data arrays in conjunction with specific encodings of the Cache instruction or other implementation-dependent method. The exact format of the ErrCtl register is imple- mentation dependent and not specified by the architecture. Refer to the processor specification for the format of this register and a description of the fields.
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9.45 CacheErr Register (CP0 Register 27, Select 0)
Compliance Level: Optional.
The CacheErr register provides an interface with the cache error detection logic that may be implemented by a pro-
cessor.
The exact format of the CacheErr register is implementation dependent and not specified by the architecture. Refer to the processor specification for the format of this register and a description of the fields.
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9.45 CacheErr Register (CP0 Register 27, Select 0)
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9.46 TagLo Register (CP0 Register 28, Select 0, 2)
Compliance Level: Required if a cache is implemented; Optional otherwise.
The TagLo and TagHi registers are read/write registers that act as the interface to the cache tag array. The Index Store Tag and Index Load Tag operations of the CACHE instruction use the TagLo and TagHi registers as the source or sink of tag information, respectively.
The exact format of the TagLo and TagHi registers is implementation dependent. Refer to the processor specification for the format of this register and a description of the fields.
However, software must be able to write zeros into the TagLo and TagHi registers and then use the Index Store Tag cache operation to initialize the cache tags to a valid state at powerup.
It is implementation dependent whether there is a single TagLo register that acts as the interface to all caches, or a dedicated TagLo register for each cache. If multiple TagLo registers are implemented, they occupy the even select values for this register encoding, with select 0 addressing the instruction cache and select 2 addressing the data cache. Whether individual TagLo registers are implemented or not for each cache, processors must accept a write of zero to select 0 and select 2 of TagLo as part of the software process of initializing the cache tags at powerup.
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9.47 DataLo Register (CP0 Register 28, Select 1, 3)
Compliance Level: Optional.
The DataLo and DataHi registers are registers that act as the interface to the cache data array and are intended for diagnostic operation only. The Index Load Tag operation of the CACHE instruction reads the corresponding data val- ues into the DataLo and DataHi registers.
The exact format and operation of the DataLo and DataHi registers is implementation dependent. Refer to the pro- cessor specification for the format of this register and a description of the fields.
It is implementation dependent whether there is a single DataLo register that acts as the interface to all caches, or a dedicated DataLo register for each cache. If multiple DataLo registers are implemented, they occupy the odd select values for this register encoding, with select 1 addressing the instruction cache and select 3 addressing the data cache.
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9.47 DataLo Register (CP0 Register 28, Select 1, 3)
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9.48 TagHi Register (CP0 Register 29, Select 0, 2)
Compliance Level: Required if a cache is implemented; Optional otherwise.
The TagLo and TagHi registers are read/write registers that act as the interface to the cache tag array. The Index Store Tag and Index Load Tag operations of the CACHE instruction use the TagLo and TagHi registers as the source or sink of tag information, respectively.
The exact format of the TagLo and TagHi registers is implementation dependent. Refer to the processor specification for the format of this register and a description of the fields. However, software must be able to write zeros into the TagLo and TagHi registers and the use the Index Store Tag cache operation to initialize the cache tags to a valid state at powerup.
It is implementation dependent whether there is a single TagHi register that acts as the interface to all caches, or a dedicated TagHi register for each cache. If multiple TagHi registers are implemented, they occupy the even select val- ues for this register encoding, with select 0 addressing the instruction cache and select 2 addressing the data cache. Whether individual TagHi registers are implemented or not for each cache, processors must accept a write of zero to select 0 and select 2 of TagHi as part of the software process of initializing the cache tags at powerup.
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9.49 DataHi Register (CP0 Register 29, Select 1, 3)
Compliance Level: Optional.
The DataLo and DataHi registers are registers that act as the interface to the cache data array and are intended for diagnostic operation only. The Index Load Tag operation of the CACHE instruction reads the corresponding data val- ues into the DataLo and DataHi registers.
The exact format and operation of the DataLo and DataHi registers is implementation dependent. Refer to the pro- cessor specification for the format of this register and a description of the fields.
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9.49 DataHi Register (CP0 Register 29, Select 1, 3)
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9.50 ErrorEPC (CP0 Register 30, Select 0)
Compliance Level: Required.
The ErrorEPC register is a read-write register, similar to the EPC register, at which processing resumes after a Reset, Soft Reset, Nonmaskable Interrupt (NMI) or Cache Error exceptions (collectively referred to as error exceptions). Unlike the EPC register, there is no corresponding branch delay slot indication for the ErrorEPC register. All bits of the ErrorEPC register are significant and must be writable.
When an error exception occurs, the processor writes the ErrorEPC register with:
• the virtual address of the instruction that was the direct cause of the exception, or
• the virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot.
The processor reads the ErrorEPC register as the result of execution of the ERET instruction.
Software may write the ErrorEPC register to change the processor resume address and read the ErrorEPC register to
determine at what address the processor will resume
Figure 9-38 shows the format of the ErrorEPC register; Table 9.48 describes the ErrorEPC register fields.
Figure 9-38 ErrorEPC Register Format
31 0
Table 9.48 ErrorEPC Register Field Descriptions
9.50.1 Special Handling of the ErrorEPC Register in Processors That Implement the MIPS16e ASE or microMIPS32 Base Architecture
In processors that implement the MIPS16e ASE or microMIPS32 base architecture, the ErrorEPC register requires special handling.
When the processor writes the ErrorEPC register, it combines the address at which processing resumes with the value of the ISA Mode register:
ErrorEPC ← resumePC31..1 || ISAMode0
“resumePC” is the address at which processing resumes, as described above.
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ErrorEPC
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
ErrorEPC
31..0
Error Exception Program Counter
R/W
Undefined
Required
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When the processor reads the ErrorEPC register, it distributes the bits to the PC and ISAMode registers: PC ← ErrorEPC31..1 || 0
ISAMode ← ErrorEPC0
Software reads of the ErrorEPC register simply return to a GPR the last value written with no interpretation. Soft-
ware writes to the ErrorEPC register store a new value which is interpreted by the processor as described above.
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9.50 ErrorEPC (CP0 Register 30, Select 0)
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9.51 DESAVE Register (CP0 Register 31)
Compliance Level: Optional.
The DESAVE register is part of the EJTAG specification. Refer to that specification for the format and description of
this register.
The DESAVE register is meant to be used solely while in Debug Mode. If kernel mode software uses this register, it would conflict with debugging kernel mode software. For that reason, it is strongly recommended that kernel mode software not use this register. If the KScratch* registers are implemented, kernel software can use those registers.
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9.51 DESAVE Register (CP0 Register 31)
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9.52 KScratchn Registers (CP0 Register 31, Selects 2 to 7) Compliance Level: Optional, KScratch1 and KScratch2 at selects 2, 3 are recommended.
The KScratchn registers are read/write registers available for scratch pad storage by kernel mode software. These registers are 32bits in width for 32-bit processors and 64bits for 64-bit processors.
The existence of these registers is indicated by the KScrExist field within the Config4 register. The KScrExist field specifies which of the selects are populated with a kernel scratch register.
Debug Mode software should not use these registers, instead debug software should use the DESAVE register. If EJTAG is implemented, select 0 should not be used for a KScratch register. Select 1 is being reserved for future debug use and should not be used for a KScratch register.
Figure 9-39 KScratchn Register Format
31 0
Table 9.49 KScratchn Register Field Descriptions
Data
Fields
Description
Read / Write
Reset State
Compliance
Name
Bits
Data
31:0
Scratch pad data saved by kernel software.
R/W
Undefined
Optional
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Appendix A
Alternative MMU Organizations
The main body of this specification describes the TLB-based MMU organization. This appendix describes other potential MMU organizations.
A.1 Fixed Mapping MMU
As an alternative to the full TLB-based MMU, the MIPS32/microMIPS32 Architecture supports a lightweight mem- ory management mechanism with fixed virtual-to-physical address translation, and no memory protection beyond what is provided by the address error checks required of all MMUs. This may be useful for those applications which do not require the capabilities of a full TLB-based MMU.
A.1.1 Fixed Address Translation
Address translation using the Fixed Mapping MMU is done as follows:
• Kseg0 and Kseg1 addresses are translated in an identical manner to the TLB-based MMU: they both map to the low 512MB of physical memory.
• Useg/Suseg/Kuseg addresses are mapped by adding 1GB to the virtual address when the ERL bit is zero in the Status register, and are mapped using an identity mapping when the ERL bit is one in the Status register.
• Sseg/Ksseg/Kseg2/Kseg3 addresses are mapped using an identity mapping. Supervisor Mode is not supported with a Fixed Mapping MMU.
Table A.1 lists all mappings from virtual to physical addresses. Note that address error checking is still done before the translation process. Therefore, an attempt to reference kseg0 from User Mode still results in an address error exception, just as it does with a TLB-based MMU.
Table A.1 Physical Address Generation from Virtual Addresses
Segment Name
Virtual Address
Generates Physical Address
StatusERL = 0
StatusERL = 1
useg suseg kuseg
0x0000 0000
through
0x7FFF FFFF
0x4000 0000
through
0xBFFF FFFF
0x0000 0000
through
0x7FFF FFFF
kseg0
0x8000 0000
through
0x9FFF FFFF
0x0000 0000
through
0x1FFF FFFF
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Alternative MMU Organizations
Table A.1 Physical Address Generation from Virtual Addresses (Continued)
Segment Name
Virtual Address
Generates Physical Address
StatusERL = 0
StatusERL = 1
kseg1
0xA000 0000
through
0xBFFF FFFF
0x0000 0000
through
0x0x1FFF FFFF
sseg ksseg kseg2
0xC000 0000
through
0xDFFF FFFF
0xC000 0000
through
0xDFFF FFFF
kseg3
0xE000 0000
through
0xFFFF FFFF
0xE000 0000
through
0xFFFF FFFF
Note that this mapping means that physical addresses 0x2000 0000 through 0x3FFF FFFF are inaccessible when the ERL bit is off in the Status register, and physical addresses 0x8000 0000 through 0xBFFF FFFF are inaccessible when the ERL bit is on in the Status register.
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Figure A-1 shows the memory mapping when the ERL bit in the Status register is zero; Figure A-2 shows the mem- ory mapping when the ERL bit is one.
A.1 Fixed Mapping MMU
kseg3
kseg2
ksseg
sseg
kseg1
kseg0
kuseg
suseg
useg
kseg3 Mapped
kseg2
ksseg sseg Mapped
kuseg suseg useg Mapped
Unmapped
kseg0
kseg1
Mapped
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
0xC000 0000 0xBFFF FFFF
0xA000 0000 0x9FFF FFFF
0x8000 0000 0x7FFF FFFF
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
0xC000 0000 0xBFFF FFFF
Figure A-1 Memory Mapping when ERL = 0
0x0000 0000
0x4000 0000 0x3FFF FFFF
0x2000 0000 0x1FFF FFFF
0x0000 0000
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Alternative MMU Organizations
Figure A-2 Memory Mapping when ERL = 1
kseg3
kseg2
ksseg
sseg
kseg1
kseg0
kuseg
suseg
useg
kseg3 Mapped
kseg2
ksseg sseg Mapped
Unmapped
kuseg suseg useg Mapped
kseg0
kseg1
Mapped
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
0xC000 0000 0xBFFF FFFF
0xA000 0000 0x9FFF FFFF
0x8000 0000 0x7FFF FFFF
0xFFFF FFFF
0xE000 0000 0xDFFF FFFF
0xC000 0000 0xBFFF FFFF
0x8000 0000 0x7FFF FFFF
0x0000 0000
A.1.2 Cacheability Attributes
0x0000 0000
Because the TLB provided the cacheability attributes for the kuseg, kseg2, and kseg3 segments, some mechanism is required to replace this capability when the fixed mapping MMU is used. Two additional fields are added to the Config register whose encoding is identical to that of the K0 field. These additions are the K23 and KU fields which control the cacheability of the kseg2/kseg3 and the kuseg segments, respectively. Note that when the ERL bit is on in the Status register, kuseg data references are always treated as uncacheable references, independent of the value of the KU field. The operation of the processor is UNDEFINED if the ERL bit is set while the processor is executing instructions from kuseg.
The cacheability attributes for kseg0 and kseg1 are provided in the same manner as for a TLB-based MMU: the cacheability attribute for kseg0 comes from the K0 field of Config, and references to kseg1 are always uncached.
Figure A-3 shows the format of the additions to the Config register; Table A.2 describes the new Config register fields.
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Figure A-3 Config Register Additions
31 30 28 27 25 24 16 15 14 13 12 10 9 7 6 4 3 2 0
Table A.2 Config Register Field Descriptions
A.2 Block Address Translation
M
K23
KU
0
BE
AT
AR
MT
0
VI
K0
Fields
Description
Read/ Write
Reset State
Compliance
Name
Bits
K23
30:28
Kseg2/Kseg3 cacheability and coherency attribute. See Table 9.9 on page 98 for the encoding of this field.
R/W
Undefined
Required
KU
27:25
Kuseg cacheability and coherency attribute when Sta- tusERL is zero. See Table 9.9 on page 98 for the encod- ing of this field.
R/W
Undefined
Required
A.1.3 Changes to the CP0 Register Interface
Relative to the TLB-based address translation mechanism, the following changes are necessary to the CP0 register interface:
• The Index, Random, EntryLo0, EntryLo1, Context, PageMask, Wired, and EntryHi registers are no longer required and may be removed. The effects of a read or write to these registers are UNDEFINED.
• The TLBWR, TLBWI, TLBP, and TLBR instructions are no longer required and must cause a Reserved Instruc- tion Exception.
A.2 Block Address Translation
This section describes the architecture for a block address translation (BAT) mechanism that reuses much of the hard- ware and software interface that exists for a TLB-Based virtual address translation mechanism. This mechanism has the following features:
• It preserves as much as possible of the TLB-Based interface, both in hardware and software.
• It provides independent base-and-bounds checking and relocation for instruction references and data references.
• It provides optional support for base-and-bounds relocation of kseg2 and kseg3 virtual address regions.
A.2.1 BAT Organization
The BAT is an indexed structure which is used to translate virtual addresses. It contains pairs of instruction/data entries which provide the base-and-bounds checking and relocation for instruction references and data references, respectively. Each entry contains a page-aligned bounds virtual page number, a base page frame number (whose
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Alternative MMU Organizations
width is implementation dependent), a cache coherence field (C), a dirty (D) bit, and a valid (V) bit. Figure A-4 shows the logical arrangement of a BAT entry.
Figure A-4 Contents of a BAT Entry
The BAT is indexed by the reference type and the address region to be checked as shown in Table A.3. Table A.3 BAT Entry Assignments
BoundsVPN
BasePFN
C
D
V
Entry Index
Reference Type
Address Region
0
Instruction
useg/kuseg
1
Data
2
Instruction
kseg2
(or kseg2 and kseg3)
3
Data
4
Instruction
kseg3
5
Data
Entries 0 and 1 are required. Entries 2, 3, 4 and 5 are optional and may be implemented as necessary to address the needs of the particular implementation. If entries for kseg2 and kseg3 are not implemented, it is implementa- tion-dependent how, if at all, these address regions are translated. One alternative is to combine the mapping for kseg2 and kseg3 into a single pair of instruction/data entries. Software may determine how many BAT entries are imple- mented by looking at the MMU Size field of the Config1 register.
A.2.2 Address Translation
When a virtual address translation is requested, the BAT entry that is appropriate to the reference type and address region is read. If the virtual address is greater than the selected bounds address, or if the valid bit is off in the entry, a TLB Invalid exception of the appropriate reference type is initiated. If the reference is a store and the D bit is off in the entry, a TLB Modified exception is initiated. Otherwise, the base PFN from the selected entry, shifted to align with bit 12, is added to the virtual address to form the physical address. The BAT process can be described as follows:
i ← SelectIndex (reftype, va) bounds ← BAT[i]BoundsVPN || 112 pfn ← BAT[i]BasePFN
c ← BAT[i]C
d ← BAT[i]D
v ← BAT[i]V
if (va > bounds) or (v = 0) then
InitiateTLBInvalidException(reftype)
endif
if (d = 0) and (reftype = store) then
InitiateTLBModifiedException()
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endif
pa ← va + (pfn || 012)
Making all addresses out-of-bounds can only be done by clearing the valid bit in the BAT entry. Setting the bounds value to zero leaves the first virtual page mapped.
A.2.3 Changes to the CP0 Register Interface
Relative to the TLB-based address translation mechanism, the following changes are necessary to the CP0 register interface:
• The Index register is used to index the BAT entry to be read or written by the TLBWI and TLBR instructions.
• The EntryHi register is the interface to the BoundsVPN field in the BAT entry.
• The EntryLo0 register is the interface to the BasePFN and C, D, and V fields of the BAT entry. The register has the same format as for a TLB-based MMU.
• The Random, EntryLo1, Context, PageMask, and Wired registers are eliminated. The effects of a read or write to these registers is UNDEFINED.
• The TLBP and TLBWR instructions are unnecessary. The TLBWI and TLBR instructions reference the BAT entry whose index is contained in the Index register. The effects of executing a TLBP or TLBWR are UNDE- FINED, but processors should signal a Reserved Instruction Exception.
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A.2 Block Address Translation
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Alternative MMU Organizations
A.3 Dual Variable-Page-Size and Fixed-Page-Size TLBs
Most MIPS CPU cores implement a fully associative Joint TLB. Unfortunately, such fully-associative structures can be slow, can require a large amount of logic components to implement and can dissipate a lot of power. The number of entries for a fully associative array that can be practically implemented is not large.
In high performance systems, it is desirable to minimize the frequency of TLB misses. In small and low-cost systems, it is desirable to keep the implementation costs of a TLB to a minimum. This section describes an optional alternative MMU configuration which decreases the implementation costs of a small TLB as well as allows for a TLB that can map a very large number of pages to be reasonably implemented.
A.3.1 MMU Organization
This alternative MMU configuration uses two TLB structures.
1. This first TLB is called the Fixed-Page-Size TLB or the FTLB.
• At any one time, all entries within the FTLB use a shared, common page size.
• The FTLB is not fully-associative, but rather set associative.
• The number of ways per set is implementation specific.
• The number of sets is implementation specific.
• The common page size is also implementation specific.
• The common page size is allowed to be software configurable. The choice of the common page size is done once for the entire FTLB, not on a per-entry basis. This configuration by software can only be done after a full flush/initialization of the FTLB, before there are any valid entries within the FTLB. Implementations are also allowed to support only one page size for the FTLB – in that case, the FTLB page size is fixed by hard- ware and not software configurable.
2. The
second TLB is called the Variable-Page-Size TLB or the VTLB.
• The choice of page size is done on a per-entry basis. That is, one VTLB entry can use a pagesize that is dif- ferent from the size used by another VTLB entry.
• The VTLB is fully-associative.
• The number of entries is implementation specific.
• The set of allowable page sizes for VTLB entries is implementation specific.
Just as for the JTLB, both the FTLB and VTLB are shared between the instruction stream and the data stream. For address translation, the virtual address is presented to both the FTLB and VTLB in parallel. Entries in both structures are accessed in parallel to search for the physical address.
The use of two TLB structures has these benefits:
• The implementation costs of building a set-associative TLB with many entries can be much less than that of implementing a large fully-associative TLB.
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• The existence of a VTLB retains the capability of using large pages to map large sections of physical memory without consuming a large number of entries in the FTLB.
Random replacement of pages in the MMU happens mainly in the FTLB. In most operating systems, on-demand pag- ing only uses one page size so the FTLB is sufficient for this purpose. Some of the address bits of the specified virtual address are used to index into the FTLB as appropriate for the chosen FTLB array size. The method of choosing which FTLB way to modify is implementation specific.
The VTLB is very similiar to the JTLB. The C0_PageMask register is used to program the page size used for a par- ticular VTLB entry.
The configuration of the FTLB is reflected in the FTLB fields within the new C0_Config4 register. The size of the VTLB is reflected in the C0_Config1MMUSize-1 field. The presense of the dual FTLB and VTLB is denoted by the value of 0x4 in C0_ConfigMT register field. These registers are described in “Changes to the COP0 Registers” on page 206.
Most implementations would choose to build a VTLB with a smaller number of entries and a FTLB with a larger number of entries. This combination allows for many on-demand fixed-sized pages as well as for a small number of large address blocks to be simultaneously mapped by the MMU.
A.3.2 Programming Interface
The software programming interface used for the fully-associative JTLB is maintained as much as possible to decrease the amount of software porting.
Also for that purpose, each entry in the FTLB as well as the VTLB use one tag (VPN2) to map two physical pages (PFN), just as in the JTLB. The entries in either array are accessed through the C0_EntryHi and C0_EntryLo0/1 registers.
Entries in either array (FTLB or VTLB) can be accessed with the TLBWI and TLBWR instructions.
The PageMask register is used to set the page size for the VTLB entries. This register is also used to choose which array (FTLB or VTLB) to write for the TLBWR instruction.
For the rest of this section, the following parameters are used:
3. FPageSize – the page size used by the FTLB entries
4. FSetSize – Number of entries in one way of the FTLB.
5. FWays – Number of ways within a set of the FTLB.
6. VIndex – Number of entries in the VTLB.
For the C0_Index , the C0_Wired registers, the TLBP, TLBR and TLBWI instructions; the VTLB occupies indices 0 to VIndex-1. The FTLB occupies indices VIndex to VIndex + (FSetSize * FWays)-1.
The TLBP instruction produces a value which can be used by the TLBWI instruction without modification by soft- ware. When referring to the FTLB, the value is the concatentation of the selected FTLB way and set, and incremented by the size of the VTLB. For example, {selected FTLB Way, selected FTLB Set} + VIndex.
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If C0_PageMask is set to the page size used by the FTLB, the TLBWR instruction modifies entries within the FTLB.
How the FTLB set-associative array is indexed is implementation specific. In any indexing scheme, the least signifi- cant address bit that can be used for indexing is log2(FPageSize)+1. The number of index bits needed to select the correct set within the FTLB array is log2(FSetSize).
Since the FTLB array can be modified through the TLBWI instruction, it is possible for software to choose an inap- propriate FTLB index value for the specified virtual address. In this case, it is implementation specific whether a Machine Check exception is generated for the TLBWI instruction.
The method of choosing which FTLB way to modify is implementation specific.
If C0_PageMask is not set to the pagesize used by the FTLB, the TLBWR instruction modifies entries within the VTLB. The VTLB entry to be written is specified by the log2(VIndex) least significant bits of the C0_Random reg- ister value.
For both the TLBWR and TLBWI instruction, it is implementation specific whether both (FTLB and VTLB) arrays are checked for duplicate or overlapping entries and whether a Machine Check exception is generated for these cases.
A.3.2.1 Example with chosen FTLB and VTLB sizes
As an example, let’s assume an implementation chooses these values:
1. FPageSize – 4KB used by the FTLB entries
2. FSetSize – 128 in one way of the FTLB.
3. FWays – 4 ways within a set of the FTLB. (The FTLB has (128 sets x 4 ways/set) 512 entries, capable of map- ping (512 entries x 2 pages/entry x 4KB/page) 4MB of address space simultaneously.
4. VIndex – 8 entries in the VTLB.
For the C0_Index, the C0_Wired registers, the TLBP, TLBR and TLBWI instructions; the VTLB occupies indices 0 to 7. The FTLB occupies indices 8 to 519.
The FTLB entries have a VPN2 field which starts at virtual address bit 12.
The least significant virtual address bit that can be used for FTLB indexing is virtual address 13. To index the FTLB set-associative array, 7 index bits are needed.
In this simple example, the design uses contiguous virtual address bits directly for indexing the FTLB ( it does not create a hash for the FTLB indexing). The FTLB set-associative array is indexed using virtual address bits 19:13. The TLBWR instruction uses these address bits held in C0_EntryHi.
In this simple example, the design uses a cycle counter of 2 bits for way selection within the FTLB. The Random register field within C0_Random is 3 bits wide to select the entry within the VTLB.
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A.3.3 Changes to the TLB Instructions
TLBP
Both the VTLB and the FTLB are probed in parallel for the specified virtual address.
If the address hits in the VTLB, C0_Index specifies the entry within the VTLB [ a value within 0 to VIndex-1].
If the address hits in the FTLB, C0_Index specifies the entry within the FTLB [ a value within VIndex to VIn- dex+(FSetSize * FWays)-1 ]. Which bits are used to encode the selected FTLB set as opposed to which bits are used to encode the selected FTLB way is implementation specific, but must match what is expected by the TLBWI instruction implementation. C0_PageMask reflects the pagesize used by the FTLB.
TLBR
Either a VTLB entry or a FTLB entry is read depending on the specified index in C0_Index.
Index values of 0 to VIndex-1 access the VTLB. Index values VIndex to VIndex+(FSetSize * FWays)-1 access
the FTLB.
TLBWI
Either the VTLB or FTLB entry is written depending on the specified index in C0_Index.
Index values of 0 to VIndex-1 access the VTLB. Index values VIndex to VIndex+(FSetSize * FWays)-1 access
the FTLB.
It is implementation specific if the hardware checks the VPN2 field of C0_EntryHi is appropriate for the speci- fied set within the FTLB. The implementation may generate a machine-check exception if the VPN2 field is not appropriate for the specified set.
It is implementation specific if the hardware checks both arrays (FTLB and VTLB) for valid duplicate or over- lapping entries and if the hardware signals a Machine Check exception for these cases.
TLBWR
Either the VTLB or FTLB entry is written depending on the specified pagesize in C0_PageMask.
If C0_PageMask is set to any pagesize other than that used by the FTLB, the TLBWR instruction modifies a
VTLB entry. The VTLB entry is specified by the Random register field within C0_Random.
If C0_PageMask is set to the pagesize used by the FTLB, the TLBWR modifies a FTLB entry. The FTLB
set-associative array is indexed in an implementation-specific manner.
The method of selecting which FTLB way to modify is implementation specific.
It is implementation specific if the hardware checks both arrays (FTLB and VTLB) for valid duplicate or over- lapping entries and if the hardware signals a Machine Check exception for these cases.
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A.3.4 Changes to the COP0 Registers
C0_Config4 (CP0 Register 16, Select 4)
A new register introduced to reflect the FTLB configuration. Config4MMUExtDef register field must be set to a value of 2 to reflect that the Dual VTLB and FTLB configuration is implemented. If either Config4 is not imple- mented or the Config4MMUExtDef field is not fixed to 2, the Dual VTLB/FTLB configuration is not implemented.
If Config4MMUExtDef is fixed to a value of 2, the FTLBPageSize, FTLBWays and FTLBSets fields reflect the FTLB configuration. Please refer to “Configuration Register 4 (CP0 Register 16, Select 4)” on page 165 for more detail on this register.
C0_Config1 (CP0 Register 16, Select 1)
If Config4MMUExtDef is fixed to a value of 2, the MMUSize-1 register field is redefined to reflect only the size of the VTLB.
C0_Config (CP0 Register 16, Select 0)
If Config4MT is fixed to a value of 4, the implemented MMU Type is the dual FTLB and VTLB configuration. C0_Index (CP0 Register 0, Select 0)
If Config4MMUExtDef is fixed to a value of 2, the register is redefined in this way:
The value held in the Index field can refer to either an entry in the FTLB or the VTLB. Index values of 0 to VIndex-1 access the VTLB. Index values VIndex to VIndex+(FSetSize * FWays)-1 access the FTLB. Which bits in the register field which encode the FTLB set as opposed to which bits encode the FTLB way is imple- mentation specific, but must match what is expected by the TLBWI instruction implementation.
C0_Random (CP0 Register 1, Select 0)
If Config4MMUExtDef is fixed to a value of 2, the register is redefined in this way:
If the value in C0_PageMask is not set to the page-size used by the FTLB, and a TLBWR instruction is executed, a VTLB entry is modified. The Random register field is used to select the VTLB entry which is modified.
If the value in C0_PageMask is set to the page-size used by the FTLB, and a TLBWR instruction is exe- cuted, a FTLB entry is modified. It is implementation specific whether the C0_RANDOM register is used to select the FTLB entry.
The upper bound of the Random register field value is VIndex.
C0_Wired (CP0 Register 6, Select 0)
If Config4MMUExtDef is fixed to a value of 2, the Wired register field can only hold a value of VIndex-1 or less. That is, only VTLB entries can be wired down.
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C0_PageMask (CP0 Register 5, Select 0)
A.3 Dual Variable-Page-Size and Fixed-Page-Size TLBs
If Config4MMUExtDef is fixed to a value of 2, the register is redefined in this way:
The Mask and MaskX field values determine whether the VTLB or the FTLB is modified by a TLBWR
instruction.
The Mask and MaskX register fields do not affect the TLB address match operation for FTLB entries. The
pagesize used by the FTLB entries are specified by the Config4FPageSize register field.
The software writeable bits in the Mask and MaskX fields reflect what page sizes are available in the VTLB.
These fields do not reflect the page sizes which are available in the FTLB.
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A.3.5 Software Compatibility
One of the main software visible changes introducted by this alternative MMU are the values reported in the C0_Index register. Previously, it was just a simple linear index. For this alternative MMU configuration, the value reflects both a selected way as well as a selected set when a FTLB entry is specified.
Fortunately, this Index value isn’t frequently generated by software nor read by software. Instead, the contents of the C0_Index register is generated by hardware upon a TLBP instruction. Software then just issues the TLBWI instruc- tion once the C0_EnLo* registers have been appropriately modified.
Another software visible change is that the MMUSize-1 field no longer reports the entire MMU size. For TLB initial- ization and TLB flushing, the contents of Config1MMUSize-1, Config4FTLBWays and Config4FTLBSets register fields must all be read to calculate the entire number of TLB entries that must be initialized. TLB initialization and flushing are the only times software needs to generate an Index value to write into the C0_Index register.
Only the VTLB entries may be wired down. This limitation is due to using some of the EntryHi VPN2 bits to index the FTLB array.
If a page using the FTLB page-size is to be wired down, that page must be programmed into the VTLB using the TLBWI instruction, as the TLBWR instruction would only access the FTLB in that situation and could not access any wired-down TLB entry. The TLBWI instruction is normally used for wired-down pages, so this restriction should not affect existing software.
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Appendix B
Revision History
In the left hand page margins of this document you may find vertical change bars to note the location of significant changes to this document since its last release. Significant changes are defined as those which you should take note of as you use the MIPS IP. Changes to correct grammar, spelling errors or similar may or may not be noted with change bars. Change bars will be removed for changes which are more than one revision old.
Please note: Limitations on the authoring tools make it difficult to place change bars on changes to figures. Change bars on figure titles are used to denote a potential change in the figure itself.
Revision
0.92 0.95 1.00
Date
January 20, 2001 March 12, 2001 August 29, 2002
Description
Internal review copy of reorganized and updated architecture documentation. Clean up document for external review release
Update based on review feedback:
• Change ProbEn to ProbeTrap in the EJTAG Debug entry vector location dis-
cussion.
• Add cache error and EJTAG Debug exceptions to the list of exceptions that
do not go through the general exception processing mechanism.
• Fix incorrect branch offset adjustment in general exception processing
pseudo code to deal with extended MIPS16e instructions.
• Add ConfigVI to denote an instruction cache with both virtual indexing and
virtual tags.
• Correct XContext register description to note that both BadVPN2 and R
fields are UNPREDICTABLE after an address error exception.
• Note that Supervisor Mode is not supported with a Fixed Mapping MMU.
• Define TagLo bits 4..3 as implementation dependent.
• Describe the intended usage model differences between Reset and Soft Reset
Exceptions.
• Correct the minimum number of TLB entries to be 3, not 2, and show an
example of the need for 3.
• Modify the description of PageMask and the TLB lookup process to
acknowledge the fact that not all implementations may support all page sizes.
Update the specification with the changes introduced in Release 2 of the Archi- tecture. Changes in this revision include:
• The following new Coprocessor 0 registers were added: EBase, HWREna,
IntCtl, PageGrain, SRSCtl, SRSMap.
• The following Coprocessor 0 registers were modified: Cause, Config,
Config2, Config3, EntryHi, EntryLo0, EntryLo1, PageMask, PerfCnt, Status,
WatchHi, WatchLo.
• The descriptions of Virtual memory, exceptions, and hazards have been
updated to reflect the changes in Release 2.
• A chapter on GPR shadow regsiters has been added.
• The chapter on CP0 hazards has been completely rewriten to reflect the
Release 2 changes.
1.90
September 1, 2002
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Revision History
Revision
2.00
Date
June 9, 2003
Description
Complete the update to include Release 2 changes. These include:
• Make bits 12..11 of the PageMask register power up zero and be gated by 1K page enable. This eliminates the problem of having these bits set to 0b11 on a
Release 2 chip in which kernel software has not enabled 1K page support.
• Correct the address of the cache error vector when the BEV bit is 1. It should
be 0xBFC0.0300,. not 0xBFC0.0200.
• Correct the introduction to shadow registers to note that the SRSCtl register
is not updated at the end of an exception in which StatusBEV = 1.
• Clarify that a MIPS16e PC-relative load reference is a data reference for the
purposes of the Watch registers.
• Add note about a hardware interrupt being deasserted between the time that
the processor detects the interrupt request and the time that the software interrupt handler runs. Software must be prepared for this case and simply dismiss the interrupt via an ERET.
• Add restriction that software must set EBase15..12 to zero in all bit positions less than or equal to the most significant bit in the vector offset. This is only required in certain combinations of vector number and vector spacing when using VI or EIC Interrupt modes.
• Add suggested software TLB init routine which reduced the probability of triggering a machine check.
Changes in this revision:
• Correct the encoding table description for the CausePCI bit to indicate that the
bit controlls the performance counter, not the timer interrupt.
• Correct the figure Interrupt Generation for External Interrupt Controller
Interrupt Mode to show CauseIP1..0 going to the EIC, rather than StatusIP1..0
• Update all files to FrameMaker 7.1.
• Update reset exception list to reflect missing Release 2 reset requirements.
• Define bits 31..30 in the HWREna register as access enables for the imple-
mentation-dependent hardware registers 31 and 30.
• Add definition for Coprocessor 0 Enable to Operating Modes chapter.
• Add K23 and KU fields to main Config register definition as a pointer to the
Fixed Mapping MMU appendix.
• Add specific note about the need to implement all shadow sets between 0 and
HSS – no holes are allowed.
• Change the hazard from a software write to the SRSCtlPSS field and a
RDPGPR and WRPGPR and instruction hazard vs. an execution hazard.
• Correct the pseudo-code in the cache error exception description to reflect the
Release 2 change that introduced EBase.
• Document that EHB clears instruction state change hazards for writes to
interrupt-related fields in the Status, Cause, Compare, and PerfCnt regis-
ters.
• Note that implementation-dependent bits in the Status and Config registers
should be defined in such a way that standard boot software will run, and that software which preserves the value of the field when writing the registers will also run correctly.
• With Release 2 of the Architecture the FR bit in the Status register should be a R/W bit, not a R bit.
• Improve the organization of the CP0 hazards table, and document that DERET, ERET, and exceptions and interrupts clear all hazards before the instruction fetch at the target instruction.
• Add list of MIPS® MT CP0 registers and MIPS MT and MIPS® DSP present bits in the Config3 register.
2.50
July 1, 2005
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Revision
2.60
2.61 2.62 2.70
2.71
2.72
2.73 2.74
2.75
2.80
Date
Jun 25, 2008
August 01, 2008 January 2,009 January 22, 2009
January 28, 2009
April 20, 2009
April 22, 2009 June 03, 2009
June 12, 2009
July 20, 2009
Description
Changes in this revision:
• Add the UserLocal register and access to it via the RDHWR instruction. • Operating Modes – footnote about ksseg/sseg
• COP3 no longer usable for customer extensions
• EIC Mode allows VectorNum != RIPL
• CP0Regs Table – added missing EJTAG & PDTrace Registers
• C0_DataLo/Hi are actually R/W
• Hazards table – added a bunch of missing ones
• Various typos fixed.
• In the Status register description, the ERL behavior description was incor- rect in saying only 29bits of kuseg becomes uncached&unmapped.
• CCRes is accessed through $3 not $4 – HWENA register affected. • PCTD bit added to C0_PerfCtl.
MIPS Technologies-only release for internal review:
• Added CP0 Reg 31, Select 2 & 3 as kernel scratch registers.
• Added VTLB/FTLB optional MMU configuration to Appendix A and
Config4 register for these new MMU configurations
• Added CDMM chapter, CDMMBase COP0 Register, CDMM bit in
C0_Config3, FDCI bit in C0_Cause register and IPFDC field in IntCtl reg- ister.
MIPS Technologies-only release for internal review:
• EIC mode – revision 2.70, was actually missing the new option of EIC driv-
ing an explicit vector offset (not using VectorNumbers).
• Clarified the text and diagrams for the 3 EIC options – RIPL=VectorNum,
Explicit VectorNum; Explicit VectorOffset.
MIPS Technologies-only release for internal review:
• Table was incorrectly saying ECRProbEn selected debug exception Vector.
Changed to ECRProbTrap.
• Added MIPS Technologies traditional meanings for CCA values.
• Added list of COP2 instruction to COPUnusable Exception description.
• Added statement that only uncached access is allowed to CDMM region.
• Updated Exception Handling Operation pseudo-code for EIC Option_3 (EIC
sends entire vector).
MIPS Technologies-only release for internal review:
• Fixed comments for ASE.
MIPS Technologies-only release for internal review:
• Added CDMM Enable Bit in CDMMBase COP0 register
• Reserved CCA values can be used to init TLB; just can’t be used for map-
ping.
MIPS Technologies-only release for internal review:
• CDMMBase_Upper_Address Field doesn’t have a fixed reset value.
• Added DSP State Disabled Exception to C0_Cause Exception Type table.
• FTLB and VTLB MMU configuration denoted by 0x4 in ConfigMT • Added TLBP -> TLBWI hazard
• Added KScrExist field in Config4.
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Revision History
Revision
2.81
2.82 3.00
3.05
3.10 3.11
3.12
Date
September 22, 2009
January 19, 2010 March 8, 2010
July 07, 2010
July 27, 2010 April 24, 2011
April 28, 2011
Description
MIPS Technologies-only release for internal review:
• ContextConfig Register description added.
• Context Register description updated for SmartMIPS behavior.
• EntryLo* register descriptions updated for RI & XI bits.
• TLB description and pseudo-code updated for RI & XI bits.
• PageMask register updated for RIE and XIE bits.
• Config3 register updated for CTXTC and RXI bits.
• Reserve MCU ASE bits in C0_Cause and C0_Status.
• Clean up description for KScratch registers – selects 2&3 are recommended,
but additional scratch registers are allowed.
MIPS Technologies-only release for internal review: • Added Debug2 register.
• RI/XI feature moved from SmartMIPS ASE.
• microMIPS features added
• MCU ASE features added.
• XI and RI exceptions can be programmed to use their own exception codes
instead of using TLBL code.
• XI and RI can be independently implemented as XIE and RIE bits are
allowed to be Read-Only.
• TCOpt Register added to C0 Register list.
• Added encoding (0x7) for 32 sets for one cache way.
• CMGCRBase register added.
• Lower bits of C0_Context register allowed to be write-able if
Config3.CTXTC=1 and Config3.SM=0.
• Explain the limits of the BadVPN2 field within Context register and the rela- tionships with the writeable bits within ContextConfig register.
MIPS Technologies-only release for internal review:
• FPR registers are UNPREDICTABLE after change of Status.FR bit.
• 1004K did not support CCA=0
• Config4 – KScratch Registers, mention that select 1 is reserved for future
debugger use.
• Context Register – the bit subscripts describing which VA bits go into the
BadVPN2 field was incorrect for the case when the ContextConfig register is used. The correct VA bits are 31:31-((X-Y)-1) for MIPS32.
• Changes for MIPS64, no changes for MIPS32.
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