嵌入式系统代写代做代考 Embedded Systems Reconfigurable computing

Reconfigurable computing

Small Embedded Systems

Unit 2.3 Processor Hardware

Introduction
Instructions and data
The instruction cycle
Constituents of the CPU

Instructions and Data
All instructions are encoded as binary words
Each instruction is at a location in memory
All data items are encoded as binary words
Each program variable is at a location in memory
Microcontrollers usually use the Harvard architecture
Instructions and data are in separate memories and separate address spaces

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

The Instruction Cycle
The cycle to process an instruction is:
Fetch the instruction from the program memory

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

The Instruction Cycle
The cycle to process an instruction is:
Fetch the instruction from the program memory
Decode the instruction
Figure out what it does and what operands it needs

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

The Instruction Cycle
The cycle to process an instruction is:
Fetch the instruction from the program memory
Decode the instruction
Fetch the operands

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

The Instruction Cycle
The cycle to process an instruction is:
Fetch the instruction from the program memory
Decode the instruction
Fetch the operands
Perform the computation

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

The Instruction Cycle
The cycle to process an instruction is:
Fetch the instruction from the program memory
Decode the instruction
Fetch the operands
Perform the computation
Write the result back to memory

Central Processing Unit

Data Memory
Data
Address

Program memory

Data
Address

Pipelining

Pipelining is a technique used to speed up processing
Start an instruction before its predecessor is complete
This approach only works well if each instruction is one word long and takes one clock cycle for each stage
If a single instruction is many words in size, it takes many clock cycles to load
Whole pipeline goes at speed of slowest stages

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6
Fetch 1 Decode 1 Operands 1 Execute 1 Write back 1
Fetch 2 Decode 2 Operands 2 Execute 2 Write back 2
Fetch 3 Decode 3 Operands 3 Execute 3
Fetch 4 Decode 4 Operands 4

Making Processors Pipeline-Friendly
There are two approaches to design of instruction set architecture
CISC (Complex Instruction Set Computer)
Instructions can be any length
Instructions can be any format
Instructions can take any number of clock cycles to complete
Very difficult for pipelines to handle
RISC (Reduced Instruction Set Computer).
Instructions are one word long
Instructions have similar formats
Instructions take one clock cycle to execute

The Central Processing Unit (CPU)
Key parts of CPU:
Arithmetic Logic Unit (ALU) computes results of instructions
General purpose registers each hold a word of data ready for processing by the ALU
Control unit sets switches around computer that steer items to where they need to be

Control unit

General purpose registers
PC
IR
SP
MAR
MDR
SR
ALU

The Central Processing Unit (CPU)
Key registers of CPU:
PC : register holds address of next instruction
MAR: register holds address issued to address bus
MDR: register that exchanges data with the data bus
IR: holds the currently executing instruction
SP: holds the current address of the top of the stack
SR: holds the status bits

Control unit

General purpose registers
PC
IR
SP
MAR
MDR
SR
ALU
Program counter
Memory address register
Memory data register
Instruction register
Stack pointer
Status register

Summary
CPU runs instruction cycle to fetch instructions and operands and to write results to memory
Instruction cycle is often pipelined in modern processors
RISC is a set of restrictions on instruction type, format and memory access modes to ensure that code pipelines well
CPU consists of ALU, general purpose registers and registers that handle housekeeping of computer operation

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