程序代写代做代考 Lectures for 2nd Edition

Lectures for 2nd Edition

Reading: 4.4
EEE 230
Single Cycle Control

Need to control
Register write
Memory access
ALU operation
ALU source
Register write source
Register write destination
Overview
2

Components of a Computer

3

Note the Control Lines
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3 June, 2016
Chapter 4 — The Processor
4

ALU used for
Load/Store: add
Branch: subtract
R-type: depends on function field
ALU Control
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
5

Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
ALU Control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
6

Control signals derived from instruction
The Main Control Unit
0
rs
rt
rd
shamt
funct
31:26
5:0
25:21
20:16
15:11
10:6
35 or 43
rs
rt
address
31:26
25:21
20:16
15:0
4
rs
rt
address
31:26
25:21
20:16
15:0
R-type
Load/
Store
Branch

opcode
always read
read, except for load
write for R-type and load

sign-extend and add

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
7

Datapath With Control

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
8

R-Type Instruction

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
9

Load Instruction

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3 June, 2016
Chapter 4 — The Processor
10

Branch-on-Equal Instruction

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
11

Jump uses word address
Update PC with concatenation of
Top 4 bits of old PC
26-bit jump address
00
Need an extra control signal decoded from opcode
Implementing Jumps
2
address
31:26
25:0
Jump
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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
12

Datapath With Jump Added

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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
13

Longest delay determines clock period
Critical path: load instruction
Instruction memory  register file  ALU  data memory  register file
Not feasible to vary period for different instructions
Violates design principle
Making the common case fast
We will improve performance by pipelining
Performance Issues
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Morgan Kaufmann Publishers
3 June, 2016
Chapter 4 — The Processor
14

Opcode determines control
Function code needed for ALU control
Need to prevent updates to registers and memory is not required by instructions
Clock cycle time is determined by longest path
Need to complete all actions
lw
15
Review

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