L1 MOV R2, #0 L2
;x==0x30
; if TRUE execute s0 ;x==0x31
; if TRUE execute s0 ;x>=0x40
; if FALSE execute s1 else s0 ; y = 1 (s0)
; skip s1
; y = 0 (s1)
if (((x >= 0x30) && (x <= 0x39)) || ((x >= 0x41) && (x <= 0x5a))) {
y = 1; } else {
y = 0;
CMP BLT CMP BLE
L0 CMP BLT
CMP
BGT
L1 MOV
// s0 // s1
R1, #0x30 L0
R1, #0x39 L1
R1, #0x41 L2
R1, #0x5a L2
R2, #01
}
B
L2 MOV R2, #0
L3
;x>=0x30
; if FALSE check ((x >= 0x41) && (x <= 0x5a)) ;x<=0x39
; if TRUE execute s0
;x>=0x41
; if FALSE execute s1
;x<=0x5a
; if FALSE execute s1 else s0
; y = 1 (s0)
; skip s1
; y = 0 (s1)
L3
1
CS1021 Tutorial 4 2018 jones@scss.tcd.ie
CS1021 Tutorial 4 Condition Code Flags
Q1 Translate following pseudo-code statement into a sequence of ARM assembly language instructions. Assume that x and y are signed integers in R1 and R2 respectively.
if ((x == 0x30) || (x == 0x31) || (x >= 0x40)) {
y = 1; } else {
y = 0;
CMP BEQ CMP BEQ CMP BLT
L0 MOV B
// s0 // s1
R1, #0x30 L0
R1, #0x31 L0
R1, #0x40 L1
R2, #01 L2
}
Q2 For each ARM Assembly Language code segment below, determine the value stored in R0 and the state of the N (Negative), Z (Zero), C (Carry) and V (oVerflow) flags after the instructions have been executed
(i) LDR
LDR R1, =0x00000001 ADDS R0, R0, R1
R0, =0x00000000
(ii) LDR
LDR R1, =0x00000000 SUBS R0, R0, R1
; 0x00000001 N=0, Z=0, C=0, V=0 (0)
; 0x00000001 N=0, Z=0, C=1, V=0 (2)
; 0x00000001 N=0, Z=0, C=1, V=1 (3)
; 0x00000000 N=0, Z=1, C=1, V=0 (6)
; 0x00000000 N=0, Z=1, C=0, V=0 (4)
; 0x00000000 N=0, Z=1, C=1, V=0 (6)
; 0x00000000 N=0, Z=1, C=1, V=1 (7)
; 0x80000000 N=1, Z=0, C=1, V=0 (10)
R0, =0x00000001
(iii) LDR
LDR R1, =0x80000001 ADDS R0, R0, R1
R0, =0x80000000
(iv) LDR
LDR R1, =0x00000000 SUBS R0, R0, R1
CS1021 Tutorial 4 2018 jones@scss.tcd.ie
R0, =0x00000000
(v) LDR
LDR R1, =0x00000000 ADDS R0, R0, R1
R0, =0x00000000
(vi) LDR
LDR R1, =0x80000000 SUBS R0, R0, R1
R0, =0x80000000
(vii) LDR
LDR R1, =0x80000000 ADDS R0, R0, R1
R0, =0x80000000
(viii) LDR
LDR R1, =0x00000000 SUBS R0, R0, R1
R0, =0x80000000
2
if (x == y) { z = 1;
} else { z =0;
}
//
// s0 //
// s1
;
; compare MS 32-bits of x and y
; if different, now know x != y so execute s1
; if equal, need to compare LS 32 bits to determine if x != y ;
if (x < y) { z = 1;
} else { z =0;
}
//
// s0 //
// s1
CMP R0, R2 BNE L2 CMP R1, R3 BNE L2
; compare MS 32-bits ;ifR0!=R2executes1
; MS 32-bits equal, compare LS 32-bits ;ifR1!=R3executes1
;z=1(s0)
; skip s1
;z=0(s1)
L1 MOV
B L3
L2 MOV R4, #0 L3
R4, #01
;
; compare MS 32-bits of x and y
; if different, now know if x < y or x > y
; if equal, need to compare LS 32 bits to determine if x < y ;
CMP R0, R2 BLT L1 BGT L2 CMP R1, R3 BHS L2
; compare MS 32-bits
; if R0 < R1 execute s0 (signed branch)
; if R0 > R1 execute s1 (signed branch)
; MS 32-bits equal, compare LS 32-bits
; if R1 >= R3 execute s1 (unsigned branch) ;z=1(s0)
; skip s1
;z=0(s1)
L1 MOV
B L3
L2 MOV R4, #0 L3
R4, #01
3
CS1021 Tutorial 4 2018 jones@scss.tcd.ie
Q3 If x and y are signed 64-bit integers in R0:R1 and R2:R3 respectively and z is an integer in R4, translate the following pseudo-code statements into a sequence of ARM assembly language instructions