MEMORY
CS1021 AFTER READING WEEK Mid-Semester Test
• NOW Thurs 8th Nov @ 9am in Goldsmith Hall (ALL students to attend at 9am) Final 2 Labs
• Lab5 2-Nov-18, due 16-Nov-18 (2 weeks duration)
• Lab6 16-Nov-19, due 30-Nov-18 (2 weeks duration)
End of Semester Exam
• written 2 hour exam (week of 12-Dec-18)
• answer 3 out of 4 questions (not 2 out of 3 as in recent CS1021 exams)
• 40 mins per question
• questions similar to previous CS1021 exams (shorter, less parts)
Yet to cover
• reading and writing to memory, stacks and subroutines CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
ARM Memory System
• ARM system comprises CPU and memory
• instructions and data stored in memory
• CPU can read (LOAD) data from memory into a register
• CPU can write (STORE) data from a register into memory
• called a load / store architecture
• to operate on data in memory, the data must first be loaded into register(s), updated in the registers and then stored back to memory
MEMORY
32 32
bus
address data
registers
CPU
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Memory Revision
• memory comprises an array of memory locations
• each location stores a byte of data
• each location location has a unique 32 bit address
0x00000000 to 0xFFFFFFFF
• the address space, 232 bytes (4GB), is the amount of memory that can be physically attached to the CPU
0xFFFFFFFF 0xFFFFFFFE 0xFFFFFFFD 0xFFFFFFFC
0x00000005 0x00000004 0x00000003 0x00000002 0x00000001 0x00000000
memory as an array of BYTEs
0xFF
0xEE
0xDD
0xCC
0x05
0x04
0x11
0x22
0x33
0x44
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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…
MEMORY
Memory Revision…
• often easier to view memory as an array of WORDs (32 bits) rather than an array of BYTEs
• as each WORD location is aligned on a 4 byte boundary, the low order 2 bits of each address is 0
• making a comparison with the previous slide, the byte of data stored at memory location 0 is the least significant byte of the WORD stored in location 0
• this way of storing a WORD is termed LITTLE ENDIAN – the least significant byte is stored at the lowest address (the other way is BIG ENDIAN)
• ARM CPUs can be configured to be LITTLE ENDIAN or BIG ENDIAN (term from Gulliver’s Travels)
0xFFFFFFFC 0xFFFFFFF8
0x0000000C 0x00000008 0x00000004 0x00000000
memory as an array of WORDs
0xFFEEDDCC
0xF8F8F8F8
0x87654321
0 x 8 A BC D E F 0
0x07060504
0x11223344
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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…
MEMORY
NXP LPC2468 Memory Map
0xFFFFFF FF
64K RAM
512K flash memory
• address space NOT fully populated with memory devices
• 512K of flash memory at address 0x00000000 to 0x0007FFFF
• 64K RAM at address 0x40000000 to 0x4000FFFF
• flash memory
read ONLY (programmed electronically – “flashed”) retains data when power removed
• RAM (random access memory) read write
0x4000FFFF 0x40000000
0x0007FFFF
looses its data when power removed
• uVision projects are configured to simulate this memory map
• code placed in flash memory starting at address 0x00000000 CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
0x00000000
NXP LPC2468 memory map (NOT to scale)
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MEMORY
Load Instructions – LDR and LDRB • memory address specified in a register
• load word
LDR R1, =0x40000000
LDR R0, [R1]
• load byte
; R1 -> 0x40000000 (in RAM) ; R0 = MWORD[0x40000000]
R1 points to 0x40000003 (in RAM)
; R1 -> 0x40000003 (in RAM) ; R0 = MBYTE[0x40000003]
LDR
LDRB R0, [R1]
R1, =0x40000003
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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R1 points to 0x40000000 (in RAM)
load data from 0x40000000 (in RAM)
load data from 0x40000003 (in RAM)
MEMORY
LDR and LDRB
• load word
reads 4 bytes from memory address into a register
address must be even (LS address bit = 0)
normally used with an address aligned on a 4 byte boundary (address ends with …002) BUT …
if address end with …102, it accesses memory as though the address ended with …002 but swaps the high and low 16 bits
• load byte
reads byte from memory address and stores in LS byte of register
clears MS bytes of register
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
LDR and LDRB… • load word
LDR R1, =0x40000000 LDR R0, [R1]
• load byte
LDR R1, =0x40000003
R0 0x00000004 • load word (address ends with ..102)
0x0F0E0D0C
0x0B0A0908
0x07060504
0x04030201
R0 0x04030201
0x4000000C 0x40000008 0x40000004 0x40000000
LDRB R0, [R1]
memory
little endian
0x01 in address 0x40000000 0x04 in address 0x40000003
LDR R1, =0x40000002 LDR R0, [R1]
R0 0x02010403
high and low 16 bits swapped
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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… …
MEMORY
Store Instructions – STR and STRB • memory address specified in a register
• store word
LDR R1, =0x40000000
STR R0, [R1] • store byte
LDR R1, =0x40000001 STRB R0, [R1]
R1 points to 0x40000000 (in RAM) ; R1 -> 0x40000000 (in RAM)
; MWORD[0x40000000] = R0
R1 points to 0x40000002 (in RAM) ; R1 -> 0x40000002 (in RAM)
; MBYTE[0x40000002] = R0 (LS byte)
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
STR and STRB
• store word
writes ALL 4 bytes of register to memory address
address must be aligned on a 4 byte boundary (address ends with …002)
• store byte
writes LS byte of register to memory address
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example
• a, b and c are 32-bit signed binary integers stored in memory locations 0x40000000, 0x40000004 and 0x40000008 respectively
• computec=a+b
LDR R1, =0x40000000 LDR R0, [R1]
LDR R1, =0x40000004 LDR R1, [R1]
ADD R0, R0, R1
LDR R1, =0x40000008 STR R0, [R1]
R1 points to 0x40000000 (where a is stored in RAM)
; R1 -> a
; R0 = a
; R1 -> b
; R1 = b
; R0 = a + b ; R1 -> c
; c = a + b
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
ASCII strings
• American Standard Code for Information Interchange
• ASCII is a standard used to encode alphanumeric and other characters
• each character is stored as a single byte (8 bits)
• upper and lower case characters have different ASCII codes
• ASCII only uses 7 bits to encode the character, giving 128 possible characters
• MSB may be used as a parity bit
• ODD or EVEN parity
• parity bit set so that number of 1 bits in a character is either odd or even
• used to detect transmit and receive errors
• originally used to transmit characters from a computer to a tele printer (terminal) CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
ASCII Table (hex values)
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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ASCII
‘H’ = 0x48 ‘e’ = 0x65
‘l’ = 0x6C ‘o’ = 0x6F
MEMORY
ASCII …
• the string “Hello”, if at address 0x1000, stored as follows
H
e
l
l
o
NUL
0x48
0x65
0x6c
0x6c
0x6f
0x00
0x1000
0x1001
0x1002
0x1003
0x1004
0x1005
ASCII code address
• ASCII strings early always NUL terminated
• only 96 ASCII characters are printable, the remainder are control codes
• example control codes
0x0A LF 0x0D CR
0x08 BS
0x09 HT
0x1B ESC
0x00 NUL
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
line feed carriage return backspace horizontal tab escape
NUL
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MEMORY
Example
• copy a NULL terminated ASCII string from 0x1000 (in read-only flash memory) to
0x40000000 (RAM)
LDR R1, =0x1000
LDR R2, =0x40000000
R1 points to src string in RAM
L LDRB
STRB R0,
ADD R1, ADD R2, CMP R0, BNE L
R1, #1 R2, #1 #0
R0, [R1] [R2]
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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; R1 -> src
; R2 -> dst
; get char from src string
; store char in dst string
; move to next src char
; move to next dst char
; char == 0 ?
; next character if not finished
R2 points to dst string in RAM
MEMORY
CS1021 Mid-Semester Test
• Thurs 8th Nov @ 9am in Goldsmith Hall
• ALL students to attend at 9am (no Tutorial @ 13.00)
• NO calculators, phones, laptop etc.
• 20 Questions (like Tutorial questions)
• ALL questions carry equal marks (some are easier than others)
• Remember to fill in exam number, student ID and name on answer booklet
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
uVision Console and Memory Windows
console window (UART #1) [View][Serial Windows][UART #1]
memory window
[View][Memory Windows][Memory 1]
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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memory address
memory data
ASCII bytes for “0123456” + 0x0D (CR)
MEMORY
DCB, DCW and DCW Assembler Directives
• •
can use assembler to initialise the contents of flash memory with constant data
if RAM needs to be initialised, it is normally initialised at start-up by copying data from flash memory (very microcontroller centric)
•
•
load address of constant string using points to
LDR R0, =C0 ; R0 -> “Hello World!”
C0 DCB
C1 DCD
C2 DCW
“Hello World!”, 0 1, 2, 3, 4, 5, 6, 7, 8 1, 2, 3, 4, 5, 6, 7, 8
; NUL terminated ASCII string
; 8 x 32-bit (word) constants (why DCD for words?) ; 8 x 16-bit (halfword) constants
need to place constants where they will not be mistakenly executed as code CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
DCB, DCW and DCW Assembler Directives …
constant data stored in memory @ address 0x50
C1 @ address = 0x60
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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C2 @ address = 0x80
C0 @ address = 0x50 (padded to be a multiple of 4 bytes)
MEMORY
Additional features of LDR / STR instructions
• additional features can be used to reduce the number of instructions that have to be written and the number of instructions executed at runtime
• LDR R0, [R1] ; R1 used as an address register as R1 contains an address
• STR R0, [R1] ; R1 used as an address register as R1 contains an address
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Some Advanced features of LDR / STR instructions
• best understood by examining LDR / STR machine code fields
32 bits
4 2111111 4 4 12
LDR STR machine code fields
• I – immediate bit
if 0, offset field specifies a 12 bit offset (0 .. 4095)
if 1, offset field specifies a register + shift operation
• P – pre or post indexing
if 0 (post indexing), add offset to base register after transfer if 1 (pre indexing), add offset to base register before transfer
• U (up/down) – 0 for subtract and 1 to add offset to base register
• B – 0 for word and 1 for byte transfer
• W – 1 for write back of effective address into base register
• L – 0 for store and 1 for load
condition
0
1
I
P
U
B
W
L
Rn
Rd
offset
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Examples
immediate offset
I
P
U
B
W
L
offset
0
1
1
0
0
1
4
• LDR
R0, [R1, #4]
R0 = MEM[R1 + 4]
R0, [R1], #4
R0 = MEM[R1] R1 = R1 + 4
; with immediate offset
I
P
U
B
W
L
offset
0
0
1
0
1
1
4
• LDR
; post-indexed
; post increment address register
I
P
U
B
W
L
Offset
0
1
0
0
1
1
4
• LDR
can specify a +ve or -ve offset
R0, [R1, #-4]! ; pre-indexed
R1 = R1 – 4 ; pre increment address register R0 = MEM[R1]
•
LDR can read memory and increment address register in a single instruction CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Examples…
register offset
I
P
U
B
W
L
offset
1
1
1
0
0
1
R4
• LDR
• LDR
R0, [R1, R4]
R0 = MEM[R1 + R4]
R0, [R1], R4
R0 = MEM[R1] R1 = R1 + R4
; register offset
; register offset post-indexed
; post increment address register
I
P
U
B
W
L
offset
1
0
1
0
1
1
R4
I
P
U
B
W
L
offset
1
1
1
0
1
1
R4
• LDR
can specify a +ve or -ve offset
R0, [R1, -R4]! ; pre-indexed register offset
R1 = R1 – R4 ; pre increment address register R0 = MEM[R1]
• LDR can read memory and increment address register in a single instruction CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Examples…
scaled register offset
• LDR
• LDR
R0, [R1, R4, LSL #2] ; scaled register offset R0 = MEM[R1 + R4*4]
R0, [R1], R4, LSL #2 ; post-indexed scaled register offset
R0 = MEM[R1] R1 = R1 + R4*4
can specify a +ve or -ve offset
R0, [R1, -R4, LSL #2]! ; pre-indexed scaled register offset R1 = R1 – R4*4
R0 = MEM[R1]
I
P
U
B
W
L
offset
1
1
1
0
0
1
R4, LSL #2
I
P
U
B
W
L
offset
1
0
1
0
1
1
R4, LSL #2
• LDR
I
P
U
B
W
L
offset
1
1
1
0
1
1
-R4, LSL #2
• LDR can read memory and increment address register in a single instruction CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 1: string copy
• copy a NULL terminated ASCII string from 0x1000 (in read-only flash memory) to
0x40000000 (RAM)
LDR R1, =0x1000
LDR R2, =0x40000000
points to
; R1 -> src string
; R2 -> dst string
; load ch from src string AND post increment R1 ; store ch in dst string AND post increment R2
; ch == 0? has NUL ch been copied?
; next ch if NOT finished
post increment R1 post increment R2
L LDRB
STRB R0,
CMP R0, BNE L
#0
R0, [R1], #1 [R2], #1
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 2: c = a + b
• a, b and c are 32-bit signed binary integers stored in memory locations 0x40000000, 0x40000004 and 0x40000008 respectively
• computec=a+b
LDR R1, =0x40000000 LDR R0, [R1], #4
LDR R2, [R1], #4
ADD R0, R0, R2
STR R0, [R1]
post increment R1
; R1 -> a
; R0 = a; R1 = R1 + 4 -> b ; R2 = b; R1 = R1 + 4 -> c ; R0 = a + b
; c = a + b
• exploiting (1) a, b and c are stored in sequential memory locations AND (2) can post increment R1 as part of LDR instruction
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 3: reverse string
• if a zero terminated string of ASCII characters is stored at memory address 0x40000000, write ARM assembly language instructions to reverse the string in situ
• step 1: find R2 such that R2->last ch in string (excluding terminating 0)
;
; R1 -> first ch in string ;
LDR R1, =0x40000000 MOV R2, R1
post increment R1
; R1 -> string
; R2 -> string
; load next ch of string AND R2 = R2 + 1
; 0?
; next ch
; R2 -> last ch of string (excluding terminating 0)
decrement R2 by 2 as R2 was one past NUL terminator
L0 LDRB
CMP R0, #0
BNE L0
SUB R2, R2, #2
R0, [R2], #1
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 3: reverse string …
•
step 2: swap first and last characters and work towards middle
0x30
0x31
0x32
0x33
0
0x40000000
R1
R2
0x33
0x31
0x32
0x30
0
0x40000000
R1
R2
0x33
0x32
0x31
0x30
0
0x40000000
• loop terminating condition CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
R2 <= R1
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MEMORY
Example 3: reverse string ...
;
; R1 -> first ch in string
; R2 -> last ch in string (excluding termination zero) ;
; swap first and last characters and work towards middle ;
L1 CMP
R2, R1 BLS L2
; if R2 <= R1? ...
; finished
; read “first” character
; read “last” character
; write “first” character to “last” slot ; write “last” character to “first” slot
post increment R2 by - 1 post increment R1 by 1
LDRB R0, [R1] LDRB R3, [R2] STRB R0, [R2], #-1 STRB R3, [R1], #1 B L1
L2
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 4: Array Access
• consider an array a of 32-bit signed integers stored in memory at address 0x40000000
int a[256]; // array a contains 256 integers a[0] .. a[255]
a[0] stored @ MEM[0x40000000] a[1] stored @ MEM[0x40000004] a[2] stored @ MEM[0x40000008] ...
// increasing by 4...
// because each integer
// occupies 4 bytes of memory
a[n] stored @ MEM[0x40000000 + 4*n] // ...
a[255] stored @ MEM[0x400003FC] //
• array a occupies 256 x 4 = 1024 = 0x400 bytes of memory
• array a occupies memory locations 0x40000000 to 0x400003FF
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
Example 4: Array Access ...
• array elements stored in consecutive memory locations
• as each array element is a 32 bit integer (4 bytes), address increases by 4 from one element to the next
a[0]
a[1]
a[2]
a[3]
a[254]
a[255]
0x40000000 0x40000004 0x40000008 0x4000000C
... a[n] ... 0x40000000 + 4*n
0x400003F8 0x400003FC
• if i and j are two 32-bit signed integer variables stored at memory addresses 0x40000400 and 0x40000404 respectively, write ARM assembly language instructions to compute:
31
a[i] = a[5] + a[j];
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
MEMORY
Example 4: Array Access...
• a[5] - constant index
• a[i] and a[j] - variable indices
LDR R1, =0x40000000 LDR R0, [R1, #5*4] LDR R2, =0x40000404 LDR R2, [R2]
LDR R2, [R1, R2, LSL #2] ADD R0, R0, R2
LDR R2, =0x40000400 LDR R2, [R2]
STR R0, [R1, R2, LSL #2]
constant offset
scaled register offset
// R1 -> a
// R0 = a[5] (R0 = MEM[a + 5*4])
// R2 -> j
// R2 = j
// R2 = a[j] (R2 = MEM[a + j*4])
// R0 = a[5] + a[j]
// R2 -> i
// R2 = i
// a[i] = a[5] + a[j] (MEM[a + i*4] = R0)
scaled register offset
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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MEMORY
What has not been covered?
• LDRH
• STRH
• LDRSB
• LDRSH
load halfword store halfword
load byte with sign extend load halfword with sign extend
CS1021 © 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College Dublin 13-Nov-18
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