Requirements
You are required to implement a single cycle data path for a 32-bit MIPS processor in Verilog. You
may refer to figure 4.24 in Computer Organization and Design 4th edition (available electronically
in the UTas library). You will be given a test bench file along with some modules and will need to
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implement the following modules yourself:
Control (including the following instructions: r-type, lw, sw, beq, j, addi)
ALU Control
ALU (you may extend/modify your final ALU from prac 1)
Single Cycle Datapath (including variables, wiring and multiplexing – some parts have
already been implemented to get you started)
You must write a test programme, compile it to machine language in hexadecimal format (you
may do this in MARS or any other MIPS compiler), load and run this programme in the provided
MIPSSingleCycle tb. v test bench file. Another test bench is also provided to assist you in
testing your ALU; you may wish to extend this if you have other test cases you’d like to test.
Make sure you have a look at the test bench since it implements memory management and your
data path will need to be built accordingly.
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