x86 Programming III CSE 351 Autumn 2016
Roadmap
1
car *c = malloc(sizeof(car));
c->miles = 100;
c->gals = 17;
float mpg = get_mpg(c);
free(c);
Car c = new Car();
c.setMiles(100);
c.setGals(17);
float mpg =
c.getMPG();
Java:
C:
Assembly language:
Machine code:
0111010000011000
100011010000010000000010
1000100111000010
110000011111101000011111
Computer system:
OS:
Memory & data
Arrays & structs
Integers & floats
RISC V assembly
Procedures & stacks
Executables
Memory & caches
Processor Pipeline
Performance
Parallelism
CS295
L07 – RISC V Final
1
Stored-Program Concept
R-Format
I-Format
S-Format
SB-Format
U-Format
UJ-Format
Agenda
2
CS295
L07 – RISC V Final
So how do we represent instructions?
Remember: Computer only understands 1s and 0s, so assembler string “add x10,x11,x0” is meaningless to hardware
CS295
L07 – RISC V Final
Big Idea: Stored-Program Concept
programs can be stored in memory as numbers
Before: a number can mean anything
Now: make convention for interpreting numbers as instructions
4
INSTRUCTIONS ARE DATA
CS295
L07 – RISC V Final
Divide the 32 bits of an instruction into “fields”
regular field sizes → simpler hardware
will need some variation….
Instructions as Numbers
5
31
0
By convention, RISCV instructions are each
1 word = 4 bytes = 32 bits
CS295
L07 – RISC V Final
6 formats to memorize, but 4 formats to internalize (R with three registers, I with two registers and an immediate, S with two registers and an address, U with a big immediate/address)
5
The 6 Instruction Formats
R-Format: instructions using 3 register inputs
add, xor, mul —arithmetic/logical ops
I-Format: instructions with immediates, loads
addi, lw, jalr, slli
S-Format: store instructions: sw,sb
SB-Format: branch instructions: beq, bge
U-Format: instructions with upper immediates
lui, auipc —upper immediate is 20-bits
UJ-Format: the jump instruction: jal
CS295
L07 – RISC V Final
lui: load upper immediate
auipc: adding an upper immediate to PC and putting the result in a register
RISCV Instruction: add x5,x6,x7
Field representation (decimal):
Field representation (binary):
R-Format Example
7
two
0
0x33
7
6
0
5
31
0
0000000
0110011
00111
00110
000
00101
31
0
hex representation: 0x 0073 02B3
decimal representation: 7,537,331
Called a Machine Language Instruction
CS295
L07 – RISC V Final
x5 = t0, x6 = t1, x7 = t2
opcode (7): uniquely specifies the instruction
rs1 (5): specifies a register operand
rd (5): specifies destination register that receives result of computation
8
imm[11:0]
func3
rd
opcode
31
0
rs1
I-Format Instructions (3/4)
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L07 – RISC V Final
I-Format Instructions (4/4)
immediate (12): 12 bit number
All computations done in words, so 12-bit immediate must be extended to 32 bits
always sign-extended to 32-bits before use in an arithmetic operation
9
imm[11:0]
func3
rd
opcode
31
0
rs1
Can represent 212 different immediates
imm[11:0] can hold values in range [-211 , +211)
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L07 – RISC V Final
???
I-Format Example (1/2)
10
addi x15,x1,-50
rd = x15
rs1 = x1
???
?
???
???
31
0
00001
imm[11:0]
func3
rd
opcode
rs1
111111001110
01111
0
0x13
CS295
L07 – RISC V Final
Load Instructions are also I-Type
The 12-bit signed immediate is added to the base address in register rs1 to form the memory address
This is very similar to the add-immediate operation but used to create address, not to create final result
Value loaded from memory is stored in rd
11
imm[11:0]
func3
rd
opcode
31
0
rs1
offset[11:0]
width
dst
LOAD
base
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L07 – RISC V Final
11
I-Format Load Example
12
imm[11:0]
func3
rd
opcode
31
0
rs1
offset[11:0]
width
dst
LOAD
base
lw x14, 8(x2)
000000001000
010
01110
0000011
00010
imm=+8
LW
rd=14
LOAD
rs1=2
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L07 – RISC V Final
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S-Format Used for Stores
Store needs to read two registers, rs1 for base memory address, and rs2 for data to be stored, as well as need immediate offset!
Can’t have both rs2 and immediate in same place as other instructions!
Note: stores don’t write a value to the register file, no rd!
RISC-V design decision is move low 5 bits of immediate to where rd field was in other instructions – keep rs1/rs2 fields in same place
register names more critical than immediate bits in hardware design
13
imm[11:5]
opcode
rs2
rs1
func3
imm[4:0]
31
0
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L07 – RISC V Final
13
S-Format Example
sw x14, 8(x2)
14
imm[11:5]
opcode
rs2
rs1
func3
imm[4:0]
31
0
00000000
0100011
01110
00010
010
01000
off[11:5] = 0
STORE
rs2=14
rs1=2
SW
off[4:0] = 8
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L07 – RISC V Final
14
B-format is mostly same as S-Format, with two register sources (rs1/rs2) and a 12-bit immediate
But now immediate represents values -212 to +212-2 in 2-byte increments
The 12 immediate bits encode even 13-bit signed byte offsets (lowest bit of offset is always zero, so no need to store it)
RISC-V B-Format for Branches
15
imm[12|10:5]
opcode
rs2
rs1
func3
imm[4:1|11]
31
0
7
7
5
5
3
5
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L07 – RISC V Final
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Branch Example (1/2)
RISCV Code:
Loop: beq x19,x10,End
add x18,x18,x10
addi x19,x19,-1
j Loop
End:
Branch offset =
(Branch with offset of 0, branches to itself)
16
Start counting from instruction AFTER the branch
1
2
3
4
4×32-bit instructions = 16 bytes
CS295
L07 – RISC V Final
Branch Example (1/2)
RISCV Code:
Loop: beq x19,x10,End
add x18,x18,x10
addi x19,x19,-1
j Loop
End:
17
Start counting from instruction AFTER the branch
1
2
3
4
???????
1100011
01010
10011
000
?????
31
0
7
7
5
5
3
5
BRANCH
rs2=10
rs1=19
BEQ
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L07 – RISC V Final
U-Format for “Upper Immediate” instructions
Has 20-bit immediate in upper 20 bits of 32-bit instruction word
One destination register, rd
Used for two instructions
LUI – Load Upper Immediate
AUIPC – Add Upper Immediate to PC
18
imm[31:12]
opcode
rd
31
0
20
U-immediate[31:12]
7
LUI/AUIPC
5
dest
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18
lui writes the upper 20 bits of the destination with the immediate value, and clears the lower 12 bits
Together with an addi to set low 12 bits, can create any 32-bit value in a register using two instructions (lui/addi).
lui x10, 0x87654 # x10 = 0x87654000
addi x10, x10, 0x321 # x10 = 0x87654321
LUI to create long immediates
19
CS295
L07 – RISC V Final
UJ-Format Instructions (2/3)
jal saves PC+4 in register rd (the return address)
Set PC = PC + offset (PC-relative jump)
Target somewhere within ±219 locations, 2 bytes apart
±218 32-bit instructions
Reminder: “j” jump is a pseudo-instruction—the assembler will instead use jal but sets rd=x0 to discard return address
Immediate encoding optimized similarly to branch instruction to reduce hardware cost
20
imm[20|10:1|11|19:12]
opcode
rd
31
0
20
offset[31:12]
7
JAL
5
dest
CS295
L07 – RISC V Final
Uses of jalr
# ret and jr psuedo-instructions
ret = jr ra = jalr x0, ra, 0
# Call function at any 32-bit absolute address
lui x1,
jalr ra, x1,
# Jump PC-relative with 32-bit offset
auipc x1,
jalr x0, x1,
21
imm[11:0]
func3
rd
opcode
31
0
rs1
offset
0
dest
JALR
base
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L07 – RISC V Final
21
Summary of RISC-V Instruction Formats
22
CS295
L07 – RISC V Final
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